Fix UNF thread IDs in enum + improve some comments

This commit is contained in:
Arceveti
2024-03-18 22:56:34 -07:00
parent e84457b94a
commit c7d2e359a5
7 changed files with 15 additions and 9 deletions

View File

@@ -35,6 +35,8 @@ DEF_REGION_NAME(us);
DEF_REGION_NAME(eu);
#elif VERSION_SH
DEF_REGION_NAME(sh);
#elif VERSION_CN
DEF_REGION_NAME(cn);
#elif BBPLAYER
DEF_REGION_NAME(bb);
#else
@@ -274,7 +276,7 @@ static const char* sFltErrDesc[NUM_FLT_ERR] = {
[FLT_ERR_NAN ] = "NaN float",
};
//! TODO: NaN floats aren't detected here even though validate_float does, and this works with denorms.
//! TODO: NaN floats aren't detected here even though validate_f32 does, and this works with denorms.
enum FloatErrorType validate_floats_in_reg_buffer(void) {
enum FloatErrorType fltErrType = FLT_ERR_NONE;
@@ -285,7 +287,7 @@ enum FloatErrorType validate_floats_in_reg_buffer(void) {
IEEE754_f32 val = {
.asU32 = get_reg_val(reg.cop, reg.idx)
};
fltErrType = validate_float(val);
fltErrType = validate_f32(val);
if (fltErrType != FLT_ERR_NONE) {
break;

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@@ -88,7 +88,7 @@ static OSThread* get_crashed_thread(void) {
) {
if (
(thread->priority > OS_PRIORITY_IDLE ) &&
(thread->priority < OS_PRIORITY_APPMAX) && //! TODO: Should this include OS_PRIORITY_APPMAX threads? Official N64 games don't.
(thread->priority < OS_PRIORITY_APPMAX) && //! TODO: Should this include threads with priority OS_PRIORITY_APPMAX and higher? Official N64 games don't.
(thread->flags & (OS_FLAG_CPU_BREAK | OS_FLAG_FAULT)) &&
(thread != gCrashedThread)
) {

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@@ -461,8 +461,9 @@ static const FloatErrorPrintFormat sFltErrFmt[] = {
[FLT_ERR_NAN ] = { .r = 0xFF, .g = 0x7F, .b = 0x7F, .prefixChar = CHAR_FLT_PREFIX_NAN, .suffix = "NaN", },
};
//! TODO: Version of this but for f64.
size_t cs_print_f32(u32 x, u32 y, IEEE754_f32 val, _Bool includeSuffix) {
const enum FloatErrorType fltErrType = validate_float(val);
const enum FloatErrorType fltErrType = validate_f32(val);
size_t numChars = 0;
if (fltErrType != FLT_ERR_NONE) {

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@@ -366,7 +366,7 @@ void page_disasm_draw(void) {
sDisasmBranchStartX = (DISASM_BRANCH_ARROW_HEAD_SIZE + DISASM_BRANCH_ARROW_HEAD_OFFSET) +
cs_get_setting_val(CS_OPT_GROUP_PAGE_DISASM, CS_OPT_DISASM_OFFSET_ADDR)
? TEXT_X(INSN_NAME_DISPLAY_WIDTH + STRLEN("R0, R0, 0x80000000"))
? TEXT_X(INSN_NAME_DISPLAY_WIDTH + STRLEN("R0, R0, 0x80XXXXXX"))
: TEXT_X(INSN_NAME_DISPLAY_WIDTH + STRLEN("R0, R0, +0x0000"));
u32 line = 1;

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@@ -44,6 +44,8 @@
// MIPS III Instructions:
// https://n64brew.dev/wiki/MIPS_III_instructions
// https://hack64.net/docs/VR43XX.pdf
// Opcode instructions:
ALIGNED32 static const InsnTemplate insn_db_standard[] = { // INSN_TYPE_OPCODE
@@ -196,6 +198,7 @@ ALIGNED32 static const InsnTemplate insn_db_cop0_sub00[] = { // OPC_COP0, INSN_T
};
ALIGNED32 static const InsnTemplate insn_db_cop0_sub10[] = { // OPC_COP0, INSN_TYPE_FUNC
//! TODO: Find out the proper format for these?
//! TODO: These use the COP0 TLB Index register as the input/output.
{ .opcode = OPC_COP0_TLBP , .name = "TLBP" , .fmt = "\'" , .out = 0, }, // 8: Searches for a TLB entry that matches the EntryHi register.
{ .opcode = OPC_COP0_TLBR , .name = "TLBR" , .fmt = "\'" , .out = 0, }, // 1: Loads EntryHi and EntryLo registers with the TLB entry pointed at by the Index register.
{ .opcode = OPC_COP0_TLBWI , .name = "TLBWI" , .fmt = "\'" , .out = 0, }, // 2: Stores the contents of EntryHi and EntryLo registers into the TLB entry pointed at by the Index register.
@@ -269,7 +272,7 @@ static const InsnTemplate* insn_db_cop_lists[][0b11 + 1] = {
[COP3] = { [INSN_TYPE_COP_FMT] = NULL, [INSN_TYPE_REGIMM] = NULL, [INSN_TYPE_FUNC] = NULL, [INSN_TYPE_UNKNOWN] = NULL, }, // Coprocessor-3 (CP3).
};
// Pseudo-instructions
// Single-line pseudo-instructions.
ALIGNED32 static const InsnTemplate insn_db_pseudo[] = {
[PSEUDO_NOP ] = { .opcode = OPS_SLL , .name = "NOP" , .fmt = "_" , .out = 0, }, // NOP (pseudo of SLL).
[PSEUDO_MOVET] = { .opcode = OPS_ADD , .name = "MOVE" , .fmt = "\'dt" , .out = 1, }, // Move (pseudo of ADD and OR).

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@@ -15,7 +15,7 @@ NEVER_INLINE uintptr_t _asm_getaddr(void) {
return RAddr;
}
// Replaces its own call instruction with a custom MIPS assembly instruction.
// Replaces its own call instruction with a custom MIPS assembly instruction and jumps back to right before it to run it. Replaces the branch delay slot with a NOP.
NEVER_INLINE void _asm_setbits(uintptr_t bits) {
uintptr_t RAddr;
ASM_GET_REG_CPU(RAddr, "$ra"); // Get $ra.

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@@ -29,8 +29,8 @@ enum ThreadID {
THREAD_7_HVQM, // HVQM main thread (see HVQM_THREAD_ID in src/hvqm/hvqm.h).
THREAD_8_TIMEKEEPER, // HVQM timekeeper thread (see TIMEKEEPER_THREAD_ID in src/hvqm/hvqm.h).
THREAD_9_DA_COUNTER, // HVQM DA counterthread (see DA_COUNTER_THREAD_ID in src/hvqm/hvqm.h).
THREAD_13_FAULT, // UNF debug thread (see FAULT_THREAD_ID in src/usb/debug.h).
THREAD_14_USB, // UNF USB thread (see USB_THREAD_ID in src/usb/debug.h).
THREAD_13_FAULT = 13, // UNF debug thread (see FAULT_THREAD_ID in src/usb/debug.h).
THREAD_14_USB = 14, // UNF USB thread (see USB_THREAD_ID in src/usb/debug.h).
// Crash screen threads (the crash screen has its own crash thread):
THREAD_1000_CRASH_SCREEN_0 = 1000, // Initial crash screen thread for the normal game. Can be repurposed as a crash screen for the crash screen.