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synced 2026-01-21 10:35:32 -08:00
Fix UNF thread IDs in enum + improve some comments
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@@ -35,6 +35,8 @@ DEF_REGION_NAME(us);
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DEF_REGION_NAME(eu);
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#elif VERSION_SH
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DEF_REGION_NAME(sh);
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#elif VERSION_CN
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DEF_REGION_NAME(cn);
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#elif BBPLAYER
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DEF_REGION_NAME(bb);
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#else
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@@ -274,7 +276,7 @@ static const char* sFltErrDesc[NUM_FLT_ERR] = {
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[FLT_ERR_NAN ] = "NaN float",
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};
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//! TODO: NaN floats aren't detected here even though validate_float does, and this works with denorms.
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//! TODO: NaN floats aren't detected here even though validate_f32 does, and this works with denorms.
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enum FloatErrorType validate_floats_in_reg_buffer(void) {
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enum FloatErrorType fltErrType = FLT_ERR_NONE;
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@@ -285,7 +287,7 @@ enum FloatErrorType validate_floats_in_reg_buffer(void) {
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IEEE754_f32 val = {
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.asU32 = get_reg_val(reg.cop, reg.idx)
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};
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fltErrType = validate_float(val);
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fltErrType = validate_f32(val);
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if (fltErrType != FLT_ERR_NONE) {
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break;
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@@ -88,7 +88,7 @@ static OSThread* get_crashed_thread(void) {
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) {
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if (
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(thread->priority > OS_PRIORITY_IDLE ) &&
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(thread->priority < OS_PRIORITY_APPMAX) && //! TODO: Should this include OS_PRIORITY_APPMAX threads? Official N64 games don't.
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(thread->priority < OS_PRIORITY_APPMAX) && //! TODO: Should this include threads with priority OS_PRIORITY_APPMAX and higher? Official N64 games don't.
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(thread->flags & (OS_FLAG_CPU_BREAK | OS_FLAG_FAULT)) &&
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(thread != gCrashedThread)
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) {
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@@ -461,8 +461,9 @@ static const FloatErrorPrintFormat sFltErrFmt[] = {
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[FLT_ERR_NAN ] = { .r = 0xFF, .g = 0x7F, .b = 0x7F, .prefixChar = CHAR_FLT_PREFIX_NAN, .suffix = "NaN", },
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};
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//! TODO: Version of this but for f64.
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size_t cs_print_f32(u32 x, u32 y, IEEE754_f32 val, _Bool includeSuffix) {
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const enum FloatErrorType fltErrType = validate_float(val);
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const enum FloatErrorType fltErrType = validate_f32(val);
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size_t numChars = 0;
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if (fltErrType != FLT_ERR_NONE) {
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@@ -366,7 +366,7 @@ void page_disasm_draw(void) {
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sDisasmBranchStartX = (DISASM_BRANCH_ARROW_HEAD_SIZE + DISASM_BRANCH_ARROW_HEAD_OFFSET) +
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cs_get_setting_val(CS_OPT_GROUP_PAGE_DISASM, CS_OPT_DISASM_OFFSET_ADDR)
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? TEXT_X(INSN_NAME_DISPLAY_WIDTH + STRLEN("R0, R0, 0x80000000"))
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? TEXT_X(INSN_NAME_DISPLAY_WIDTH + STRLEN("R0, R0, 0x80XXXXXX"))
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: TEXT_X(INSN_NAME_DISPLAY_WIDTH + STRLEN("R0, R0, +0x0000"));
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u32 line = 1;
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@@ -44,6 +44,8 @@
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// MIPS III Instructions:
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// https://n64brew.dev/wiki/MIPS_III_instructions
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// https://hack64.net/docs/VR43XX.pdf
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// Opcode instructions:
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ALIGNED32 static const InsnTemplate insn_db_standard[] = { // INSN_TYPE_OPCODE
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@@ -196,6 +198,7 @@ ALIGNED32 static const InsnTemplate insn_db_cop0_sub00[] = { // OPC_COP0, INSN_T
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};
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ALIGNED32 static const InsnTemplate insn_db_cop0_sub10[] = { // OPC_COP0, INSN_TYPE_FUNC
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//! TODO: Find out the proper format for these?
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//! TODO: These use the COP0 TLB Index register as the input/output.
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{ .opcode = OPC_COP0_TLBP , .name = "TLBP" , .fmt = "\'" , .out = 0, }, // 8: Searches for a TLB entry that matches the EntryHi register.
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{ .opcode = OPC_COP0_TLBR , .name = "TLBR" , .fmt = "\'" , .out = 0, }, // 1: Loads EntryHi and EntryLo registers with the TLB entry pointed at by the Index register.
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{ .opcode = OPC_COP0_TLBWI , .name = "TLBWI" , .fmt = "\'" , .out = 0, }, // 2: Stores the contents of EntryHi and EntryLo registers into the TLB entry pointed at by the Index register.
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@@ -269,7 +272,7 @@ static const InsnTemplate* insn_db_cop_lists[][0b11 + 1] = {
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[COP3] = { [INSN_TYPE_COP_FMT] = NULL, [INSN_TYPE_REGIMM] = NULL, [INSN_TYPE_FUNC] = NULL, [INSN_TYPE_UNKNOWN] = NULL, }, // Coprocessor-3 (CP3).
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};
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// Pseudo-instructions
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// Single-line pseudo-instructions.
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ALIGNED32 static const InsnTemplate insn_db_pseudo[] = {
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[PSEUDO_NOP ] = { .opcode = OPS_SLL , .name = "NOP" , .fmt = "_" , .out = 0, }, // NOP (pseudo of SLL).
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[PSEUDO_MOVET] = { .opcode = OPS_ADD , .name = "MOVE" , .fmt = "\'dt" , .out = 1, }, // Move (pseudo of ADD and OR).
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@@ -15,7 +15,7 @@ NEVER_INLINE uintptr_t _asm_getaddr(void) {
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return RAddr;
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}
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// Replaces its own call instruction with a custom MIPS assembly instruction.
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// Replaces its own call instruction with a custom MIPS assembly instruction and jumps back to right before it to run it. Replaces the branch delay slot with a NOP.
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NEVER_INLINE void _asm_setbits(uintptr_t bits) {
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uintptr_t RAddr;
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ASM_GET_REG_CPU(RAddr, "$ra"); // Get $ra.
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@@ -29,8 +29,8 @@ enum ThreadID {
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THREAD_7_HVQM, // HVQM main thread (see HVQM_THREAD_ID in src/hvqm/hvqm.h).
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THREAD_8_TIMEKEEPER, // HVQM timekeeper thread (see TIMEKEEPER_THREAD_ID in src/hvqm/hvqm.h).
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THREAD_9_DA_COUNTER, // HVQM DA counterthread (see DA_COUNTER_THREAD_ID in src/hvqm/hvqm.h).
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THREAD_13_FAULT, // UNF debug thread (see FAULT_THREAD_ID in src/usb/debug.h).
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THREAD_14_USB, // UNF USB thread (see USB_THREAD_ID in src/usb/debug.h).
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THREAD_13_FAULT = 13, // UNF debug thread (see FAULT_THREAD_ID in src/usb/debug.h).
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THREAD_14_USB = 14, // UNF USB thread (see USB_THREAD_ID in src/usb/debug.h).
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// Crash screen threads (the crash screen has its own crash thread):
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THREAD_1000_CRASH_SCREEN_0 = 1000, // Initial crash screen thread for the normal game. Can be repurposed as a crash screen for the crash screen.
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