mirror of
https://github.com/HackerN64/F3DEX3.git
synced 2026-01-21 10:37:45 -08:00
Non working draft which matches/beats EX2
This commit is contained in:
Sauraen
@@ -4,15 +4,15 @@
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Vertex pipeline cycles per **vertex pair** in steady state (lower is better).
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Hand-counted timings taking into account all pipeline stalls and all dual-issue
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conditions except for instruction alignment.
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conditions. Instruction alignment is only taken into account for LVP_NOC.
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| Microcode | No Lighting | First Dir Lt | Total for 1 Dir Lt | Extra Dir Lts |
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|----------------|-------------|--------------|--------------------|---------------|
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| F3DEX3 | 98 | 103 | 201 | 29 |
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| F3DEX3_NOC | 79 | 103 | 182 | 29 |
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| F3DEX3_LVP | 81 | 15 | 96 | 7 |
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| F3DEX3_LVP_NOC | 62 | 15 | 77 | 7 |
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| F3DEX2 | 54 | 19 | 73 | 3 then 12 |
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| F3DEX3_LVP_NOC | 54 | 17 | 71 | 7, 7, 7, 7, ... |
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| F3DEX2 | 54 | 19 | 73 | 3, 12, 3, 12, ... |
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Vertex processing time as reported by the performance counter in the `PA`
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configuration.
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@@ -26,7 +26,7 @@ configuration.
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| F3DEX3 | 7.64ms | 3.13ms | 2.37ms |
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| F3DEX3_NOC | 7.07ms | 2.89ms | 2.14ms |
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| F3DEX3_LVP | 4.57ms | 1.77ms | 1.67ms |
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| F3DEX3_LVP_NOC | 3.96ms | 1.52ms | 1.41ms |
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| F3DEX3_LVP_NOC | Outdated | | |
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| F3DEX2 | No* | No* | No* |
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| Vertex count | 3664 | 1608 | 1608 |
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192
f3dex3.s
192
f3dex3.s
@@ -1525,111 +1525,128 @@ vtx_after_calc_mit:
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srl $7, $7, 5 // 8 if G_FOG is set, 0 otherwise
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vertices_store:
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vge XV3, XV25, $v31[2] // 0; clamp Z to >= 0
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sKPI equ $v11 // vtx_store Keep Int (keep across pipelining)
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sKPF equ $v12 // vtx_store Keep Frac
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.align 8
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vtx_loop_no_lighting:
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vmadn vPairTPosF, vM2F, vPairPosI[2h]
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or $10, $10, $11 // Combine results for first vertex
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vmadh vPairTPosI, vM2I, vPairPosI[2h]
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sh $10, (VTX_CLIP )($19) // Store first vertex flags
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sKPG equ vBBB // = $v21
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vge sKPG, sKPI, $v31[6] // Clamp W/fog to >= 0x7F00 (low byte is used)
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luv vPairRGBA[0], (tempVpRGBA)(rdpCmdBufEndP1) // Vtx pair RGBA
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sCLZ equ $v19
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vge sCLZ, sKPI, $v31[2] // 0; clamp Z to >= 0
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addi $1, $1, -2*inputVtxSize // Decrement vertex count by 2
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vtx_return_from_lighting:
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vmudl $v29, vPairTPosF, $v30[3] // Persp norm
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sub $11, secondVtxPos, $7 // Points 8 before secondVtxPos if fog, else 0
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vmadm XV2, vPairTPosI, $v30[3] // Persp norm
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sbv XV27[15], (VTX_COLOR_A + 8)($11) // In VTX_SCR_Y if fog disabled...
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vmadn XV21, $v31, $v31[2] // 0
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sbv XV27[7], (VTX_COLOR_A + 8 - vtxSize)($11) // ...which gets overwritten below
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vmov XV26[1], XV3[2]
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ssv XV3[12], (VTX_SCR_Z )(secondVtxPos)
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vmudn XV7, vPairTPosF, $v31[3] // W * clip ratio for scaled clipping
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slv XV25[8], (VTX_SCR_VEC )(secondVtxPos)
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vmadh XV6, vPairTPosI, $v31[3] // W * clip ratio for scaled clipping
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sdv XV25[0], (VTX_SCR_VEC )($19)
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vrcph $v29[0], XV2[3]
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ssv XV26[12], (VTX_SCR_Z_FRAC )(secondVtxPos)
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vrcpl XV5[3], XV21[3]
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slv XV26[2], (VTX_SCR_Z )($19)
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vrcph XV4[3], XV2[7]
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// s1WH is $v16 // vtx_store 1/W High
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vmadm s1WH, vPairTPosI, $v30[3] // Persp norm
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addi outputVtxPos, outputVtxPos, 2*vtxSize // Points to SECOND output vtx
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vrcpl XV5[7], XV21[7]
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sra $11, $1, 31 // All 1s if on last iter
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vrcph XV4[7], $v31[2] // 0
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andi $11, $11, vtxSize // vtxSize if on last iter, else normally 0
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// s1WL is $v17 // vtx_store 1/W Low
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vmadn s1WL, $v31, $v31[2] // 0
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sbv sKPG[15], (VTX_COLOR_A + 8)($11) // In VTX_SCR_Y if fog disabled...
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vmov sKPF[1], sCLZ[2]
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sbv sKPG[7], (VTX_COLOR_A + 8 - vtxSize)($11) // ...which gets overwritten below
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// sSCL is $v20 // vtx_store Scaled Clipping Low
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vmudn sSCL, vPairTPosF, $v31[3] // W * clip ratio for scaled clipping
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ssv sCLZ[12], (VTX_SCR_Z )(secondVtxPos)
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// sSCH is $v21 // vtx_store Scaled Clipping High
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vmadh sSCH, vPairTPosI, $v31[3] // W * clip ratio for scaled clipping
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slv sKPI[8], (VTX_SCR_VEC )(secondVtxPos)
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vrcph $v29[0], s1WH[3]
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slv sKPI[0], (VTX_SCR_VEC )($19)
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// sWRL is $v25 // vtx_store W Reciprocal Low
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vrcpl sWRL[3], s1WL[3]
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ssv sKPF[12], (VTX_SCR_Z_FRAC )(secondVtxPos)
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// sWRH is $v26 // vtx_store W Reciprocal High
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vrcph sWRH[3], s1WH[7]
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slv sKPF[2], (VTX_SCR_Z )($19)
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vrcpl sWRL[7], s1WL[7]
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sra $24, $1, 31 // All 1s if on last iter
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vrcph sWRH[7], $v31[2] // 0
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andi $24, $24, vtxSize // vtxSize if on last iter, else normally 0
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vch $v29, vPairTPosI, vPairTPosI[3h] // Clip screen high
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sub secondVtxPos, outputVtxPos, $11 // First output vtx on last iter, else second
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sub secondVtxPos, outputVtxPos, $24 // First output vtx on last iter, else second
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vcl $v29, vPairTPosF, vPairTPosF[3h] // Clip screen low
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addi $19, outputVtxPos, -vtxSize // First output vtx always
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vmudl $v29, XV21, XV5
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vmudl $v29, s1WL, sWRL
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cfc2 $10, $vcc // Screen clip results
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vmadm $v29, XV2, XV5
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vmadm $v29, s1WH, sWRL
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sdv vPairTPosF[8], (VTX_FRAC_VEC )(secondVtxPos)
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vmadn XV21, XV21, XV4
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ldv XTEMPST[0], (VTX_IN_TC + 2 * inputVtxSize)(inputVtxPos) // ST in 0:1, RGBA in 2:3
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vmadh XV2, XV2, XV4
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vmadn s1WL, s1WL, sWRH
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sTCL equ $v19
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ldv sTCL[0], (VTX_IN_TC + 2 * inputVtxSize)(inputVtxPos) // ST in 0:1, RGBA in 2:3
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vmadh s1WH, s1WH, sWRH
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sdv vPairTPosF[0], (VTX_FRAC_VEC )($19)
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vge $v29, vPairTPosI, $v31[2] // Int position XYZW >= 0
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lsv vPairTPosF[14], (VTX_Z_FRAC )(secondVtxPos) // load Z into W slot, will be for fog below
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vmudh $v29, vOne, $v31[4] // 4
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sdv vPairTPosI[8], (VTX_INT_VEC )(secondVtxPos)
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vmadn XV26, XV21, $v31[0] // -4
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vmadn sKPF, s1WL, $v31[0] // -4
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lsv vPairTPosF[6], (VTX_Z_FRAC )($19) // load Z into W slot, will be for fog below
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vmadh XV25, XV2, $v31[0] // -4
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vmadh sKPI, s1WH, $v31[0] // -4
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sdv vPairTPosI[0], (VTX_INT_VEC )($19)
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vmrg XV2, vZero, $v31[7] // Set to 0 where positive, 0x7FFF where negative
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ldv XTEMPST[8], (VTX_IN_TC + 3 * inputVtxSize)(inputVtxPos) // ST in 4:5, RGBA in 6:7
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vch $v29, vPairTPosI, XV6[3h] // Clip scaled high
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slv vPairRGBA[0], (VTX_COLOR_VEC )(secondVtxPos) // Store RGBA for first vector
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vmudl $v29, XV26, XV5
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sWNG equ $v16 // vtx_store W NeGative
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vmrg sWNG, vZero, $v31[7] // Set to 0 where positive, 0x7FFF where negative
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ldv sTCL[8], (VTX_IN_TC + 3 * inputVtxSize)(inputVtxPos) // ST in 4:5, RGBA in 6:7
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vch $v29, vPairTPosI, sSCH[3h] // Clip scaled high
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suv vPairRGBA[4], (VTX_COLOR_VEC )(secondVtxPos) // Store RGBA for second vtx
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vmudl $v29, sKPF, sWRL
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lsv vPairTPosI[14], (VTX_Z_INT )(secondVtxPos) // load Z into W slot, will be for fog below
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vmadm $v29, XV25, XV5
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slv vPairRGBA[4], (VTX_COLOR_VEC )($19) // Store RGBA for second vector
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vmadn XV5, XV26, XV4
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vmadm $v29, sKPI, sWRL
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suv vPairRGBA[0], (VTX_COLOR_VEC )($19) // Store RGBA for first vtx
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vmadn sWRL, sKPF, sWRH
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lsv vPairTPosI[6], (VTX_Z_INT )($19) // load Z into W slot, will be for fog below
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vmadh XV4, XV25, XV4
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vmadh sWRH, sKPI, sWRH
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srl $24, $10, 4 // Shift second vertex screen clipping to first slots
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vmadh XV2, XV2, $v31[7] // Makes screen coords a large number if W < 0
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vmadh sWNG, sWNG, $v31[7] // Makes screen coords a large number if W < 0
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andi $24, $24, CLIP_SCRN_NPXY | CLIP_CAMPLANE // Mask to only screen bits we care about
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vcl $v29, vPairTPosF, XV7[3h] // Clip scaled low
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vcl $v29, vPairTPosF, sSCL[3h] // Clip scaled low
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cfc2 $20, $vcc // Scaled clip results
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vmudl $v29, vPairTPosF, XV5[3h] // Pos times inv W
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ssv XV5[14], (VTX_INV_W_FRAC)(secondVtxPos)
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vmadm $v29, vPairTPosI, XV5[3h] // Pos times inv W
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vmudl $v29, vPairTPosF, sWRL[3h] // Pos times inv W
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ssv sWRL[14], (VTX_INV_W_FRAC)(secondVtxPos)
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vmadm $v29, vPairTPosI, sWRL[3h] // Pos times inv W
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// vPairPosI is $v20
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ldv vPairPosI[0], (VTX_IN_OB + 2 * inputVtxSize)(inputVtxPos) // Pos of 1st vector for next iteration
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vmadn XV26, vPairTPosF, XV2[3h] // Makes screen coords a large number if W < 0
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vmadn sKPF, vPairTPosF, sWNG[3h] // Makes screen coords a large number if W < 0
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ldv vPairPosI[8], (VTX_IN_OB + 3 * inputVtxSize)(inputVtxPos) // Pos of 2nd vector on next iteration
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vmadh XV25, vPairTPosI, XV2[3h] // XV25:XV26 = pos times inv W
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vmadh sKPI, vPairTPosI, sWNG[3h] // sKPI:sKPF = pos times inv W
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addi inputVtxPos, inputVtxPos, (2 * inputVtxSize) // Advance two positions forward in the input vertices
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vmudm XV3, vPairST, sSTS // Scale ST
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sST2 equ $v21
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vmudm sST2, vPairST, sSTS // Scale ST
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andi $10, $10, CLIP_SCRN_NPXY | CLIP_CAMPLANE // Mask to only screen bits we care about
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vcopy vPairST, XTEMPST
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vcopy vPairST, sTCL
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sll $11, $20, 4 // Shift first vertex scaled clipping to second slots
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vmudl $v29, XV26, $v30[3] // Persp norm
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ssv XV5[6], (VTX_INV_W_FRAC)($19)
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vmadm XV25, XV25, $v30[3] // Persp norm
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ssv XV4[14], (VTX_INV_W_INT )(secondVtxPos)
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vmadn XV26, $v31, $v31[2] // 0; Now XV26:XV25 = projected position
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ssv XV4[6], (VTX_INV_W_INT )($19)
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vmov XTEMPST[4], vPairST[2]
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slv XV3[4], (VTX_TC_VEC )(secondVtxPos) // Store scaled S, T vertex 1
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vmov XTEMPST[5], vPairST[3]
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slv XV3[12], (VTX_TC_VEC )($19) // Store scaled S, T vertex 2
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vmudl $v29, sKPF, $v30[3] // Persp norm
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ssv sWRL[6], (VTX_INV_W_FRAC)($19)
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vmadm sKPI, sKPI, $v30[3] // Persp norm
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ssv sWRH[14], (VTX_INV_W_INT )(secondVtxPos)
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vmadn sKPF, $v31, $v31[2] // 0; Now sKPI:sKPF = projected position
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ssv sWRH[6], (VTX_INV_W_INT )($19)
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vmov sTCL[4], vPairST[2] // First vtx RG to elem 4
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slv sST2[4], (VTX_TC_VEC )(secondVtxPos) // Store scaled S, T vertex 1
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vmov sTCL[5], vPairST[3] // First vtx BA to elem 5
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slv sST2[12], (VTX_TC_VEC )($19) // Store scaled S, T vertex 2
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vmudh $v29, sVPO, vOne // offset * 1
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andi $20, $20, CLIP_SCAL_NPXY // Mask to only bits we care about
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vmadn XV26, XV26, sVPS // + pos frac * scale
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andi $11, $11, CLIP_SCAL_NPXY // Mask to only bits we care about
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vmadh XV25, XV25, sVPS // int part, XV25:XV26 is now screen space pos
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vmadn sKPF, sKPF, sVPS // + pos frac * scale
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or $24, $24, $20 // Combine results for second vertex
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vmadh sKPI, sKPI, sVPS // int part, sKPI:sKPF is now screen space pos
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andi $11, $11, CLIP_SCAL_NPXY // Mask to only bits we care about
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vmudn $v29, vM3F, vOne
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or $10, $10, $11 // Combine results for first vertex
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vmadh $v29, vM3I, vOne
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sh $24, (VTX_CLIP )(secondVtxPos) // Store second vertex clip flags
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vmadn $v29, vM0F, vPairPosI[0h]
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sh $10, (VTX_CLIP )($19) // Store first vertex results
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vmadh $v29, vM0I, vPairPosI[0h]
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vmadh $v29, vM3I, vOne
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blez $1, vtx_epilogue
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vmadn $v29, vM1F, vPairPosI[1h]
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vmadh $v29, vM1I, vPairPosI[1h]
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sdv XTEMPST[8], (tempVpRGBA)(rdpCmdBufEndP1) // Vtx 0 and 1 RGBA
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vmadn vPairTPosF, vM2F, vPairPosI[2h]
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luv vPairRGBA[0], (tempVpRGBA)(rdpCmdBufEndP1) // Vtx pair RGBA
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vmadh vPairTPosI, vM2I, vPairPosI[2h]
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vmadn $v29, vM0F, vPairPosI[0h]
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vmadh $v29, vM0I, vPairPosI[0h]
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sdv sTCL[8], (tempVpRGBA)(rdpCmdBufEndP1) // Vtx 0 and 1 RGBA in order
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vmadn $v29, vM1F, vPairPosI[1h]
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jr $ra
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vge XV27, XV25, $v31[6] // Clamp W/fog to >= 0x7F00 (low byte is used)
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vmadh $v29, vM1I, vPairPosI[1h]
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vtx_epilogue:
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@@ -1806,7 +1823,7 @@ middle_of_vtx_store:
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// vPairNrml is $v16
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vmudn vPairNrml, vPairRGBA, $v31[3] // 2; left shift RGBA without clamp; vtx pair normals
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ssv vPairTPosF[12], (VTX_SCR_Z_FRAC)(secondVtxPos)
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// sCLZ is $v21 // vtx_store CLipped Z
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// sCLZ is $v21 // vtx_store CLamped Z
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vge sCLZ, vPairTPosI, $v31[2] // 0; clamp Z to >= 0
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ssv vPairTPosF[4], (VTX_SCR_Z_FRAC)($19)
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vge sFOG, sFOG, $v31[6] // 0x7F00; clamp fog to >= 0 (want low byte only)
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@@ -1932,7 +1949,7 @@ skip_return_to_lt_or_loop:
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ssv vPairTPosF[12], (VTX_SCR_Z_FRAC)(secondVtxPos)
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vge sFOG, sFOG, $v31[6] // 0x7F00; clamp fog to >= 0 (want low byte only)
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or $24, $24, $20 // Combine results for second vertex
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// sCLZ is $v25 // vtx_store CLipped Z
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// sCLZ is $v25 // vtx_store CLamped Z
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vge sCLZ, vPairTPosI, $v31[2] // 0; clamp Z to >= 0
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ssv vPairTPosF[4], (VTX_SCR_Z_FRAC)($19)
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vmulf $v29, sOPM, vPairTPosI[1h] // -0x4000*Y1, --, +0x4000*Y1, --, repeat vtx 2
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@@ -3113,10 +3130,23 @@ xfrm_single_dir:
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sw $11, (0)($20) // Store 3 (4) bytes to target address
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// This clobbers the specular size
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.if CFG_LEGACY_VTX_PIPE && CFG_NO_OCCLUSION_PLANE
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.align 8
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.endif
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lt_vtx_pair:
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//
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// LVP main lighting
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//
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.if CFG_LEGACY_VTX_PIPE && CFG_NO_OCCLUSION_PLANE // New LVP_NOC
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vmadn vPairTPosF, vM2F, vPairPosI[2h]
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lpv vPairNrml[0], (tempVpRGBA)(rdpCmdBufEndP1) // Vtx pair normals
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vmadh vPairTPosI, vM2I, vPairPosI[2h]
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lpv $v14[7], (tempVpRGBA - 8)(rdpCmdBufEndP1) // Y to elem 0, 4
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// vnop
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lpv $v15[6], (tempVpRGBA - 8)(rdpCmdBufEndP1) // Z to elem 0, 4
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// vnop
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or $10, $10, $11 // Combine results for first vertex
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.endif
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vmulf $v29, vPairNrml, $v13[4] // Normals X elems 0, 4 * first light dir
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luv vPairLt, (ltBufOfs + 0)($3) // Total light level, init to ambient
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vmacf $v29, $v14, $v13[5] // Normals Y elems 0, 4 * first light dir
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@@ -3127,8 +3157,10 @@ lt_vtx_pair:
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.endif
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beq $3, altBaseReg, lt_post
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lpv $v18[0], (xfrmLookatDirs + 0)($zero) // Lookat 0 in 0-2, 1 in 4-6; = vNrmOut
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// vnop
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move curLight, $3 // Point to ambient light
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// vnop
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// nop
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lt_loop:
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vge vCCC, vAAA, $v31[2] // 0; clamp dot product to >= 0
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vmulf $v29, vPairNrml, vDDD[4] // Normals X elems 0, 4
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@@ -3141,12 +3173,24 @@ lt_loop:
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bne curLight, altBaseReg, lt_loop
|
||||
vmacf vPairLt, vBBB, vCCC[0h] // + light color * dot product
|
||||
lt_post:
|
||||
.if CFG_LEGACY_VTX_PIPE && CFG_NO_OCCLUSION_PLANE // New LVP_NOC
|
||||
vge sKPG, sKPI, $v31[6] // Clamp W/fog to >= 0x7F00 (low byte is used)
|
||||
sh $10, (VTX_CLIP )($19) // Store first vertex flags
|
||||
vge sCLZ, sKPI, $v31[2] // 0; clamp Z to >= 0
|
||||
addi $1, $1, -2*inputVtxSize // Decrement vertex count by 2
|
||||
vne $v29, $v31, $v31[3h] // Set VCC to 11101110
|
||||
beqz $17, vtx_return_from_lighting
|
||||
vmrg vPairRGBA, vPairLt, vPairRGBA // RGB = light, A = vtx alpha
|
||||
.else
|
||||
beqz $17, vtx_early_return_from_lighting
|
||||
vne $v29, $v31, $v31[3h] // Set VCC to 11101110
|
||||
.endif
|
||||
|
||||
.endif
|
||||
// These definitions are shared by both versions
|
||||
vLookat1 equ vAAA
|
||||
vLookat0 equ vPairLt
|
||||
// Texgen uses these, vCCC:vDDD, and of course vPairST.
|
||||
.if CFG_LEGACY_VTX_PIPE
|
||||
vmulf $v29, vPairNrml, $v18[0] // Normals X elems 0, 4 * lookat 0 X
|
||||
vmacf $v29, $v14, $v18[1] // Normals Y elems 0, 4 * lookat 0 Y
|
||||
|
||||
21
notes.s
21
notes.s
@@ -36,3 +36,24 @@ lpv $v27[4], ( 0)($11) // 0C 0D 0E 0F 00 01 02 03
|
||||
lpv $v27[5], ( 0)($11) // 0B 0C 0D 0E 0F 00 01 02
|
||||
lpv $v27[6], ( 0)($11) // 0A 0B 0C 0D 0E 0F 00 01
|
||||
lpv $v27[7], ( 0)($11) // 09 0A 0B 0C 0D 0E 0F 00
|
||||
|
||||
// spv and suv always store to the 8 bytes at/after the scalar reg + offset.
|
||||
// What is stored starts at lane e, increments and wraps at lane 8. However for
|
||||
// the lanes >= 8, the functionality of spv and suv swaps.
|
||||
// Mem addr rel to $11 0 1 2 3 4 5 6 7
|
||||
spv $v27[0], ( 0)($11) // P0 P1 P2 P3 P4 P5 P6 P7 Lane number
|
||||
spv $v27[1], ( 0)($11) // P1 P2 P3 P4 P5 P6 P7 U0 P = packed (top 8 bits)
|
||||
spv $v27[2], ( 0)($11) // P2 P3 P4 P5 P6 P7 U0 U1 U = unsigned (bits 14:7)
|
||||
spv $v27[3], ( 0)($11) // P3 P4 P5 P6 P7 U0 U1 U2
|
||||
spv $v27[4], ( 0)($11) // P4 P5 P6 P7 U0 U1 U2 U3
|
||||
spv $v27[5], ( 0)($11) // P5 P6 P7 U0 U1 U2 U3 U4
|
||||
spv $v27[6], ( 0)($11) // P6 P7 U0 U1 U2 U3 U4 U5
|
||||
spv $v27[7], ( 0)($11) // P7 U0 U1 U2 U3 U4 U5 U6
|
||||
suv $v27[0], ( 0)($11) // U0 U1 U2 U3 U4 U5 U6 U7 = spv $v27[8], (0)($11)
|
||||
suv $v27[1], ( 0)($11) // U1 U2 U3 U4 U5 U6 U7 P0
|
||||
suv $v27[2], ( 0)($11) // U2 U3 U4 U5 U6 U7 P0 P1
|
||||
suv $v27[3], ( 0)($11) // U3 U4 U5 U6 U7 P0 P1 P2
|
||||
suv $v27[4], ( 0)($11) // U4 U5 U6 U7 P0 P1 P2 P3
|
||||
suv $v27[5], ( 0)($11) // U5 U6 U7 P0 P1 P2 P3 P4
|
||||
suv $v27[6], ( 0)($11) // U6 U7 P0 P1 P2 P3 P4 P5
|
||||
suv $v27[7], ( 0)($11) // U7 P0 P1 P2 P3 P4 P5 P6
|
||||
|
||||
Reference in New Issue
Block a user