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vmovss and vmovsd don't load 128 bits when given a memory argument (#7520)

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Co-authored-by: Nick Fitzgerald <fitzgen@gmail.com>
This commit is contained in:
Trevor Elliott
2023-11-09 22:48:39 +00:00
committed by GitHub
co-authored by Nick Fitzgerald
parent 648ccce0f6
commit 3078b9cbd2
1 changed files with 50 additions and 18 deletions
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cranelift/codegen/src/isa/x64/pcc.rs
+50 -18
View File
@@ -3,6 +3,7 @@
use crate::ir::pcc::*;
use crate::ir::types::*;
use crate::ir::Type;
use crate::isa::x64::args::AvxOpcode;
use crate::isa::x64::inst::args::{
AluRmiROpcode, Amode, Gpr, Imm8Reg, RegMem, RegMemImm, ShiftKind, SyntheticAmode,
ToWritableReg, CC,
@@ -533,34 +534,24 @@ pub(crate) fn check(
ensure_no_fact(vcode, dst.to_writable_reg().to_reg())
}
// NOTE: it's assumed that all of these cases perform 128-bit loads, but this hasn't been
// verified. The effect of this will be spurious PCC failures when these instructions are
// involved.
Inst::XmmRmRUnaligned { dst, ref src2, .. }
| Inst::XmmRmRImmVex { dst, ref src2, .. }
| Inst::XmmRmRVex3 {
dst,
src3: ref src2,
..
}
| Inst::XmmRmRBlendVex { dst, ref src2, .. }
| Inst::XmmUnaryRmRVex {
dst, src: ref src2, ..
}
| Inst::XmmUnaryRmRImmVex {
dst, src: ref src2, ..
}
| Inst::XmmRmREvex { dst, ref src2, .. }
| Inst::XmmUnaryRmRImmEvex {
dst, src: ref src2, ..
}
| Inst::XmmRmREvex3 {
dst,
src3: ref src2,
..
}
| Inst::XmmUnaryRmRUnaligned {
dst, src: ref src2, ..
}
| Inst::XmmUnaryRmREvex {
dst, src: ref src2, ..
}
| Inst::XmmRmREvex3 {
dst,
src3: ref src2,
..
} => {
match <&RegMem>::from(src2) {
RegMem::Mem { ref addr } => {
@@ -571,6 +562,47 @@ pub(crate) fn check(
ensure_no_fact(vcode, dst.to_writable_reg().to_reg())
}
Inst::XmmRmRImmVex {
op, dst, ref src2, ..
}
| Inst::XmmRmRVex3 {
op,
dst,
src3: ref src2,
..
}
| Inst::XmmRmRBlendVex {
op, dst, ref src2, ..
}
| Inst::XmmUnaryRmRVex {
op,
dst,
src: ref src2,
..
}
| Inst::XmmUnaryRmRImmVex {
op,
dst,
src: ref src2,
..
} => {
let size = match op {
AvxOpcode::Vmovss => 32,
AvxOpcode::Vmovsd => 64,
// We assume all other operations happen on 128-bit values.
_ => 128,
};
match <&RegMem>::from(src2) {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I8X16, size)?;
}
RegMem::Reg { .. } => {}
}
ensure_no_fact(vcode, dst.to_writable_reg().to_reg())
}
Inst::XmmRmiRVex { dst, ref src2, .. } => {
match <&RegMemImm>::from(src2) {
RegMemImm::Mem { ref addr } => {