mirror of
https://github.com/encounter/tp.git
synced 2026-07-11 06:18:46 -07:00
most of shieldD revo sdk matching (#2951)
* shieldD revo wpad done * shieldD revo hio2 done * shieldD revo aralt, ppcarch, gf done * shieldD revo exi done * shieldD revo SI done * shieldD revo vi done * shieldD revo mtx done * shieldD revo GX mostly done * shieldD revo ai/dsp done * shieldD revo sc mostly done * shieldD revo esp/euart/wenc mostly done * build fixes
This commit is contained in:
TakaRikka
@@ -4154,7 +4154,7 @@ revolution/vi/vi3in1.c:
|
||||
.text start:0x805D28D0 end:0x805D3610
|
||||
.data start:0x8072CE20 end:0x8072D460
|
||||
.sdata start:0x8074BE80 end:0x8074BE90
|
||||
.sbss start:0x8074D3B0 end:0x8074D3CC
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||||
.sbss start:0x8074D3B0 end:0x8074D3C8
|
||||
.bss start:0x807FAAE0 end:0x807FAB00
|
||||
|
||||
revolution/mtx/mtx.c:
|
||||
@@ -4189,14 +4189,14 @@ revolution/gx/GXInit.c:
|
||||
.text start:0x805D7340 end:0x805D8E80
|
||||
.data start:0x8072ED20 end:0x8072EFD0
|
||||
.sdata start:0x8074BEB8 end:0x8074BEC0
|
||||
.sbss start:0x8074D3CC end:0x8074D3F4
|
||||
.sbss start:0x8074D3C8 end:0x8074D3F0
|
||||
.sdata2 start:0x80752D00 end:0x80752D28
|
||||
.bss start:0x807FAB00 end:0x807FB180
|
||||
|
||||
revolution/gx/GXFifo.c:
|
||||
.text start:0x805D8E80 end:0x805DA790
|
||||
.data start:0x8072EFD0 end:0x8072F4C0
|
||||
.sbss start:0x8074D3F4 end:0x8074D410
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||||
.sbss start:0x8074D3F0 end:0x8074D410
|
||||
.bss start:0x807FB180 end:0x807FB1C8
|
||||
|
||||
revolution/gx/GXAttr.c:
|
||||
@@ -4404,7 +4404,7 @@ revolution/nand/NANDErrorMessage.c:
|
||||
.text start:0x8060F6A0 end:0x8060F960
|
||||
.rodata start:0x8065EC00 end:0x8065EE18
|
||||
.data start:0x8073BED8 end:0x8073DB08
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||||
.sbss start:0x8074D5E0 end:0x8074D5EC
|
||||
.sbss start:0x8074D5E0 end:0x8074D5E8
|
||||
.sdata2 start:0x80752E38 end:0x80752E68
|
||||
|
||||
revolution/sc/scsystem.c:
|
||||
@@ -4412,7 +4412,7 @@ revolution/sc/scsystem.c:
|
||||
.rodata start:0x8065EE18 end:0x8065EE70
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||||
.data start:0x8073DB08 end:0x8073DDB0
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||||
.sdata start:0x8074C078 end:0x8074C1C0
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||||
.sbss start:0x8074D5EC end:0x8074D600
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||||
.sbss start:0x8074D5E8 end:0x8074D600
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||||
.bss start:0x80801DC0 end:0x80809F60
|
||||
|
||||
revolution/sc/scapi.c:
|
||||
@@ -4467,13 +4467,14 @@ revolution/pad/Pad.c:
|
||||
.text start:0x80616840 end:0x80618AB0
|
||||
.data start:0x8073DE70 end:0x8073E0B0
|
||||
.sdata start:0x8074C1F8 end:0x8074C220
|
||||
.sbss start:0x8074D648 end:0x8074D680
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||||
.sbss start:0x8074D648 end:0x8074D678
|
||||
.bss start:0x8080DBA0 end:0x8080DC20
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||||
|
||||
revolution/wpad/WPAD.c:
|
||||
.text start:0x80618AB0 end:0x80619BD0
|
||||
.data start:0x8073E0B0 end:0x8073E1F0
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||||
.sdata start:0x8074C220 end:0x8074C228
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.sbss start:0x8074D678 end:0x8074D680
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.sdata2 start:0x80752E78 end:0x80752E80
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.bss start:0x8080DC20 end:0x8080DC40
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|
||||
|
||||
+141
-2
@@ -1461,6 +1461,27 @@ config.libs = [
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Object(MatchingFor(ALL_GCN), "dolphin/gd/GDGeometry.c"),
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],
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||||
),
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||||
RevolutionLib(
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||||
"gf",
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||||
[
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Object(NonMatching, "revolution/gf/GFGeometry.cpp"),
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Object(NonMatching, "revolution/gf/GFLight.cpp"),
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||||
Object(NonMatching, "revolution/gf/GFPixel.cpp"),
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Object(NonMatching, "revolution/gf/GFTev.cpp"),
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||||
],
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||||
),
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||||
RevolutionLib(
|
||||
"aralt",
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[
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||||
Object(NonMatching, "revolution/aralt/aralt.c"),
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||||
],
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||||
),
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RevolutionLib(
|
||||
"base",
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[
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||||
Object(NonMatching, "revolution/base/PPCArch.c"),
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||||
],
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||||
),
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RevolutionLib(
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"os",
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[
|
||||
@@ -1500,6 +1521,64 @@ config.libs = [
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Object(MatchingFor("ShieldD"), "revolution/os/__ppc_eabi_init.cpp"),
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],
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),
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RevolutionLib(
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"exi",
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[
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Object(NonMatching, "revolution/exi/EXIBios.c"),
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||||
Object(NonMatching, "revolution/exi/EXIUart.c"),
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Object(NonMatching, "revolution/exi/EXICommon.c"),
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||||
],
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||||
),
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||||
RevolutionLib(
|
||||
"si",
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[
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Object(NonMatching, "revolution/si/SIBios.c"),
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Object(NonMatching, "revolution/si/SISamplingRate.c"),
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||||
],
|
||||
),
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||||
RevolutionLib(
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||||
"vi",
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||||
[
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||||
Object(NonMatching, "revolution/vi/vi.c"),
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Object(NonMatching, "revolution/vi/i2c.c"),
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Object(NonMatching, "revolution/vi/vi3in1.c"),
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||||
],
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||||
),
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RevolutionLib(
|
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"mtx",
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[
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||||
Object(NonMatching, "revolution/mtx/mtx.c"),
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Object(NonMatching, "revolution/mtx/mtxvec.c"),
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||||
Object(NonMatching, "revolution/mtx/mtx44.c"),
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Object(NonMatching, "revolution/mtx/vec.c"),
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Object(NonMatching, "revolution/mtx/quat.c"),
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||||
],
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||||
),
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||||
RevolutionLib(
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"gx",
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||||
[
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Object(NonMatching, "revolution/gx/GXInit.c", extra_cflags=["-opt nopeephole"]),
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Object(NonMatching, "revolution/gx/GXFifo.c"),
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||||
Object(NonMatching, "revolution/gx/GXAttr.c"),
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||||
Object(NonMatching, "revolution/gx/GXMisc.c"),
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||||
Object(NonMatching, "revolution/gx/GXGeometry.c"),
|
||||
Object(NonMatching, "revolution/gx/GXFrameBuf.c"),
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||||
Object(NonMatching, "revolution/gx/GXLight.c", extra_cflags=["-fp_contract off"]),
|
||||
Object(NonMatching, "revolution/gx/GXTexture.c"),
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Object(NonMatching, "revolution/gx/GXBump.c"),
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||||
Object(NonMatching, "revolution/gx/GXTev.c"),
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||||
Object(NonMatching, "revolution/gx/GXPixel.c"),
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||||
Object(NonMatching, "revolution/gx/GXDraw.c"),
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||||
Object(NonMatching, "revolution/gx/GXDisplayList.c"),
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||||
Object(NonMatching, "revolution/gx/GXVert.c"),
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||||
Object(NonMatching, "revolution/gx/GXTransform.c", extra_cflags=["-fp_contract off"]),
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Object(NonMatching, "revolution/gx/GXVerify.c"),
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Object(NonMatching, "revolution/gx/GXVerifXF.c"),
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||||
Object(NonMatching, "revolution/gx/GXVerifRAS.c"),
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||||
Object(NonMatching, "revolution/gx/GXSave.c"),
|
||||
Object(NonMatching, "revolution/gx/GXPerf.c"),
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||||
],
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||||
),
|
||||
RevolutionLib(
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||||
"dvd",
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||||
[
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||||
@@ -1513,6 +1592,26 @@ config.libs = [
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||||
Object(NonMatching, "revolution/dvd/dvd_broadway.c", extra_cflags=["-char signed"]),
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||||
],
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||||
),
|
||||
RevolutionLib(
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"ai",
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||||
[
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||||
Object(NonMatching, "revolution/ai/ai.c"),
|
||||
],
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||||
),
|
||||
RevolutionLib(
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||||
"dsp",
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||||
[
|
||||
Object(NonMatching, "revolution/dsp/dsp.c"),
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||||
Object(NonMatching, "revolution/dsp/dsp_debug.c"),
|
||||
Object(NonMatching, "revolution/dsp/dsp_task.c"),
|
||||
],
|
||||
),
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||||
RevolutionLib(
|
||||
"hio2",
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||||
[
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||||
Object(NonMatching, "revolution/hio2/hio2.c"),
|
||||
],
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||||
),
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||||
RevolutionLib(
|
||||
"nand",
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||||
[
|
||||
@@ -1525,9 +1624,23 @@ config.libs = [
|
||||
],
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||||
),
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RevolutionLib(
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||||
"fs",
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||||
"sc",
|
||||
[
|
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Object(NonMatching, "revolution/fs/fs.c"),
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||||
Object(NonMatching, "revolution/sc/scsystem.c"),
|
||||
Object(NonMatching, "revolution/sc/scapi.c"),
|
||||
Object(NonMatching, "revolution/sc/scapi_prdinfo.c"),
|
||||
],
|
||||
),
|
||||
RevolutionLib(
|
||||
"wenc",
|
||||
[
|
||||
Object(NonMatching, "revolution/wenc/wenc.c"),
|
||||
],
|
||||
),
|
||||
RevolutionLib(
|
||||
"esp",
|
||||
[
|
||||
Object(NonMatching, "revolution/esp/esp.c"),
|
||||
],
|
||||
),
|
||||
RevolutionLib(
|
||||
@@ -1539,6 +1652,12 @@ config.libs = [
|
||||
Object(NonMatching, "revolution/ipc/ipcProfile.c"),
|
||||
],
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||||
),
|
||||
RevolutionLib(
|
||||
"fs",
|
||||
[
|
||||
Object(NonMatching, "revolution/fs/fs.c"),
|
||||
],
|
||||
),
|
||||
RevolutionLib(
|
||||
"pad",
|
||||
[
|
||||
@@ -1546,6 +1665,26 @@ config.libs = [
|
||||
Object(NonMatching, "revolution/pad/Pad.c"),
|
||||
],
|
||||
),
|
||||
RevolutionLib(
|
||||
"wpad",
|
||||
[
|
||||
Object(NonMatching, "revolution/wpad/WPAD.c"),
|
||||
Object(NonMatching, "revolution/wpad/WUD.c"),
|
||||
],
|
||||
),
|
||||
RevolutionLib(
|
||||
"euart",
|
||||
[
|
||||
Object(NonMatching, "revolution/euart/euart.c"),
|
||||
],
|
||||
),
|
||||
RevolutionLib(
|
||||
"gd",
|
||||
[
|
||||
Object(NonMatching, "revolution/gd/GDBase.c"),
|
||||
Object(NonMatching, "revolution/gd/GDGeometry.c"),
|
||||
],
|
||||
),
|
||||
{
|
||||
"lib": "Runtime.PPCEABI.H",
|
||||
"mw_version": MWVersion(config.version),
|
||||
|
||||
@@ -70,6 +70,13 @@ extern int __rlwimi(int, int, int, int, int);
|
||||
extern void __dcbz(void*, int);
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||||
extern void __sync();
|
||||
extern int __abs(int);
|
||||
#else
|
||||
// to stop clangd errors
|
||||
#define __cntlzw
|
||||
#define __rlwimi
|
||||
#define __dcbz
|
||||
#define __sync
|
||||
#define __abs
|
||||
#endif
|
||||
|
||||
#ifndef __MWERKS__
|
||||
|
||||
@@ -25,21 +25,8 @@ u32 AIGetDMABytesLeft(void);
|
||||
u32 AIGetDMAStartAddr(void);
|
||||
u32 AIGetDMALength(void);
|
||||
BOOL AICheckInit(void);
|
||||
AISCallback AIRegisterStreamCallback(AISCallback callback);
|
||||
u32 AIGetStreamSampleCount(void);
|
||||
void AIResetStreamSampleCount(void);
|
||||
void AISetStreamTrigger(u32 trigger);
|
||||
u32 AIGetStreamTrigger(void);
|
||||
void AISetStreamPlayState(u32 state);
|
||||
u32 AIGetStreamPlayState(void);
|
||||
void AISetDSPSampleRate(u32 rate);
|
||||
u32 AIGetDSPSampleRate(void);
|
||||
void AISetStreamSampleRate(u32 rate);
|
||||
u32 AIGetStreamSampleRate(void);
|
||||
void AISetStreamVolLeft(u8 vol);
|
||||
u8 AIGetStreamVolLeft(void);
|
||||
void AISetStreamVolRight(u8 vol);
|
||||
u8 AIGetStreamVolRight(void);
|
||||
void AIInit(u8* stack);
|
||||
void AIReset(void);
|
||||
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
#ifndef _REVOLUTION_ARALT_H_
|
||||
#define _REVOLUTION_ARALT_H_
|
||||
|
||||
#include <revolution/types.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef void (*ARQCallback)(u32 pointerToARQRequest);
|
||||
|
||||
struct ARQRequest {
|
||||
/* 0x00 */ struct ARQRequest *next;
|
||||
/* 0x04 */ u32 owner;
|
||||
/* 0x08 */ u32 type;
|
||||
/* 0x0C */ u32 priority;
|
||||
/* 0x10 */ u32 source;
|
||||
/* 0x14 */ u32 dest;
|
||||
/* 0x18 */ u32 length;
|
||||
/* 0x1C */ ARQCallback callback;
|
||||
};
|
||||
|
||||
#define ARQ_DMA_ALIGNMENT 32
|
||||
|
||||
#define ARAM_DIR_MRAM_TO_ARAM 0x00
|
||||
#define ARAM_DIR_ARAM_TO_MRAM 0x01
|
||||
|
||||
#define ARStartDMARead(mmem, aram, len) \
|
||||
ARStartDMA(ARAM_DIR_ARAM_TO_MRAM, mmem, aram, len)
|
||||
#define ARStartDMAWrite(mmem, aram, len) \
|
||||
ARStartDMA(ARAM_DIR_MRAM_TO_ARAM, mmem, aram, len)
|
||||
|
||||
typedef struct ARQRequest ARQRequest;
|
||||
|
||||
#define ARQ_TYPE_MRAM_TO_ARAM ARAM_DIR_MRAM_TO_ARAM
|
||||
#define ARQ_TYPE_ARAM_TO_MRAM ARAM_DIR_ARAM_TO_MRAM
|
||||
|
||||
#define ARQ_PRIORITY_LOW 0
|
||||
#define ARQ_PRIORITY_HIGH 1
|
||||
|
||||
// AR
|
||||
ARQCallback ARRegisterDMACallback(ARQCallback callback);
|
||||
void ARStartDMA(u32 type, u32 mainmem_addr, u32 aram_addr, u32 length);
|
||||
u32 ARAlloc(u32 length);
|
||||
u32 ARInit(u32* stack_index_addr, u32 num_entries);
|
||||
u32 ARGetBaseAddress(void);
|
||||
u32 ARGetSize(void);
|
||||
|
||||
// ARQ
|
||||
void ARQInit(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
+11
-11
@@ -1,5 +1,5 @@
|
||||
#ifndef ESP_H
|
||||
#define ESP_H
|
||||
#ifndef _REVOLUTION_ESP_H_
|
||||
#define _REVOLUTION_ESP_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@@ -122,17 +122,17 @@ typedef struct {
|
||||
|
||||
s32 ESP_InitLib(void);
|
||||
s32 ESP_CloseLib(void);
|
||||
s32 ESP_LaunchTitle(u64, ESTicketView*);
|
||||
s32 ESP_GetTicketViews(ESTitleId, ESTicketView*, u32*);
|
||||
s32 ESP_DiGetTicketView(const void*, ESTicketView*);
|
||||
s32 ESP_DiGetTmd(ESTitleMeta*, u32*);
|
||||
s32 ESP_GetTmdView(ESTitleId, ESTmdView*, u32*);
|
||||
s32 ESP_GetDataDir(ESTitleId, char*);
|
||||
s32 ESP_GetTitleId(ESTitleId*);
|
||||
s32 ESP_GetConsumption(ESTicketId, ESLpEntry*, u32*);
|
||||
s32 ESP_LaunchTitle(u64 titleID, ESTicketView* pTicketView);
|
||||
s32 ESP_GetTicketViews(ESTitleId titleId, ESTicketView* ticketViewList, u32* ticketViewCnt);
|
||||
s32 ESP_DiGetTicketView(const void* ticket, ESTicketView* ticketView);
|
||||
s32 ESP_DiGetTmd(ESTitleMeta* tmd, u32* tmdSize);
|
||||
s32 ESP_GetTmdView(ESTitleId titleId, ESTmdView* tmdView, u32* size);
|
||||
s32 ESP_GetDataDir(ESTitleId titleId, char* dataDir);
|
||||
s32 ESP_GetTitleId(ESTitleId* titleId);
|
||||
s32 ESP_GetConsumption(ESTicketId ticketId, ESLpEntry* entries, u32* nEntries);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // ESP_H
|
||||
#endif // _REVOLUTION_ESP_H_
|
||||
|
||||
@@ -0,0 +1,61 @@
|
||||
#ifndef _REVOLUTION_EUART_H_
|
||||
#define _REVOLUTION_EUART_H_
|
||||
|
||||
#include <revolution/types.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef int UARTError;
|
||||
|
||||
typedef enum {
|
||||
kBaudHWSet = -1,
|
||||
kBaud300 = 300,
|
||||
kBaud600 = 600,
|
||||
kBaud1200 = 1200,
|
||||
kBaud1800 = 1800,
|
||||
kBaud2000 = 2000,
|
||||
kBaud2400 = 2400,
|
||||
kBaud3600 = 3600,
|
||||
kBaud4800 = 4800,
|
||||
kBaud7200 = 7200,
|
||||
kBaud9600 = 9600,
|
||||
kBaud19200 = 19200,
|
||||
kBaud38400 = 38400,
|
||||
kBaud57600 = 57600,
|
||||
kBaud115200 = 115200,
|
||||
kBaud230400 = 230400
|
||||
} UARTBaudRate;
|
||||
|
||||
enum {
|
||||
kUARTDataError = -1,
|
||||
kUARTNoError = 0,
|
||||
kUARTUnknownBaudRate,
|
||||
kUARTConfigurationError,
|
||||
kUARTBufferOverflow,
|
||||
kUARTNoData
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
EUART_ERROR_NONE = 0,
|
||||
EUART_ERROR_UNINITIALIZED,
|
||||
EUART_ERROR_CANNOT_USE,
|
||||
EUART_ERROR_CHANNEL_FULL,
|
||||
EUART_ERROR_NOT_FIND,
|
||||
EUART_ERROR_INTERNAL,
|
||||
EUART_ERROR_INVALID_PARAMETER,
|
||||
EUART_ERROR_INVALID_HANDLE,
|
||||
EUART_ERROR_COM_OPEN,
|
||||
EUART_ERROR_COMM
|
||||
} EUARTError;
|
||||
|
||||
|
||||
UARTError InitializeUART(UARTBaudRate);
|
||||
UARTError WriteUARTN(const void *, unsigned long);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -74,6 +74,8 @@ typedef struct EXIControl {
|
||||
} queue[3];
|
||||
} EXIControl;
|
||||
|
||||
extern const u32 __EXIFreq;
|
||||
|
||||
EXICallback EXISetExiCallback(s32 channel, EXICallback callback);
|
||||
|
||||
void EXIInit(void);
|
||||
@@ -96,6 +98,12 @@ int EXISelectSD(s32 chan, u32 dev, u32 freq);
|
||||
s32 EXIGetType(s32 chan, u32 dev, u32* type);
|
||||
char* EXIGetTypeString(u32 type);
|
||||
|
||||
s32 EXIGetConsoleType(void);
|
||||
void EXIWait(void);
|
||||
BOOL EXIWriteReg(s32 chan, u32 dev, u32 exiCmd, void* reg, s32 size);
|
||||
BOOL EXIReadRam(s32 chan, u32 dev, u32 exiCmd, void* buffer, s32 size, EXICallback callback);
|
||||
BOOL EXIWriteRam(s32 chan, u32 dev, u32 exiCmd, void* buffer, s32 size, EXICallback callback);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,44 @@
|
||||
#ifndef _REVOLUTION_HIO2_H_
|
||||
#define _REVOLUTION_HIO2_H_
|
||||
|
||||
#include <revolution/types.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
HIO2_DEVICE_INVALID = -1,
|
||||
HIO2_DEVICE_UNK_0 = 0,
|
||||
HIO2_DEVICE_UNK_1 = 1,
|
||||
HIO2_DEVICE_UNK_2 = 2,
|
||||
} HIO2DeviceType;
|
||||
|
||||
typedef BOOL (*HIO2EnumCallback)(HIO2DeviceType);
|
||||
typedef void (*HIO2UnkCallback)(s32);
|
||||
typedef void (*HIO2DisconnectCallback)(s32);
|
||||
|
||||
typedef struct HIO2Control {
|
||||
/* 0x00 */ HIO2DeviceType type;
|
||||
/* 0x04 */ s32 chan;
|
||||
/* 0x08 */ u32 _0x8;
|
||||
/* 0x0C */ HIO2UnkCallback exiCallback;
|
||||
/* 0x10 */ HIO2UnkCallback _0x10;
|
||||
/* 0x14 */ HIO2UnkCallback _0x14;
|
||||
/* 0x18 */ HIO2DisconnectCallback disconnectCb;
|
||||
} HIO2Control; // size 0x1C
|
||||
|
||||
|
||||
BOOL HIO2Init(void);
|
||||
BOOL HIO2EnumDevices(HIO2EnumCallback callback);
|
||||
s32 HIO2Open(HIO2DeviceType type, HIO2UnkCallback exiCb, HIO2DisconnectCallback disconnectCb);
|
||||
BOOL HIO2Close(s32 handle);
|
||||
BOOL HIO2Read(s32 handle, u32 addr, void* buffer, s32 size);
|
||||
BOOL HIO2Write(s32 handle, u32 addr, void* buffer, s32 size);
|
||||
void HIO2Exit(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -9,7 +9,7 @@ volatile u32 __PIRegs[12] AT_ADDRESS(0xCC003000);
|
||||
volatile u16 __MEMRegs[64] AT_ADDRESS(0xCC004000);
|
||||
volatile u16 __DSPRegs[] AT_ADDRESS(0xCC005000);
|
||||
volatile u32 __DIRegs[] AT_ADDRESS(0xCD006000);
|
||||
volatile u32 __SIRegs[0x100] AT_ADDRESS(0xCC006400);
|
||||
volatile u32 __SIRegs[0x100] AT_ADDRESS(0xCD006400);
|
||||
volatile u32 __EXIRegs[0x40] AT_ADDRESS(0xCD006800);
|
||||
volatile u32 __AIRegs[8] AT_ADDRESS(0xCD006C00);
|
||||
volatile u32 __IPCRegs[4] AT_ADDRESS(0xCD000000);
|
||||
@@ -19,7 +19,7 @@ volatile u32 __IPCRegs[4] AT_ADDRESS(0xCD000000);
|
||||
#define __MEMRegs ((volatile u16 *)0xCC004000)
|
||||
#define __DSPRegs ((volatile u16 *)0xCC005000)
|
||||
#define __DIRegs ((volatile u32 *)0xCD006000)
|
||||
#define __SIRegs ((volatile u32 *)0xCC006400)
|
||||
#define __SIRegs ((volatile u32 *)0xCD006400)
|
||||
#define __EXIRegs ((volatile u32 *)0xCD006800)
|
||||
#define __AIRegs ((volatile u32 *)0xCD006C00)
|
||||
#define __IPCRegs ((volatile u32 *)0xCD000000)
|
||||
|
||||
@@ -0,0 +1,263 @@
|
||||
#ifndef GXFDLSHORTCUT_H
|
||||
#define GXFDLSHORTCUT_H
|
||||
|
||||
#if __MWERKS__
|
||||
#define FAST_GPFLAGSET(line, regOrg, newFlag, regName) \
|
||||
do { \
|
||||
ASSERTMSGLINE(line, ((u32)(newFlag) & ~((1 << (regName ## _SIZE)) - 1)) == 0, "GX Internal: Register field out of range"); \
|
||||
(regOrg) = (u32) __rlwimi((int) (regOrg), \
|
||||
(int) (newFlag), \
|
||||
(regName ## _SHIFT), \
|
||||
(32-(regName ## _SHIFT)-(regName ## _SIZE)), \
|
||||
(31-(regName ## _SHIFT))); \
|
||||
} while (0)
|
||||
#else
|
||||
#define FAST_GPFLAGSET(line, regOrg, newFlag, regName)
|
||||
#endif
|
||||
|
||||
#define CP_VCD_REG_HI_TEXALL_MASK ((1UL<<CP_VCD_REG_HI_TOTAL_SIZE)-1)
|
||||
#define CP_VCD_REG_HI_TEXALL_SHIFT CP_VCD_REG_HI_TEX0_SHIFT
|
||||
#define CP_VCD_REG_LO_COLALL_MASK (CP_VCD_REG_LO_COL0_MASK|CP_VCD_REG_LO_COL1_MASK)
|
||||
#define CP_VCD_REG_LO_COLALL_SHIFT CP_VCD_REG_LO_COL0_SHIFT
|
||||
|
||||
#define TEV_REGISTERL_R8_SIZE TEV_KREGISTERL_R_SIZE
|
||||
#define TEV_REGISTERL_R8_SHIFT TEV_KREGISTERL_R_SHIFT
|
||||
#define TEV_REGISTERL_R8_MASK TEV_KREGISTERL_R_MASK
|
||||
#define SC_TEV_REGISTERL_SET_R8(line, tev_registerl, r8) \
|
||||
FAST_GPFLAGSET(line, tev_registerl, r8, TEV_REGISTERL_R8)
|
||||
|
||||
#define TEV_REGISTERL_A8_SIZE TEV_KREGISTERL_A_SIZE
|
||||
#define TEV_REGISTERL_A8_SHIFT TEV_KREGISTERL_A_SHIFT
|
||||
#define TEV_REGISTERL_A8_MASK TEV_KREGISTERL_A_MASK
|
||||
#define SC_TEV_REGISTERL_SET_A8(line, tev_registerl, a8) \
|
||||
FAST_GPFLAGSET(line, tev_registerl, a8, TEV_REGISTERL_A8)
|
||||
|
||||
#define TEV_REGISTERH_B8_SIZE TEV_KREGISTERH_B_SIZE
|
||||
#define TEV_REGISTERH_B8_SHIFT TEV_KREGISTERH_B_SHIFT
|
||||
#define TEV_REGISTERH_B8_MASK TEV_KREGISTERH_B_MASK
|
||||
#define SC_TEV_REGISTERH_SET_B8(line, tev_registerh, b8) \
|
||||
FAST_GPFLAGSET(line, tev_registerh, b8, TEV_REGISTERH_B8)
|
||||
|
||||
#define TEV_REGISTERH_G8_SIZE TEV_KREGISTERH_G_SIZE
|
||||
#define TEV_REGISTERH_G8_SHIFT TEV_KREGISTERH_G_SHIFT
|
||||
#define TEV_REGISTERH_G8_MASK TEV_KREGISTERH_G_MASK
|
||||
#define SC_TEV_REGISTERH_SET_G8(line, tev_registerh, g8) \
|
||||
FAST_GPFLAGSET(line, tev_registerh, g8, TEV_REGISTERH_G8)
|
||||
|
||||
#define TEV_REGISTERL_R8_SIZE TEV_KREGISTERL_R_SIZE
|
||||
#define TEV_REGISTERL_R8_SHIFT TEV_KREGISTERL_R_SHIFT
|
||||
#define TEV_REGISTERL_R8_MASK TEV_KREGISTERL_R_MASK
|
||||
#define SC_TEV_REGISTERL_SET_R8(line, tev_registerl, r8) \
|
||||
FAST_GPFLAGSET(line, tev_registerl, r8, TEV_REGISTERL_R8)
|
||||
|
||||
#define TEV_REGISTERL_A8_SIZE TEV_KREGISTERL_A_SIZE
|
||||
#define TEV_REGISTERL_A8_SHIFT TEV_KREGISTERL_A_SHIFT
|
||||
#define TEV_REGISTERL_A8_MASK TEV_KREGISTERL_A_MASK
|
||||
#define SC_TEV_REGISTERL_SET_A8(line, tev_registerl, a8) \
|
||||
FAST_GPFLAGSET(line, tev_registerl, a8, TEV_REGISTERL_A8)
|
||||
|
||||
#define TEV_REGISTERH_B8_SIZE TEV_KREGISTERH_B_SIZE
|
||||
#define TEV_REGISTERH_B8_SHIFT TEV_KREGISTERH_B_SHIFT
|
||||
#define TEV_REGISTERH_B8_MASK TEV_KREGISTERH_B_MASK
|
||||
#define SC_TEV_REGISTERH_SET_B8(line, tev_registerh, b8) \
|
||||
FAST_GPFLAGSET(line, tev_registerh, b8, TEV_REGISTERH_B8)
|
||||
|
||||
#define TEV_REGISTERH_G8_SIZE TEV_KREGISTERH_G_SIZE
|
||||
#define TEV_REGISTERH_G8_SHIFT TEV_KREGISTERH_G_SHIFT
|
||||
#define TEV_REGISTERH_G8_MASK TEV_KREGISTERH_G_MASK
|
||||
#define SC_TEV_REGISTERH_SET_G8(line, tev_registerh, g8) \
|
||||
FAST_GPFLAGSET(line, tev_registerh, g8, TEV_REGISTERH_G8)
|
||||
|
||||
#define XF_AMBIENT0_F_RGBA_SIZE \
|
||||
((XF_AMBIENT0_F_ALPHA_SIZE)+(XF_AMBIENT0_F_BLUE_SIZE)+ \
|
||||
(XF_AMBIENT0_F_GREEN_SIZE)+(XF_AMBIENT0_F_RED_SIZE))
|
||||
#define XF_AMBIENT0_F_RGBA_SHIFT \
|
||||
XF_AMBIENT0_F_ALPHA_SHIFT
|
||||
#define XF_AMBIENT0_F_RGBA_MASK \
|
||||
((XF_AMBIENT0_F_ALPHA_MASK)|(XF_AMBIENT0_F_BLUE_MASK)| \
|
||||
(XF_AMBIENT0_F_GREEN_MASK)|(XF_AMBIENT0_F_RED_MASK))
|
||||
#define SC_XF_AMBIENT0_F_SET_RGBA(xf_ambient0_f, rgba) { \
|
||||
xf_ambient0_f = (((unsigned long)(xf_ambient0_f)) & ~XF_AMBIENT0_F_RGBA_MASK) | (((unsigned long)(rgba)) << XF_AMBIENT0_F_RGBA_SHIFT);\
|
||||
}
|
||||
|
||||
#define XF_AMBIENT0_F_ALPHA_SIZE 8
|
||||
#define XF_AMBIENT0_F_ALPHA_SHIFT 0
|
||||
#define XF_AMBIENT0_F_ALPHA_MASK 0x000000ff
|
||||
#define XF_AMBIENT0_F_GET_ALPHA(xf_ambient0_f) \
|
||||
((((unsigned long)(xf_ambient0_f)) & XF_AMBIENT0_F_ALPHA_MASK) >> XF_AMBIENT0_F_ALPHA_SHIFT)
|
||||
#define XF_AMBIENT0_F_SET_ALPHA(xf_ambient0_f, alpha) { \
|
||||
xf_ambient0_f = (((unsigned long)(xf_ambient0_f)) & ~XF_AMBIENT0_F_ALPHA_MASK) | (((unsigned long)(alpha)) << XF_AMBIENT0_F_ALPHA_SHIFT);\
|
||||
}
|
||||
#define XF_AMBIENT0_F_BLUE_SIZE 8
|
||||
#define XF_AMBIENT0_F_BLUE_SHIFT 8
|
||||
#define XF_AMBIENT0_F_BLUE_MASK 0x0000ff00
|
||||
#define XF_AMBIENT0_F_GET_BLUE(xf_ambient0_f) \
|
||||
((((unsigned long)(xf_ambient0_f)) & XF_AMBIENT0_F_BLUE_MASK) >> XF_AMBIENT0_F_BLUE_SHIFT)
|
||||
#define XF_AMBIENT0_F_SET_BLUE(xf_ambient0_f, blue) { \
|
||||
xf_ambient0_f = (((unsigned long)(xf_ambient0_f)) & ~XF_AMBIENT0_F_BLUE_MASK) | (((unsigned long)(blue)) << XF_AMBIENT0_F_BLUE_SHIFT);\
|
||||
}
|
||||
#define XF_AMBIENT0_F_GREEN_SIZE 8
|
||||
#define XF_AMBIENT0_F_GREEN_SHIFT 16
|
||||
#define XF_AMBIENT0_F_GREEN_MASK 0x00ff0000
|
||||
#define XF_AMBIENT0_F_GET_GREEN(xf_ambient0_f) \
|
||||
((((unsigned long)(xf_ambient0_f)) & XF_AMBIENT0_F_GREEN_MASK) >> XF_AMBIENT0_F_GREEN_SHIFT)
|
||||
#define XF_AMBIENT0_F_SET_GREEN(xf_ambient0_f, green) { \
|
||||
xf_ambient0_f = (((unsigned long)(xf_ambient0_f)) & ~XF_AMBIENT0_F_GREEN_MASK) | (((unsigned long)(green)) << XF_AMBIENT0_F_GREEN_SHIFT);\
|
||||
}
|
||||
#define XF_AMBIENT0_F_RED_SIZE 8
|
||||
#define XF_AMBIENT0_F_RED_SHIFT 24
|
||||
#define XF_AMBIENT0_F_RED_MASK 0xff000000
|
||||
#define XF_AMBIENT0_F_GET_RED(xf_ambient0_f) \
|
||||
((((unsigned long)(xf_ambient0_f)) & XF_AMBIENT0_F_RED_MASK) >> XF_AMBIENT0_F_RED_SHIFT)
|
||||
#define XF_AMBIENT0_F_SET_RED(xf_ambient0_f, red) { \
|
||||
xf_ambient0_f = (((unsigned long)(xf_ambient0_f)) & ~XF_AMBIENT0_F_RED_MASK) | (((unsigned long)(red)) << XF_AMBIENT0_F_RED_SHIFT);\
|
||||
}
|
||||
|
||||
#define XF_AMBIENT0_F_RGB_SIZE \
|
||||
((XF_AMBIENT0_F_BLUE_SIZE)+(XF_AMBIENT0_F_GREEN_SIZE)+(XF_AMBIENT0_F_RED_SIZE))
|
||||
#define XF_AMBIENT0_F_RGB_SHIFT \
|
||||
XF_AMBIENT0_F_BLUE_SHIFT
|
||||
#define XF_AMBIENT0_F_RGB_MASK \
|
||||
((XF_AMBIENT0_F_BLUE_MASK)|(XF_AMBIENT0_F_GREEN_MASK)|(XF_AMBIENT0_F_RED_MASK))
|
||||
|
||||
#define SC_XF_AMBIENT0_F_SET_RGB(line, xf_ambient0_f, rgb) \
|
||||
FAST_GPFLAGSET(line, xf_ambient0_f, rgb, XF_AMBIENT0_F_RGB)
|
||||
|
||||
#define XF_AMBIENT1_F_RGBA_SIZE \
|
||||
((XF_AMBIENT1_F_ALPHA_SIZE)+(XF_AMBIENT1_F_BLUE_SIZE)+ \
|
||||
(XF_AMBIENT1_F_GREEN_SIZE)+(XF_AMBIENT1_F_RED_SIZE))
|
||||
#define XF_AMBIENT1_F_RGBA_SHIFT \
|
||||
XF_AMBIENT1_F_ALPHA_SHIFT
|
||||
#define XF_AMBIENT1_F_RGBA_MASK \
|
||||
((XF_AMBIENT1_F_ALPHA_MASK)|(XF_AMBIENT1_F_BLUE_MASK)| \
|
||||
(XF_AMBIENT1_F_GREEN_MASK)|(XF_AMBIENT1_F_RED_MASK))
|
||||
#define SC_XF_AMBIENT1_F_SET_RGBA(xf_ambient1_f, rgba) { \
|
||||
xf_ambient1_f = (((unsigned long)(xf_ambient1_f)) & ~XF_AMBIENT1_F_RGBA_MASK) | (((unsigned long)(rgba)) << XF_AMBIENT1_F_RGBA_SHIFT);\
|
||||
}
|
||||
|
||||
#define XF_AMBIENT1_F_ALPHA_SIZE 8
|
||||
#define XF_AMBIENT1_F_ALPHA_SHIFT 0
|
||||
#define XF_AMBIENT1_F_ALPHA_MASK 0x000000ff
|
||||
#define XF_AMBIENT1_F_GET_ALPHA(xf_ambient1_f) \
|
||||
((((unsigned long)(xf_ambient1_f)) & XF_AMBIENT1_F_ALPHA_MASK) >> XF_AMBIENT1_F_ALPHA_SHIFT)
|
||||
#define XF_AMBIENT1_F_SET_ALPHA(xf_ambient1_f, alpha) { \
|
||||
xf_ambient1_f = (((unsigned long)(xf_ambient1_f)) & ~XF_AMBIENT1_F_ALPHA_MASK) | (((unsigned long)(alpha)) << XF_AMBIENT1_F_ALPHA_SHIFT);\
|
||||
}
|
||||
#define XF_AMBIENT1_F_BLUE_SIZE 8
|
||||
#define XF_AMBIENT1_F_BLUE_SHIFT 8
|
||||
#define XF_AMBIENT1_F_BLUE_MASK 0x0000ff00
|
||||
#define XF_AMBIENT1_F_GET_BLUE(xf_ambient1_f) \
|
||||
((((unsigned long)(xf_ambient1_f)) & XF_AMBIENT1_F_BLUE_MASK) >> XF_AMBIENT1_F_BLUE_SHIFT)
|
||||
#define XF_AMBIENT1_F_SET_BLUE(xf_ambient1_f, blue) { \
|
||||
xf_ambient1_f = (((unsigned long)(xf_ambient1_f)) & ~XF_AMBIENT1_F_BLUE_MASK) | (((unsigned long)(blue)) << XF_AMBIENT1_F_BLUE_SHIFT);\
|
||||
}
|
||||
#define XF_AMBIENT1_F_GREEN_SIZE 8
|
||||
#define XF_AMBIENT1_F_GREEN_SHIFT 16
|
||||
#define XF_AMBIENT1_F_GREEN_MASK 0x00ff0000
|
||||
#define XF_AMBIENT1_F_GET_GREEN(xf_ambient1_f) \
|
||||
((((unsigned long)(xf_ambient1_f)) & XF_AMBIENT1_F_GREEN_MASK) >> XF_AMBIENT1_F_GREEN_SHIFT)
|
||||
#define XF_AMBIENT1_F_SET_GREEN(xf_ambient1_f, green) { \
|
||||
xf_ambient1_f = (((unsigned long)(xf_ambient1_f)) & ~XF_AMBIENT1_F_GREEN_MASK) | (((unsigned long)(green)) << XF_AMBIENT1_F_GREEN_SHIFT);\
|
||||
}
|
||||
#define XF_AMBIENT1_F_RED_SIZE 8
|
||||
#define XF_AMBIENT1_F_RED_SHIFT 24
|
||||
#define XF_AMBIENT1_F_RED_MASK 0xff000000
|
||||
#define XF_AMBIENT1_F_GET_RED(xf_ambient1_f) \
|
||||
((((unsigned long)(xf_ambient1_f)) & XF_AMBIENT1_F_RED_MASK) >> XF_AMBIENT1_F_RED_SHIFT)
|
||||
#define XF_AMBIENT1_F_SET_RED(xf_ambient1_f, red) { \
|
||||
xf_ambient1_f = (((unsigned long)(xf_ambient1_f)) & ~XF_AMBIENT1_F_RED_MASK) | (((unsigned long)(red)) << XF_AMBIENT1_F_RED_SHIFT);\
|
||||
}
|
||||
|
||||
#define XF_AMBIENT1_F_RGB_SIZE \
|
||||
((XF_AMBIENT1_F_BLUE_SIZE)+(XF_AMBIENT1_F_GREEN_SIZE)+(XF_AMBIENT1_F_RED_SIZE))
|
||||
#define XF_AMBIENT1_F_RGB_SHIFT \
|
||||
XF_AMBIENT1_F_BLUE_SHIFT
|
||||
#define XF_AMBIENT1_F_RGB_MASK \
|
||||
((XF_AMBIENT1_F_BLUE_MASK)|(XF_AMBIENT1_F_GREEN_MASK)|(XF_AMBIENT1_F_RED_MASK))
|
||||
#define SC_XF_AMBIENT1_F_SET_RGB(line, xf_ambient1_f, rgb) \
|
||||
FAST_GPFLAGSET(line, xf_ambient1_f, rgb, XF_AMBIENT1_F_RGB)
|
||||
|
||||
#define XF_MATERIAL0_F_RGBA_SIZE \
|
||||
((XF_MATERIAL0_F_ALPHA_SIZE)+(XF_MATERIAL0_F_BLUE_SIZE)+ \
|
||||
(XF_MATERIAL0_F_GREEN_SIZE)+(XF_MATERIAL0_F_RED_SIZE))
|
||||
#define XF_MATERIAL0_F_RGBA_SHIFT \
|
||||
XF_MATERIAL0_F_ALPHA_SHIFT
|
||||
#define XF_MATERIAL0_F_RGBA_MASK \
|
||||
((XF_MATERIAL0_F_ALPHA_MASK)|(XF_MATERIAL0_F_BLUE_MASK)| \
|
||||
(XF_MATERIAL0_F_GREEN_MASK)|(XF_MATERIAL0_F_RED_MASK))
|
||||
#define SC_XF_MATERIAL0_F_SET_RGBA(xf_material0_f, rgba) { \
|
||||
xf_material0_f = (((unsigned long)(xf_material0_f)) & ~XF_MATERIAL0_F_RGBA_MASK) | (((unsigned long)(rgba)) << XF_MATERIAL0_F_RGBA_SHIFT);\
|
||||
}
|
||||
|
||||
#define XF_MATERIAL0_F_RGBA_SIZE \
|
||||
((XF_MATERIAL0_F_ALPHA_SIZE)+(XF_MATERIAL0_F_BLUE_SIZE)+ \
|
||||
(XF_MATERIAL0_F_GREEN_SIZE)+(XF_MATERIAL0_F_RED_SIZE))
|
||||
#define XF_MATERIAL0_F_RGBA_SHIFT \
|
||||
XF_MATERIAL0_F_ALPHA_SHIFT
|
||||
#define XF_MATERIAL0_F_RGBA_MASK \
|
||||
((XF_MATERIAL0_F_ALPHA_MASK)|(XF_MATERIAL0_F_BLUE_MASK)| \
|
||||
(XF_MATERIAL0_F_GREEN_MASK)|(XF_MATERIAL0_F_RED_MASK))
|
||||
|
||||
#define XF_MATERIAL0_F_RGB_SIZE \
|
||||
((XF_MATERIAL0_F_BLUE_SIZE)+(XF_MATERIAL0_F_GREEN_SIZE)+(XF_MATERIAL0_F_RED_SIZE))
|
||||
#define XF_MATERIAL0_F_RGB_SHIFT \
|
||||
XF_MATERIAL0_F_BLUE_SHIFT
|
||||
#define XF_MATERIAL0_F_RGB_MASK \
|
||||
((XF_MATERIAL0_F_BLUE_MASK)|(XF_MATERIAL0_F_GREEN_MASK)|(XF_MATERIAL0_F_RED_MASK))
|
||||
#define SC_XF_MATERIAL0_F_SET_RGB(line, xf_material0_f, rgb) \
|
||||
FAST_GPFLAGSET(line, xf_material0_f, rgb, XF_MATERIAL0_F_RGB)
|
||||
|
||||
#define XF_MATERIAL0_F_RGB_SIZE \
|
||||
((XF_MATERIAL0_F_BLUE_SIZE)+(XF_MATERIAL0_F_GREEN_SIZE)+(XF_MATERIAL0_F_RED_SIZE))
|
||||
#define XF_MATERIAL0_F_RGB_SHIFT \
|
||||
XF_MATERIAL0_F_BLUE_SHIFT
|
||||
#define XF_MATERIAL0_F_RGB_MASK \
|
||||
((XF_MATERIAL0_F_BLUE_MASK)|(XF_MATERIAL0_F_GREEN_MASK)|(XF_MATERIAL0_F_RED_MASK))
|
||||
#define SC_XF_MATERIAL0_F_SET_RGB(line, xf_material0_f, rgb) \
|
||||
FAST_GPFLAGSET(line, xf_material0_f, rgb, XF_MATERIAL0_F_RGB)
|
||||
|
||||
#define XF_MATERIAL1_F_RGBA_SIZE \
|
||||
((XF_MATERIAL1_F_ALPHA_SIZE)+(XF_MATERIAL1_F_BLUE_SIZE)+ \
|
||||
(XF_MATERIAL1_F_GREEN_SIZE)+(XF_MATERIAL1_F_RED_SIZE))
|
||||
#define XF_MATERIAL1_F_RGBA_SHIFT \
|
||||
XF_MATERIAL1_F_ALPHA_SHIFT
|
||||
#define XF_MATERIAL1_F_RGBA_MASK \
|
||||
((XF_MATERIAL1_F_ALPHA_MASK)|(XF_MATERIAL1_F_BLUE_MASK)| \
|
||||
(XF_MATERIAL1_F_GREEN_MASK)|(XF_MATERIAL1_F_RED_MASK))
|
||||
#define SC_XF_MATERIAL1_F_SET_RGBA(xf_material1_f, rgba) { \
|
||||
xf_material1_f = (((unsigned long)(xf_material1_f)) & ~XF_MATERIAL1_F_RGBA_MASK) | (((unsigned long)(rgba)) << XF_MATERIAL1_F_RGBA_SHIFT);\
|
||||
}
|
||||
|
||||
|
||||
#define XF_MATERIAL1_F_RGB_SIZE \
|
||||
((XF_MATERIAL1_F_BLUE_SIZE)+(XF_MATERIAL1_F_GREEN_SIZE)+(XF_MATERIAL1_F_RED_SIZE))
|
||||
#define XF_MATERIAL1_F_RGB_SHIFT \
|
||||
XF_MATERIAL1_F_BLUE_SHIFT
|
||||
#define XF_MATERIAL1_F_RGB_MASK \
|
||||
((XF_MATERIAL1_F_BLUE_MASK)|(XF_MATERIAL1_F_GREEN_MASK)|(XF_MATERIAL1_F_RED_MASK))
|
||||
#define SC_XF_MATERIAL1_F_SET_RGB(line, xf_material1_f, rgb) \
|
||||
FAST_GPFLAGSET(line, xf_material1_f, rgb, XF_MATERIAL1_F_RGB)
|
||||
|
||||
#define XF_COLOR0CNTRL_F_LIGHT0123_SIZE \
|
||||
((XF_COLOR0CNTRL_F_LIGHT0_SIZE)+(XF_COLOR0CNTRL_F_LIGHT1_SIZE)+ \
|
||||
(XF_COLOR0CNTRL_F_LIGHT2_SIZE)+(XF_COLOR0CNTRL_F_LIGHT3_SIZE))
|
||||
#define XF_COLOR0CNTRL_F_LIGHT0123_SHIFT \
|
||||
XF_COLOR0CNTRL_F_LIGHT0_SHIFT
|
||||
#define XF_COLOR0CNTRL_F_LIGHT0123_MASK \
|
||||
((XF_COLOR0CNTRL_F_LIGHT0_MASK)|(XF_COLOR0CNTRL_F_LIGHT1_MASK)| \
|
||||
(XF_COLOR0CNTRL_F_LIGHT2_MASK)|(XF_COLOR0CNTRL_F_LIGHT3_MASK))
|
||||
#define SC_XF_COLOR0CNTRL_F_SET_LIGHT0123(line, xf_color0cntrl_f, light0123) \
|
||||
FAST_GPFLAGSET(line, xf_color0cntrl_f, light0123, XF_COLOR0CNTRL_F_LIGHT0123)
|
||||
|
||||
#define XF_COLOR0CNTRL_F_LIGHT4567_SIZE \
|
||||
((XF_COLOR0CNTRL_F_LIGHT4_SIZE)+(XF_COLOR0CNTRL_F_LIGHT5_SIZE)+ \
|
||||
(XF_COLOR0CNTRL_F_LIGHT6_SIZE)+(XF_COLOR0CNTRL_F_LIGHT7_SIZE))
|
||||
#define XF_COLOR0CNTRL_F_LIGHT4567_SHIFT \
|
||||
XF_COLOR0CNTRL_F_LIGHT4_SHIFT
|
||||
#define XF_COLOR0CNTRL_F_LIGHT4567_MASK \
|
||||
((XF_COLOR0CNTRL_F_LIGHT4_MASK)|(XF_COLOR0CNTRL_F_LIGHT5_MASK)| \
|
||||
(XF_COLOR0CNTRL_F_LIGHT6_MASK)|(XF_COLOR0CNTRL_F_LIGHT7_MASK))
|
||||
#define SC_XF_COLOR0CNTRL_F_SET_LIGHT4567(line, xf_color0cntrl_f, light4567) \
|
||||
FAST_GPFLAGSET(line, xf_color0cntrl_f, light4567, XF_COLOR0CNTRL_F_LIGHT4567)
|
||||
|
||||
#endif // GXFDLSHORTCUT_H
|
||||
@@ -0,0 +1,186 @@
|
||||
#ifndef GXREGS_H
|
||||
#define GXREGS_H
|
||||
|
||||
#include <revolution/gx.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <revolution/private/bp_reg.h>
|
||||
#include <revolution/private/cp_reg.h>
|
||||
#include <revolution/private/gen_reg.h>
|
||||
#include <revolution/private/pe_reg.h>
|
||||
#include <revolution/private/pi_reg.h>
|
||||
#include <revolution/private/ras_reg.h>
|
||||
#include <revolution/private/su_reg.h>
|
||||
#include <revolution/private/tev_reg.h>
|
||||
#include <revolution/private/tx_reg.h>
|
||||
#include <revolution/private/xf_mem.h>
|
||||
|
||||
extern volatile void* __piReg;
|
||||
extern volatile void* __cpReg;
|
||||
extern volatile void* __peReg;
|
||||
extern volatile void* __memReg;
|
||||
|
||||
#define MEM_PE_REQCOUNTH_IDX 0x27
|
||||
#define MEM_PE_REQCOUNTL_IDX 0x28
|
||||
|
||||
/* GX fifo write helpers */
|
||||
|
||||
#define GX_WRITE_U8(ub) \
|
||||
GXWGFifo.u8 = (u8)(ub)
|
||||
|
||||
#define GX_WRITE_U16(us) \
|
||||
GXWGFifo.u16 = (u16)(us)
|
||||
|
||||
#define GX_WRITE_U32(ui) \
|
||||
GXWGFifo.u32 = (u32)(ui)
|
||||
|
||||
#define GX_WRITE_F32(f) \
|
||||
GXWGFifo.f32 = (f32)(f);
|
||||
|
||||
|
||||
#define GX_PI_REG_WRITE_U32(a, d) *(vu32*)((vu8*)__piReg + (a)) = (u32)(d)
|
||||
|
||||
#define GX_PI_REG_READ_U32(a) *(vu32*)((vu8*)__piReg + (a))
|
||||
|
||||
#define GX_CP_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__cpReg + (a)) = (u16)(d)
|
||||
|
||||
#define GX_CP_REG_READ_U16(a) *(vu16*)((vu16*)__cpReg + (a))
|
||||
|
||||
#define GX_CP_REG_WRITE_U32(a, d) *(vu32*)((vu16*)__cpReg + (a)) = (u32)(d)
|
||||
|
||||
#define GX_CP_REG_READ_U32(a) *(vu32*)((vu16*)__cpReg + (a))
|
||||
|
||||
#define GX_MEM_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__memReg + (a)) = (u16)(d)
|
||||
|
||||
#define GX_MEM_REG_READ_U16(a) *(vu16*)((vu16*)__memReg + (a))
|
||||
|
||||
#define GX_PE_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__peReg + (a)) = (u16)(d)
|
||||
|
||||
#define GX_PE_REG_READ_U16(a) *(vu16*)((vu16*)__peReg + (a))
|
||||
|
||||
#define GX_CP_IDLE_REG_READ_U16(a) GX_CP_REG_READ_U16(a)
|
||||
|
||||
#define GX_PI_REG_WRITE_U32(a, d) *(vu32*)((vu8*)__piReg + (a)) = (u32)(d)
|
||||
|
||||
#define GX_PI_REG_READ_U32(a) *(vu32*)((vu8*)__piReg + (a))
|
||||
|
||||
#define GX_CP_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__cpReg + (a)) = (u16)(d)
|
||||
|
||||
#define GX_CP_REG_READ_U16(a) *(vu16*)((vu16*)__cpReg + (a))
|
||||
|
||||
#define GX_CP_REG_WRITE_U32(a, d) *(vu32*)((vu16*)__cpReg + (a)) = (u32)(d)
|
||||
|
||||
#define GX_CP_REG_READ_U32(a) *(vu32*)((vu16*)__cpReg + (a))
|
||||
|
||||
#define GX_MEM_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__memReg + (a)) = (u16)(d)
|
||||
|
||||
#define GX_MEM_REG_READ_U16(a) *(vu16*)((vu16*)__memReg + (a))
|
||||
|
||||
#define GX_PE_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__peReg + (a)) = (u16)(d)
|
||||
|
||||
#define GX_PE_REG_READ_U16(a) *(vu16*)((vu16*)__peReg + (a))
|
||||
|
||||
#define GX_CP_IDLE_REG_READ_U16(a) GX_CP_REG_READ_U16(a)
|
||||
|
||||
#define GX_WRITE_CP_STRM_REG(addr, vtxfmt, data) \
|
||||
{ \
|
||||
GX_WRITE_U8(CP_OPCODE(0, 1)); \
|
||||
GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
|
||||
GX_WRITE_U32((data)); \
|
||||
}
|
||||
|
||||
// needed to match some places
|
||||
#define GX_WRITE_CP_STRM_REG_alt(addr, vtxfmt, data, rAddr) \
|
||||
{ \
|
||||
s32 regAddr; \
|
||||
GX_WRITE_U8(CP_OPCODE(0, 1)); \
|
||||
GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
|
||||
GX_WRITE_U32((data)); \
|
||||
regAddr = rAddr; \
|
||||
}
|
||||
|
||||
// needed to match some places
|
||||
#if DEBUG
|
||||
#define GX_WRITE_CP_STRM_REG_alt2(addr, vtxfmt, data, rAddr) \
|
||||
{ \
|
||||
s32 regAddr; \
|
||||
GX_WRITE_U8(CP_OPCODE(0, 1)); \
|
||||
GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
|
||||
GX_WRITE_U32((data)); \
|
||||
regAddr = rAddr; \
|
||||
if (regAddr >= 0 && regAddr < 4) { \
|
||||
__GXData->indexBase[regAddr] = data; \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
#define GX_WRITE_CP_STRM_REG_alt2(addr, vtxfmt, data, rAddr) GX_WRITE_CP_STRM_REG(addr, vtxfmt, data)
|
||||
#endif
|
||||
|
||||
// needed to match some places
|
||||
#if DEBUG
|
||||
#define GX_WRITE_CP_STRM_REG_alt3(addr, vtxfmt, data, rAddr) \
|
||||
{ \
|
||||
s32 regAddr; \
|
||||
GX_WRITE_U8(CP_OPCODE(0, 1)); \
|
||||
GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
|
||||
GX_WRITE_U32((data)); \
|
||||
regAddr = rAddr; \
|
||||
if (regAddr >= 0 && regAddr < 4) { \
|
||||
__GXData->indexStride[regAddr] = data; \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
#define GX_WRITE_CP_STRM_REG_alt3(addr, vtxfmt, data, rAddr) GX_WRITE_CP_STRM_REG(addr, vtxfmt, data)
|
||||
#endif
|
||||
|
||||
#define GX_WRITE_XF_REG(addr, data, cnt) \
|
||||
{ \
|
||||
GX_WRITE_U8(CP_OPCODE(0, 0x2)); \
|
||||
GX_WRITE_U32(CP_XF_LOADREGS((addr), (cnt))); \
|
||||
GX_WRITE_U32((data)); \
|
||||
VERIF_XF_REG(addr, data); \
|
||||
}
|
||||
|
||||
#define GX_WRITE_XF_MEM_U32(addr, data) GX_WRITE_U32(data)
|
||||
#define GX_WRITE_XF_MEM_F32(addr, data) GX_WRITE_F32(data)
|
||||
|
||||
#define GX_WRITE_RA_REG(reg) \
|
||||
{ \
|
||||
GX_WRITE_U8(CP_OPCODE(1, 0xC)); \
|
||||
GX_WRITE_U32((reg)); \
|
||||
VERIF_RAS_REG(reg); \
|
||||
}
|
||||
|
||||
#ifdef __MWERKS__
|
||||
#define GX_DEFINE_GX_READ_COUNTER(unit) \
|
||||
inline u32 __GXRead##unit##CounterU32(u32 regAddrL, u32 regAddrH) { \
|
||||
u32 ctrH0, ctrH1, ctrL; \
|
||||
ctrH0 = GX_##unit##_REG_READ_U16(regAddrH); \
|
||||
do { \
|
||||
ctrH1 = ctrH0; \
|
||||
ctrL = GX_##unit##_REG_READ_U16(regAddrL); \
|
||||
ctrH0 = GX_##unit##_REG_READ_U16(regAddrH); \
|
||||
} while (ctrH0 != ctrH1); \
|
||||
return ((ctrH0 << 16) | ctrL); \
|
||||
}
|
||||
#else
|
||||
#define GX_DEFINE_GX_READ_COUNTER(unit)
|
||||
#endif
|
||||
|
||||
#ifdef __MWERKS__
|
||||
#define FAST_FLAG_SET(regOrg, newFlag, shift, size) \
|
||||
do { \
|
||||
(regOrg) = (u32)__rlwimi((int)(regOrg), (int)(newFlag), (shift), (32 - (shift) - (size)), (31 - (shift))); \
|
||||
} while (0);
|
||||
#else
|
||||
#define FAST_FLAG_SET(regOrg, newFlag, shift, size)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // GXREGS_H
|
||||
@@ -0,0 +1,229 @@
|
||||
#ifndef BP_REG_H
|
||||
#define BP_REG_H
|
||||
|
||||
#include <revolution/private/GXFDLShortcut.h>
|
||||
|
||||
#define BP_IMASK_RID_SIZE 8
|
||||
#define BP_IMASK_RID_SHIFT 24
|
||||
#define BP_IMASK_RID_MASK 0xff000000
|
||||
#define BP_IMASK_GET_RID(bp_imask) \
|
||||
((((unsigned long)(bp_imask)) & BP_IMASK_RID_MASK) >> BP_IMASK_RID_SHIFT)
|
||||
|
||||
#define BP_CMD_BT_SIZE 2
|
||||
#define BP_CMD_BT_SHIFT 0
|
||||
#define BP_CMD_BT_MASK 0x00000003
|
||||
#define BP_CMD_GET_BT(bp_cmd) \
|
||||
((((unsigned long)(bp_cmd)) & BP_CMD_BT_MASK) >> BP_CMD_BT_SHIFT)
|
||||
|
||||
#define BP_CMD_FMT_SIZE 2
|
||||
#define BP_CMD_FMT_SHIFT 2
|
||||
#define BP_CMD_FMT_MASK 0x0000000c
|
||||
#define BP_CMD_GET_FMT(bp_cmd) \
|
||||
((((unsigned long)(bp_cmd)) & BP_CMD_FMT_MASK) >> BP_CMD_FMT_SHIFT)
|
||||
|
||||
#define BP_CMD_BIAS_SIZE 3
|
||||
#define BP_CMD_BIAS_SHIFT 4
|
||||
#define BP_CMD_BIAS_MASK 0x00000070
|
||||
#define BP_CMD_GET_BIAS(bp_cmd) \
|
||||
((((unsigned long)(bp_cmd)) & BP_CMD_BIAS_MASK) >> BP_CMD_BIAS_SHIFT)
|
||||
|
||||
#define BP_CMD_BS_SIZE 2
|
||||
#define BP_CMD_BS_SHIFT 7
|
||||
#define BP_CMD_BS_MASK 0x00000180
|
||||
#define BP_CMD_GET_BS(bp_cmd) \
|
||||
((((unsigned long)(bp_cmd)) & BP_CMD_BS_MASK) >> BP_CMD_BS_SHIFT)
|
||||
|
||||
#define BP_CMD_M_SIZE 4
|
||||
#define BP_CMD_M_SHIFT 9
|
||||
#define BP_CMD_M_MASK 0x00001e00
|
||||
#define BP_CMD_GET_M(bp_cmd) \
|
||||
((((unsigned long)(bp_cmd)) & BP_CMD_M_MASK) >> BP_CMD_M_SHIFT)
|
||||
|
||||
#define BP_CMD_SW_SIZE 3
|
||||
#define BP_CMD_SW_SHIFT 13
|
||||
#define BP_CMD_SW_MASK 0x0000e000
|
||||
#define BP_CMD_GET_SW(bp_cmd) \
|
||||
((((unsigned long)(bp_cmd)) & BP_CMD_SW_MASK) >> BP_CMD_SW_SHIFT)
|
||||
|
||||
#define BP_CMD_TW_SIZE 3
|
||||
#define BP_CMD_TW_SHIFT 16
|
||||
#define BP_CMD_TW_MASK 0x00070000
|
||||
#define BP_CMD_GET_TW(bp_cmd) \
|
||||
((((unsigned long)(bp_cmd)) & BP_CMD_TW_MASK) >> BP_CMD_TW_SHIFT)
|
||||
|
||||
#define BP_CMD_LB_SIZE 1
|
||||
#define BP_CMD_LB_SHIFT 19
|
||||
#define BP_CMD_LB_MASK 0x00080000
|
||||
#define BP_CMD_GET_LB(bp_cmd) \
|
||||
((((unsigned long)(bp_cmd)) & BP_CMD_LB_MASK) >> BP_CMD_LB_SHIFT)
|
||||
|
||||
#define BP_CMD_FB_SIZE 1
|
||||
#define BP_CMD_FB_SHIFT 20
|
||||
#define BP_CMD_FB_MASK 0x00100000
|
||||
#define BP_CMD_GET_FB(bp_cmd) \
|
||||
((((unsigned long)(bp_cmd)) & BP_CMD_FB_MASK) >> BP_CMD_FB_SHIFT)
|
||||
|
||||
#define BP_CMD_PAD0_SIZE 3
|
||||
#define BP_CMD_PAD0_SHIFT 21
|
||||
#define BP_CMD_PAD0_MASK 0x00e00000
|
||||
#define BP_CMD_GET_PAD0(bp_cmd) \
|
||||
((((unsigned long)(bp_cmd)) & BP_CMD_PAD0_MASK) >> BP_CMD_PAD0_SHIFT)
|
||||
|
||||
#define BP_CMD_RID_SIZE 8
|
||||
#define BP_CMD_RID_SHIFT 24
|
||||
#define BP_CMD_RID_MASK 0xff000000
|
||||
#define BP_CMD_GET_RID(bp_cmd) \
|
||||
((((unsigned long)(bp_cmd)) & BP_CMD_RID_MASK) >> BP_CMD_RID_SHIFT)
|
||||
|
||||
#define BP_MTXA_MA_SIZE 11
|
||||
#define BP_MTXA_MA_SHIFT 0
|
||||
#define BP_MTXA_MA_MASK 0x000007ff
|
||||
#define BP_MTXA_GET_MA(bp_mtxa) \
|
||||
((((unsigned long)(bp_mtxa)) & BP_MTXA_MA_MASK) >> BP_MTXA_MA_SHIFT)
|
||||
|
||||
#define BP_MTXA_MB_SIZE 11
|
||||
#define BP_MTXA_MB_SHIFT 11
|
||||
#define BP_MTXA_MB_MASK 0x003ff800
|
||||
#define BP_MTXA_GET_MB(bp_mtxa) \
|
||||
((((unsigned long)(bp_mtxa)) & BP_MTXA_MB_MASK) >> BP_MTXA_MB_SHIFT)
|
||||
|
||||
#define BP_MTXA_S_SIZE 2
|
||||
#define BP_MTXA_S_SHIFT 22
|
||||
#define BP_MTXA_S_MASK 0x00c00000
|
||||
#define BP_MTXA_GET_S(bp_mtxa) \
|
||||
((((unsigned long)(bp_mtxa)) & BP_MTXA_S_MASK) >> BP_MTXA_S_SHIFT)
|
||||
|
||||
#define BP_MTXA_RID_SIZE 8
|
||||
#define BP_MTXA_RID_SHIFT 24
|
||||
#define BP_MTXA_RID_MASK 0xff000000
|
||||
#define BP_MTXA_GET_RID(bp_mtxa) \
|
||||
((((unsigned long)(bp_mtxa)) & BP_MTXA_RID_MASK) >> BP_MTXA_RID_SHIFT)
|
||||
|
||||
#define BP_MTXB_MC_SIZE 11
|
||||
#define BP_MTXB_MC_SHIFT 0
|
||||
#define BP_MTXB_MC_MASK 0x000007ff
|
||||
#define BP_MTXB_GET_MC(bp_mtxb) \
|
||||
((((unsigned long)(bp_mtxb)) & BP_MTXB_MC_MASK) >> BP_MTXB_MC_SHIFT)
|
||||
|
||||
#define BP_MTXB_MD_SIZE 11
|
||||
#define BP_MTXB_MD_SHIFT 11
|
||||
#define BP_MTXB_MD_MASK 0x003ff800
|
||||
#define BP_MTXB_GET_MD(bp_mtxb) \
|
||||
((((unsigned long)(bp_mtxb)) & BP_MTXB_MD_MASK) >> BP_MTXB_MD_SHIFT)
|
||||
|
||||
#define BP_MTXB_S_SIZE 2
|
||||
#define BP_MTXB_S_SHIFT 22
|
||||
#define BP_MTXB_S_MASK 0x00c00000
|
||||
#define BP_MTXB_GET_S(bp_mtxb) \
|
||||
((((unsigned long)(bp_mtxb)) & BP_MTXB_S_MASK) >> BP_MTXB_S_SHIFT)
|
||||
|
||||
#define BP_MTXB_RID_SIZE 8
|
||||
#define BP_MTXB_RID_SHIFT 24
|
||||
#define BP_MTXB_RID_MASK 0xff000000
|
||||
#define BP_MTXB_GET_RID(bp_mtxb) \
|
||||
((((unsigned long)(bp_mtxb)) & BP_MTXB_RID_MASK) >> BP_MTXB_RID_SHIFT)
|
||||
|
||||
#define BP_MTXC_ME_SIZE 11
|
||||
#define BP_MTXC_ME_SHIFT 0
|
||||
#define BP_MTXC_ME_MASK 0x000007ff
|
||||
#define BP_MTXC_GET_ME(bp_mtxc) \
|
||||
((((unsigned long)(bp_mtxc)) & BP_MTXC_ME_MASK) >> BP_MTXC_ME_SHIFT)
|
||||
|
||||
#define BP_MTXC_MF_SIZE 11
|
||||
#define BP_MTXC_MF_SHIFT 11
|
||||
#define BP_MTXC_MF_MASK 0x003ff800
|
||||
#define BP_MTXC_GET_MF(bp_mtxc) \
|
||||
((((unsigned long)(bp_mtxc)) & BP_MTXC_MF_MASK) >> BP_MTXC_MF_SHIFT)
|
||||
|
||||
#define BP_MTXC_S_SIZE 2
|
||||
#define BP_MTXC_S_SHIFT 22
|
||||
#define BP_MTXC_S_MASK 0x00c00000
|
||||
#define BP_MTXC_GET_S(bp_mtxc) \
|
||||
((((unsigned long)(bp_mtxc)) & BP_MTXC_S_MASK) >> BP_MTXC_S_SHIFT)
|
||||
|
||||
#define BP_MTXC_RID_SIZE 8
|
||||
#define BP_MTXC_RID_SHIFT 24
|
||||
#define BP_MTXC_RID_MASK 0xff000000
|
||||
#define BP_MTXC_GET_RID(bp_mtxc) \
|
||||
((((unsigned long)(bp_mtxc)) & BP_MTXC_RID_MASK) >> BP_MTXC_RID_SHIFT)
|
||||
|
||||
|
||||
#define SC_BP_MTXA_SET_MA(line, bp_mtxa,ma) \
|
||||
FAST_GPFLAGSET(line, bp_mtxa,ma,BP_MTXA_MA)
|
||||
|
||||
#define SC_BP_MTXA_SET_MB(line, bp_mtxa,mb) \
|
||||
FAST_GPFLAGSET(line, bp_mtxa,mb,BP_MTXA_MB)
|
||||
|
||||
#define SC_BP_MTXA_SET_S(line, bp_mtxa,s) \
|
||||
FAST_GPFLAGSET(line, bp_mtxa,s,BP_MTXA_S)
|
||||
|
||||
#define SC_BP_MTXA_SET_RID(line, bp_mtxa,rid) \
|
||||
FAST_GPFLAGSET(line, bp_mtxa,rid,BP_MTXA_RID)
|
||||
|
||||
#define SC_BP_MTXB_SET_MC(line, bp_mtxb,mc) \
|
||||
FAST_GPFLAGSET(line, bp_mtxb,mc,BP_MTXB_MC)
|
||||
|
||||
#define SC_BP_MTXB_SET_MD(line, bp_mtxb,md) \
|
||||
FAST_GPFLAGSET(line, bp_mtxb,md,BP_MTXB_MD)
|
||||
|
||||
#define SC_BP_MTXB_SET_S(line, bp_mtxb,s) \
|
||||
FAST_GPFLAGSET(line, bp_mtxb,s,BP_MTXB_S)
|
||||
|
||||
#define SC_BP_MTXB_SET_RID(line, bp_mtxb,rid) \
|
||||
FAST_GPFLAGSET(line, bp_mtxb,rid,BP_MTXB_RID)
|
||||
|
||||
#define SC_BP_MTXC_SET_ME(line, bp_mtxc,me) \
|
||||
FAST_GPFLAGSET(line, bp_mtxc,me,BP_MTXC_ME)
|
||||
|
||||
#define SC_BP_MTXC_SET_MF(line, bp_mtxc,mf) \
|
||||
FAST_GPFLAGSET(line, bp_mtxc,mf,BP_MTXC_MF)
|
||||
|
||||
#define SC_BP_MTXC_SET_S(line, bp_mtxc,s) \
|
||||
FAST_GPFLAGSET(line, bp_mtxc,s,BP_MTXC_S)
|
||||
|
||||
#define SC_BP_MTXC_SET_RID(line, bp_mtxc,rid) \
|
||||
FAST_GPFLAGSET(line, bp_mtxc,rid,BP_MTXC_RID)
|
||||
|
||||
#define SC_BP_CMD_SET_BT(line, bp_cmd,bt) \
|
||||
FAST_GPFLAGSET(line, bp_cmd,bt,BP_CMD_BT)
|
||||
|
||||
#define SC_BP_CMD_SET_FMT(line, bp_cmd,fmt) \
|
||||
FAST_GPFLAGSET(line, bp_cmd,fmt,BP_CMD_FMT)
|
||||
|
||||
#define SC_BP_CMD_SET_BIAS(line, bp_cmd,bias) \
|
||||
FAST_GPFLAGSET(line, bp_cmd,bias,BP_CMD_BIAS)
|
||||
|
||||
#define SC_BP_CMD_SET_BS(line, bp_cmd,bs) \
|
||||
FAST_GPFLAGSET(line, bp_cmd,bs,BP_CMD_BS)
|
||||
|
||||
#define SC_BP_CMD_SET_M(line, bp_cmd,m) \
|
||||
FAST_GPFLAGSET(line, bp_cmd,m,BP_CMD_M)
|
||||
|
||||
#define SC_BP_CMD_SET_SW(line, bp_cmd,sw) \
|
||||
FAST_GPFLAGSET(line, bp_cmd,sw,BP_CMD_SW)
|
||||
|
||||
#define SC_BP_CMD_SET_TW(line, bp_cmd,tw) \
|
||||
FAST_GPFLAGSET(line, bp_cmd,tw,BP_CMD_TW)
|
||||
|
||||
#define SC_BP_CMD_SET_LB(line, bp_cmd,lb) \
|
||||
FAST_GPFLAGSET(line, bp_cmd,lb,BP_CMD_LB)
|
||||
|
||||
#define SC_BP_CMD_SET_FB(line, bp_cmd,fb) \
|
||||
FAST_GPFLAGSET(line, bp_cmd,fb,BP_CMD_FB)
|
||||
|
||||
#define SC_BP_CMD_SET_PAD0(line, bp_cmd,pad0) \
|
||||
FAST_GPFLAGSET(line, bp_cmd,pad0,BP_CMD_PAD0)
|
||||
|
||||
#define SC_BP_CMD_SET_RID(line, bp_cmd,rid) \
|
||||
FAST_GPFLAGSET(line, bp_cmd,rid,BP_CMD_RID)
|
||||
|
||||
#define SC_BP_IMASK_SET_IMASK(line, bp_imask,imask) \
|
||||
FAST_GPFLAGSET(line, bp_imask,imask,BP_IMASK_IMASK)
|
||||
|
||||
#define SC_BP_IMASK_SET_PAD0(line, bp_imask,pad0) \
|
||||
FAST_GPFLAGSET(line, bp_imask,pad0,BP_IMASK_PAD0)
|
||||
|
||||
#define SC_BP_IMASK_SET_RID(line, bp_imask,rid) \
|
||||
FAST_GPFLAGSET(line, bp_imask,rid,BP_IMASK_RID)
|
||||
|
||||
#endif // BP_REG_H
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,163 @@
|
||||
#ifndef GEN_REG_H
|
||||
#define GEN_REG_H
|
||||
|
||||
#include <revolution/private/GXFDLShortcut.h>
|
||||
|
||||
#define GEN_MODE_RID_SIZE 8
|
||||
#define GEN_MODE_RID_SHIFT 24
|
||||
#define GEN_MODE_RID_MASK 0xff000000
|
||||
#define GEN_MODE_GET_RID(gen_mode) \
|
||||
((((unsigned long)(gen_mode)) & GEN_MODE_RID_MASK) >> GEN_MODE_RID_SHIFT)
|
||||
|
||||
#define GEN_MODE_NTEX_SIZE 4
|
||||
#define GEN_MODE_NTEX_SHIFT 0
|
||||
#define GEN_MODE_NTEX_MASK 0x0000000f
|
||||
#define GEN_MODE_GET_NTEX(gen_mode) \
|
||||
((((unsigned long)(gen_mode)) & GEN_MODE_NTEX_MASK) >> GEN_MODE_NTEX_SHIFT)
|
||||
|
||||
#define GEN_MODE_NTEX_SIZE 4
|
||||
#define GEN_MODE_NTEX_SHIFT 0
|
||||
#define GEN_MODE_NTEX_MASK 0x0000000f
|
||||
#define GEN_MODE_GET_NTEX(gen_mode) \
|
||||
((((unsigned long)(gen_mode)) & GEN_MODE_NTEX_MASK) >> GEN_MODE_NTEX_SHIFT)
|
||||
|
||||
#define GEN_MODE_NCOL_SIZE 3
|
||||
#define GEN_MODE_NCOL_SHIFT 4
|
||||
#define GEN_MODE_NCOL_MASK 0x00000070
|
||||
#define GEN_MODE_GET_NCOL(gen_mode) \
|
||||
((((unsigned long)(gen_mode)) & GEN_MODE_NCOL_MASK) >> GEN_MODE_NCOL_SHIFT)
|
||||
|
||||
#define GEN_MODE_PAD0_SIZE 1
|
||||
#define GEN_MODE_PAD0_SHIFT 7
|
||||
#define GEN_MODE_PAD0_MASK 0x00000080
|
||||
#define GEN_MODE_GET_PAD0(gen_mode) \
|
||||
((((unsigned long)(gen_mode)) & GEN_MODE_PAD0_MASK) >> GEN_MODE_PAD0_SHIFT)
|
||||
|
||||
#define GEN_MODE_FLAT_EN_SIZE 1
|
||||
#define GEN_MODE_FLAT_EN_SHIFT 8
|
||||
#define GEN_MODE_FLAT_EN_MASK 0x00000100
|
||||
#define GEN_MODE_GET_FLAT_EN(gen_mode) \
|
||||
((((unsigned long)(gen_mode)) & GEN_MODE_FLAT_EN_MASK) >> GEN_MODE_FLAT_EN_SHIFT)
|
||||
|
||||
#define GEN_MODE_MS_EN_SIZE 1
|
||||
#define GEN_MODE_MS_EN_SHIFT 9
|
||||
#define GEN_MODE_MS_EN_MASK 0x00000200
|
||||
#define GEN_MODE_GET_MS_EN(gen_mode) \
|
||||
((((unsigned long)(gen_mode)) & GEN_MODE_MS_EN_MASK) >> GEN_MODE_MS_EN_SHIFT)
|
||||
|
||||
#define GEN_MODE_NTEV_SIZE 4
|
||||
#define GEN_MODE_NTEV_SHIFT 10
|
||||
#define GEN_MODE_NTEV_MASK 0x00003c00
|
||||
#define GEN_MODE_GET_NTEV(gen_mode) \
|
||||
((((unsigned long)(gen_mode)) & GEN_MODE_NTEV_MASK) >> GEN_MODE_NTEV_SHIFT)
|
||||
|
||||
#define GEN_MODE_REJECT_EN_SIZE 2
|
||||
#define GEN_MODE_REJECT_EN_SHIFT 14
|
||||
#define GEN_MODE_REJECT_EN_MASK 0x0000c000
|
||||
#define GEN_MODE_GET_REJECT_EN(gen_mode) \
|
||||
((((unsigned long)(gen_mode)) & GEN_MODE_REJECT_EN_MASK) >> GEN_MODE_REJECT_EN_SHIFT)
|
||||
|
||||
#define GEN_MODE_NBMP_SIZE 3
|
||||
#define GEN_MODE_NBMP_SHIFT 16
|
||||
#define GEN_MODE_NBMP_MASK 0x00070000
|
||||
#define GEN_MODE_GET_NBMP(gen_mode) \
|
||||
((((unsigned long)(gen_mode)) & GEN_MODE_NBMP_MASK) >> GEN_MODE_NBMP_SHIFT)
|
||||
|
||||
#define GEN_MODE_ZFREEZE_SIZE 1
|
||||
#define GEN_MODE_ZFREEZE_SHIFT 19
|
||||
#define GEN_MODE_ZFREEZE_MASK 0x00080000
|
||||
#define GEN_MODE_GET_ZFREEZE(gen_mode) \
|
||||
((((unsigned long)(gen_mode)) & GEN_MODE_ZFREEZE_MASK) >> GEN_MODE_ZFREEZE_SHIFT)
|
||||
|
||||
#define GEN_MODE_PAD1_SIZE 4
|
||||
#define GEN_MODE_PAD1_SHIFT 20
|
||||
#define GEN_MODE_PAD1_MASK 0x00f00000
|
||||
#define GEN_MODE_GET_PAD1(gen_mode) \
|
||||
((((unsigned long)(gen_mode)) & GEN_MODE_PAD1_MASK) >> GEN_MODE_PAD1_SHIFT)
|
||||
|
||||
#define GEN_MODE_RID_SIZE 8
|
||||
#define GEN_MODE_RID_SHIFT 24
|
||||
#define GEN_MODE_RID_MASK 0xff000000
|
||||
#define GEN_MODE_GET_RID(gen_mode) \
|
||||
((((unsigned long)(gen_mode)) & GEN_MODE_RID_MASK) >> GEN_MODE_RID_SHIFT)
|
||||
|
||||
|
||||
#define SC_GEN_MODE_SET_NTEX(line, gen_mode,ntex) \
|
||||
FAST_GPFLAGSET(line, gen_mode,ntex,GEN_MODE_NTEX)
|
||||
|
||||
#define SC_GEN_MODE_SET_NCOL(line, gen_mode,ncol) \
|
||||
FAST_GPFLAGSET(line, gen_mode,ncol,GEN_MODE_NCOL)
|
||||
|
||||
#define SC_GEN_MODE_SET_PAD0(line, gen_mode,pad0) \
|
||||
FAST_GPFLAGSET(line, gen_mode,pad0,GEN_MODE_PAD0)
|
||||
|
||||
#define SC_GEN_MODE_SET_FLAT_EN(line, gen_mode,flat_en) \
|
||||
FAST_GPFLAGSET(line, gen_mode,flat_en,GEN_MODE_FLAT_EN)
|
||||
|
||||
#define SC_GEN_MODE_SET_MS_EN(line, gen_mode,ms_en) \
|
||||
FAST_GPFLAGSET(line, gen_mode,ms_en,GEN_MODE_MS_EN)
|
||||
|
||||
#define SC_GEN_MODE_SET_NTEV(line, gen_mode,ntev) \
|
||||
FAST_GPFLAGSET(line, gen_mode,ntev,GEN_MODE_NTEV)
|
||||
|
||||
#define SC_GEN_MODE_SET_REJECT_EN(line, gen_mode,reject_en) \
|
||||
FAST_GPFLAGSET(line, gen_mode,reject_en,GEN_MODE_REJECT_EN)
|
||||
|
||||
#define SC_GEN_MODE_SET_NBMP(line, gen_mode,nbmp) \
|
||||
FAST_GPFLAGSET(line, gen_mode,nbmp,GEN_MODE_NBMP)
|
||||
|
||||
#define SC_GEN_MODE_SET_ZFREEZE(line, gen_mode,zfreeze) \
|
||||
FAST_GPFLAGSET(line, gen_mode,zfreeze,GEN_MODE_ZFREEZE)
|
||||
|
||||
#define SC_GEN_MODE_SET_PAD1(line, gen_mode,pad1) \
|
||||
FAST_GPFLAGSET(line, gen_mode,pad1,GEN_MODE_PAD1)
|
||||
|
||||
#define SC_GEN_MODE_SET_RID(line, gen_mode,rid) \
|
||||
FAST_GPFLAGSET(line, gen_mode,rid,GEN_MODE_RID)
|
||||
|
||||
#define SC_GEN_MSLOC_SET_XS0(line, gen_msloc,xs0) \
|
||||
FAST_GPFLAGSET(line, gen_msloc,xs0,GEN_MSLOC_XS0)
|
||||
|
||||
#define SC_GEN_MSLOC_SET_YS0(line, gen_msloc,ys0) \
|
||||
FAST_GPFLAGSET(line, gen_msloc,ys0,GEN_MSLOC_YS0)
|
||||
|
||||
#define SC_GEN_MSLOC_SET_XS1(line, gen_msloc,xs1) \
|
||||
FAST_GPFLAGSET(line, gen_msloc,xs1,GEN_MSLOC_XS1)
|
||||
|
||||
#define SC_GEN_MSLOC_SET_YS1(line, gen_msloc,ys1) \
|
||||
FAST_GPFLAGSET(line, gen_msloc,ys1,GEN_MSLOC_YS1)
|
||||
|
||||
#define SC_GEN_MSLOC_SET_XS2(line, gen_msloc,xs2) \
|
||||
FAST_GPFLAGSET(line, gen_msloc,xs2,GEN_MSLOC_XS2)
|
||||
|
||||
#define SC_GEN_MSLOC_SET_YS2(line, gen_msloc,ys2) \
|
||||
FAST_GPFLAGSET(line, gen_msloc,ys2,GEN_MSLOC_YS2)
|
||||
|
||||
#define SC_GEN_MSLOC_SET_RID(line, gen_msloc,rid) \
|
||||
FAST_GPFLAGSET(line, gen_msloc,rid,GEN_MSLOC_RID)
|
||||
|
||||
#define SC_GEN_COLOR_SET_ALPHA(line, gen_color,alpha) \
|
||||
FAST_GPFLAGSET(line, gen_color,alpha,GEN_COLOR_ALPHA)
|
||||
|
||||
#define SC_GEN_COLOR_SET_BLUE(line, gen_color,blue) \
|
||||
FAST_GPFLAGSET(line, gen_color,blue,GEN_COLOR_BLUE)
|
||||
|
||||
#define SC_GEN_COLOR_SET_GREEN(line, gen_color,green) \
|
||||
FAST_GPFLAGSET(line, gen_color,green,GEN_COLOR_GREEN)
|
||||
|
||||
#define SC_GEN_COLOR_SET_RED(line, gen_color,red) \
|
||||
FAST_GPFLAGSET(line, gen_color,red,GEN_COLOR_RED)
|
||||
|
||||
#define SC_GEN_Z24_COLOR_SET_BLUE(line, gen_z24_color,blue) \
|
||||
FAST_GPFLAGSET(line, gen_z24_color,blue,GEN_Z24_COLOR_BLUE)
|
||||
|
||||
#define SC_GEN_Z24_COLOR_SET_GREEN(line, gen_z24_color,green) \
|
||||
FAST_GPFLAGSET(line, gen_z24_color,green,GEN_Z24_COLOR_GREEN)
|
||||
|
||||
#define SC_GEN_Z24_COLOR_SET_RED(line, gen_z24_color,red) \
|
||||
FAST_GPFLAGSET(line, gen_z24_color,red,GEN_Z24_COLOR_RED)
|
||||
|
||||
#define SC_GEN_Z24_COLOR_SET_PAD0(line, gen_z24_color,pad0) \
|
||||
FAST_GPFLAGSET(line, gen_z24_color,pad0,GEN_Z24_COLOR_PAD0)
|
||||
|
||||
#endif // GEN_REG_H
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,73 @@
|
||||
#ifndef PI_REG_H
|
||||
#define PI_REG_H
|
||||
|
||||
#include <revolution/private/GXFDLShortcut.h>
|
||||
|
||||
#define PI_REG_INTSR 0x000
|
||||
#define PI_REG_INTMSK 0x004
|
||||
#define PI_REG_CPBAS 0x00C
|
||||
#define PI_REG_CPTOP 0x010
|
||||
#define PI_REG_CPWRT 0x014
|
||||
#define PI_REG_CPABT 0x018
|
||||
#define PI_REG_PIESR 0x01C
|
||||
#define PI_REG_PIEAR 0x020
|
||||
#define PI_REG_CONFIG 0x024
|
||||
#define PI_REG_DURAR 0x028
|
||||
#define PI_REG_CHIPID 0x02C
|
||||
#define PI_REG_STRGTH 0x030
|
||||
#define PI_REG_CPUDBB 0x034
|
||||
|
||||
#define PI_REGSP_CP 0x0C000000
|
||||
#define PI_REGSP_PE 0x0C001000
|
||||
#define PI_REGSP_VI 0x0C002000
|
||||
#define PI_REGSP_PI 0x0C003000
|
||||
#define PI_REGSP_MEM 0x0C004000
|
||||
#define PI_REGSP_DSP 0x0C005000
|
||||
#define PI_REGSP_IO 0x0C006000
|
||||
#define PI_GFXSP 0x0C008000
|
||||
|
||||
#define PI_CPWRT_REG_CPWRT_SIZE 24
|
||||
#define PI_CPWRT_REG_CPWRT_SHIFT 5
|
||||
#define PI_CPWRT_REG_CPWRT_MASK 0x1fffffe0
|
||||
#define PI_CPWRT_REG_GET_CPWRT(pi_cpwrt_reg) \
|
||||
((((unsigned long)(pi_cpwrt_reg)) & PI_CPWRT_REG_CPWRT_MASK) >> PI_CPWRT_REG_CPWRT_SHIFT)
|
||||
|
||||
#define XF_PERF0_F_PERF_B_SIZE 5
|
||||
#define XF_PERF0_F_PERF_B_SHIFT 5
|
||||
#define XF_PERF0_F_PERF_B_MASK 0x000003e0
|
||||
#define XF_PERF0_F_GET_PERF_B(xf_perf0_f) \
|
||||
((((unsigned long)(xf_perf0_f)) & XF_PERF0_F_PERF_B_MASK) >> XF_PERF0_F_PERF_B_SHIFT)
|
||||
|
||||
#define XF_PERF0_F_PERF_C_SIZE 5
|
||||
#define XF_PERF0_F_PERF_C_SHIFT 10
|
||||
#define XF_PERF0_F_PERF_C_MASK 0x00007c00
|
||||
#define XF_PERF0_F_GET_PERF_C(xf_perf0_f) \
|
||||
((((unsigned long)(xf_perf0_f)) & XF_PERF0_F_PERF_C_MASK) >> XF_PERF0_F_PERF_C_SHIFT)
|
||||
|
||||
#define XF_PERF0_F_PERF_D_SIZE 5
|
||||
#define XF_PERF0_F_PERF_D_SHIFT 15
|
||||
#define XF_PERF0_F_PERF_D_MASK 0x000f8000
|
||||
#define XF_PERF0_F_GET_PERF_D(xf_perf0_f) \
|
||||
((((unsigned long)(xf_perf0_f)) & XF_PERF0_F_PERF_D_MASK) >> XF_PERF0_F_PERF_D_SHIFT)
|
||||
|
||||
#define XF_PERF0_F_PERF_A_SIZE 5
|
||||
#define XF_PERF0_F_PERF_A_SHIFT 0
|
||||
#define XF_PERF0_F_PERF_A_MASK 0x0000001f
|
||||
#define XF_PERF0_F_GET_PERF_A(xf_perf0_f) \
|
||||
((((unsigned long)(xf_perf0_f)) & XF_PERF0_F_PERF_A_MASK) >> XF_PERF0_F_PERF_A_SHIFT)
|
||||
|
||||
#define PI_CPWRT_REG_CPWRAP_SIZE 1
|
||||
#define PI_CPWRT_REG_CPWRAP_SHIFT 29
|
||||
#define PI_CPWRT_REG_CPWRAP_MASK 0x20000000
|
||||
#define PI_CPWRT_REG_GET_CPWRAP(pi_cpwrt_reg) \
|
||||
((((unsigned long)(pi_cpwrt_reg)) & PI_CPWRT_REG_CPWRAP_MASK) >> PI_CPWRT_REG_CPWRAP_SHIFT)
|
||||
|
||||
|
||||
#define SC_PI_CPWRT_REG_SET_CPWRT(line, pi_cpwrt_reg,cpwrt) \
|
||||
FAST_GPFLAGSET(line, pi_cpwrt_reg,cpwrt,PI_CPWRT_REG_CPWRT)
|
||||
|
||||
#define SC_PI_CPWRT_REG_SET_CPWRAP(line, pi_cpwrt_reg,cpwrap) \
|
||||
FAST_GPFLAGSET(line, pi_cpwrt_reg,cpwrap,PI_CPWRT_REG_CPWRAP)
|
||||
|
||||
|
||||
#endif // PI_REG_H
|
||||
@@ -0,0 +1,232 @@
|
||||
#ifndef RAS_REG
|
||||
#define RAS_REG
|
||||
|
||||
#define RAS1_TREF_RID_SIZE 8
|
||||
#define RAS1_TREF_RID_SHIFT 24
|
||||
#define RAS1_TREF_RID_MASK 0xff000000
|
||||
#define RAS1_TREF_GET_RID(ras1_tref) \
|
||||
((((unsigned long)(ras1_tref)) & RAS1_TREF_RID_MASK) >> RAS1_TREF_RID_SHIFT)
|
||||
|
||||
#define RAS1_IREF_RID_SIZE 8
|
||||
#define RAS1_IREF_RID_SHIFT 24
|
||||
#define RAS1_IREF_RID_MASK 0xff000000
|
||||
#define RAS1_IREF_GET_RID(ras1_iref) \
|
||||
((((unsigned long)(ras1_iref)) & RAS1_IREF_RID_MASK) >> RAS1_IREF_RID_SHIFT)
|
||||
|
||||
#define RAS_PERF_SELA_SIZE 5
|
||||
#define RAS_PERF_SELA_SHIFT 0
|
||||
#define RAS_PERF_SELA_MASK 0x0000001f
|
||||
#define RAS_PERF_GET_SELA(ras_perf) \
|
||||
((((unsigned long)(ras_perf)) & RAS_PERF_SELA_MASK) >> RAS_PERF_SELA_SHIFT)
|
||||
|
||||
#define RAS_PERF_SELB_SIZE 5
|
||||
#define RAS_PERF_SELB_SHIFT 5
|
||||
#define RAS_PERF_SELB_MASK 0x000003e0
|
||||
#define RAS_PERF_GET_SELB(ras_perf) \
|
||||
((((unsigned long)(ras_perf)) & RAS_PERF_SELB_MASK) >> RAS_PERF_SELB_SHIFT)
|
||||
|
||||
#define RAS_PERF_NTEV_SIZE 5
|
||||
#define RAS_PERF_NTEV_SHIFT 10
|
||||
#define RAS_PERF_NTEV_MASK 0x00007c00
|
||||
#define RAS_PERF_GET_NTEV(ras_perf) \
|
||||
((((unsigned long)(ras_perf)) & RAS_PERF_NTEV_MASK) >> RAS_PERF_NTEV_SHIFT)
|
||||
|
||||
#define RAS_PERF_NBMP_SIZE 3
|
||||
#define RAS_PERF_NBMP_SHIFT 15
|
||||
#define RAS_PERF_NBMP_MASK 0x00038000
|
||||
#define RAS_PERF_GET_NBMP(ras_perf) \
|
||||
((((unsigned long)(ras_perf)) & RAS_PERF_NBMP_MASK) >> RAS_PERF_NBMP_SHIFT)
|
||||
|
||||
#define RAS_PERF_NBR_SIZE 3
|
||||
#define RAS_PERF_NBR_SHIFT 18
|
||||
#define RAS_PERF_NBR_MASK 0x001c0000
|
||||
#define RAS_PERF_GET_NBR(ras_perf) \
|
||||
((((unsigned long)(ras_perf)) & RAS_PERF_NBR_MASK) >> RAS_PERF_NBR_SHIFT)
|
||||
|
||||
#define RAS_PERF_PAD0_SIZE 3
|
||||
#define RAS_PERF_PAD0_SHIFT 21
|
||||
#define RAS_PERF_PAD0_MASK 0x00e00000
|
||||
#define RAS_PERF_GET_PAD0(ras_perf) \
|
||||
((((unsigned long)(ras_perf)) & RAS_PERF_PAD0_MASK) >> RAS_PERF_PAD0_SHIFT)
|
||||
#define RAS_PERF_RID_SIZE 8
|
||||
#define RAS_PERF_RID_SHIFT 24
|
||||
#define RAS_PERF_RID_MASK 0xff000000
|
||||
#define RAS_PERF_GET_RID(ras_perf) \
|
||||
((((unsigned long)(ras_perf)) & RAS_PERF_RID_MASK) >> RAS_PERF_RID_SHIFT)
|
||||
|
||||
#define RAS_PERF_TOTAL_SIZE 32
|
||||
#define RAS_PERF(selA, selB, ntev, nbmp, nbr, rid) \
|
||||
((((unsigned long)(selA)) << RAS_PERF_SELA_SHIFT) | \
|
||||
(((unsigned long)(selB)) << RAS_PERF_SELB_SHIFT) | \
|
||||
(((unsigned long)(ntev)) << RAS_PERF_NTEV_SHIFT) | \
|
||||
(((unsigned long)(nbmp)) << RAS_PERF_NBMP_SHIFT) | \
|
||||
(((unsigned long)(nbr)) << RAS_PERF_NBR_SHIFT) | \
|
||||
(((unsigned long)(rid)) << RAS_PERF_RID_SHIFT))
|
||||
|
||||
#define RAS1_TREF_TI0_SIZE 3
|
||||
#define RAS1_TREF_TI0_SHIFT 0
|
||||
#define RAS1_TREF_TI0_MASK 0x00000007
|
||||
#define RAS1_TREF_GET_TI0(ras1_tref) \
|
||||
((((unsigned long)(ras1_tref)) & RAS1_TREF_TI0_MASK) >> RAS1_TREF_TI0_SHIFT)
|
||||
|
||||
#define RAS1_TREF_TC0_SIZE 3
|
||||
#define RAS1_TREF_TC0_SHIFT 3
|
||||
#define RAS1_TREF_TC0_MASK 0x00000038
|
||||
#define RAS1_TREF_GET_TC0(ras1_tref) \
|
||||
((((unsigned long)(ras1_tref)) & RAS1_TREF_TC0_MASK) >> RAS1_TREF_TC0_SHIFT)
|
||||
|
||||
#define RAS1_TREF_TE0_SIZE 1
|
||||
#define RAS1_TREF_TE0_SHIFT 6
|
||||
#define RAS1_TREF_TE0_MASK 0x00000040
|
||||
#define RAS1_TREF_GET_TE0(ras1_tref) \
|
||||
((((unsigned long)(ras1_tref)) & RAS1_TREF_TE0_MASK) >> RAS1_TREF_TE0_SHIFT)
|
||||
|
||||
#define RAS1_TREF_CC0_SIZE 3
|
||||
#define RAS1_TREF_CC0_SHIFT 7
|
||||
#define RAS1_TREF_CC0_MASK 0x00000380
|
||||
#define RAS1_TREF_GET_CC0(ras1_tref) \
|
||||
((((unsigned long)(ras1_tref)) & RAS1_TREF_CC0_MASK) >> RAS1_TREF_CC0_SHIFT)
|
||||
|
||||
#define RAS1_TREF_PAD0_SIZE 2
|
||||
#define RAS1_TREF_PAD0_SHIFT 10
|
||||
#define RAS1_TREF_PAD0_MASK 0x00000c00
|
||||
#define RAS1_TREF_GET_PAD0(ras1_tref) \
|
||||
((((unsigned long)(ras1_tref)) & RAS1_TREF_PAD0_MASK) >> RAS1_TREF_PAD0_SHIFT)
|
||||
|
||||
#define RAS1_TREF_TI1_SIZE 3
|
||||
#define RAS1_TREF_TI1_SHIFT 12
|
||||
#define RAS1_TREF_TI1_MASK 0x00007000
|
||||
#define RAS1_TREF_GET_TI1(ras1_tref) \
|
||||
((((unsigned long)(ras1_tref)) & RAS1_TREF_TI1_MASK) >> RAS1_TREF_TI1_SHIFT)
|
||||
|
||||
#define RAS1_TREF_TC1_SIZE 3
|
||||
#define RAS1_TREF_TC1_SHIFT 15
|
||||
#define RAS1_TREF_TC1_MASK 0x00038000
|
||||
#define RAS1_TREF_GET_TC1(ras1_tref) \
|
||||
((((unsigned long)(ras1_tref)) & RAS1_TREF_TC1_MASK) >> RAS1_TREF_TC1_SHIFT)
|
||||
|
||||
#define RAS1_TREF_TE1_SIZE 1
|
||||
#define RAS1_TREF_TE1_SHIFT 18
|
||||
#define RAS1_TREF_TE1_MASK 0x00040000
|
||||
#define RAS1_TREF_GET_TE1(ras1_tref) \
|
||||
((((unsigned long)(ras1_tref)) & RAS1_TREF_TE1_MASK) >> RAS1_TREF_TE1_SHIFT)
|
||||
|
||||
#define RAS1_TREF_CC1_SIZE 3
|
||||
#define RAS1_TREF_CC1_SHIFT 19
|
||||
#define RAS1_TREF_CC1_MASK 0x00380000
|
||||
#define RAS1_TREF_GET_CC1(ras1_tref) \
|
||||
((((unsigned long)(ras1_tref)) & RAS1_TREF_CC1_MASK) >> RAS1_TREF_CC1_SHIFT)
|
||||
|
||||
#define RAS1_TREF_PAD1_SIZE 2
|
||||
#define RAS1_TREF_PAD1_SHIFT 22
|
||||
#define RAS1_TREF_PAD1_MASK 0x00c00000
|
||||
#define RAS1_TREF_GET_PAD1(ras1_tref) \
|
||||
((((unsigned long)(ras1_tref)) & RAS1_TREF_PAD1_MASK) >> RAS1_TREF_PAD1_SHIFT)
|
||||
|
||||
#define RAS1_TREF_RID_SIZE 8
|
||||
#define RAS1_TREF_RID_SHIFT 24
|
||||
#define RAS1_TREF_RID_MASK 0xff000000
|
||||
#define RAS1_TREF_GET_RID(ras1_tref) \
|
||||
((((unsigned long)(ras1_tref)) & RAS1_TREF_RID_MASK) >> RAS1_TREF_RID_SHIFT)
|
||||
|
||||
#define SC_RAS1_SS_SET_SS0(line, ras1_ss,ss0) \
|
||||
FAST_GPFLAGSET(line, ras1_ss,ss0,RAS1_SS_SS0)
|
||||
|
||||
#define SC_RAS1_SS_SET_TS0(line, ras1_ss,ts0) \
|
||||
FAST_GPFLAGSET(line, ras1_ss,ts0,RAS1_SS_TS0)
|
||||
|
||||
#define SC_RAS1_SS_SET_SS1(line, ras1_ss,ss1) \
|
||||
FAST_GPFLAGSET(line, ras1_ss,ss1,RAS1_SS_SS1)
|
||||
|
||||
#define SC_RAS1_SS_SET_TS1(line, ras1_ss,ts1) \
|
||||
FAST_GPFLAGSET(line, ras1_ss,ts1,RAS1_SS_TS1)
|
||||
|
||||
#define SC_RAS1_SS_SET_PAD0(line, ras1_ss,pad0) \
|
||||
FAST_GPFLAGSET(line, ras1_ss,pad0,RAS1_SS_PAD0)
|
||||
|
||||
#define SC_RAS1_SS_SET_RID(line, ras1_ss,rid) \
|
||||
FAST_GPFLAGSET(line, ras1_ss,rid,RAS1_SS_RID)
|
||||
|
||||
#define SC_RAS1_IREF_SET_BI0(line, ras1_iref,bi0) \
|
||||
FAST_GPFLAGSET(line, ras1_iref,bi0,RAS1_IREF_BI0)
|
||||
|
||||
#define SC_RAS1_IREF_SET_BC0(line, ras1_iref,bc0) \
|
||||
FAST_GPFLAGSET(line, ras1_iref,bc0,RAS1_IREF_BC0)
|
||||
|
||||
#define SC_RAS1_IREF_SET_BI1(line, ras1_iref,bi1) \
|
||||
FAST_GPFLAGSET(line, ras1_iref,bi1,RAS1_IREF_BI1)
|
||||
|
||||
#define SC_RAS1_IREF_SET_BC1(line, ras1_iref,bc1) \
|
||||
FAST_GPFLAGSET(line, ras1_iref,bc1,RAS1_IREF_BC1)
|
||||
|
||||
#define SC_RAS1_IREF_SET_BI2(line, ras1_iref,bi2) \
|
||||
FAST_GPFLAGSET(line, ras1_iref,bi2,RAS1_IREF_BI2)
|
||||
|
||||
#define SC_RAS1_IREF_SET_BC2(line, ras1_iref,bc2) \
|
||||
FAST_GPFLAGSET(line, ras1_iref,bc2,RAS1_IREF_BC2)
|
||||
|
||||
#define SC_RAS1_IREF_SET_BI3(line, ras1_iref,bi3) \
|
||||
FAST_GPFLAGSET(line, ras1_iref,bi3,RAS1_IREF_BI3)
|
||||
|
||||
#define SC_RAS1_IREF_SET_BC3(line, ras1_iref,bc3) \
|
||||
FAST_GPFLAGSET(line, ras1_iref,bc3,RAS1_IREF_BC3)
|
||||
|
||||
#define SC_RAS1_IREF_SET_RID(line, ras1_iref,rid) \
|
||||
FAST_GPFLAGSET(line, ras1_iref,rid,RAS1_IREF_RID)
|
||||
|
||||
#define SC_RAS1_TREF_SET_TI0(line, ras1_tref,ti0) \
|
||||
FAST_GPFLAGSET(line, ras1_tref,ti0,RAS1_TREF_TI0)
|
||||
|
||||
#define SC_RAS1_TREF_SET_TC0(line, ras1_tref,tc0) \
|
||||
FAST_GPFLAGSET(line, ras1_tref,tc0,RAS1_TREF_TC0)
|
||||
|
||||
#define SC_RAS1_TREF_SET_TE0(line, ras1_tref,te0) \
|
||||
FAST_GPFLAGSET(line, ras1_tref,te0,RAS1_TREF_TE0)
|
||||
|
||||
#define SC_RAS1_TREF_SET_CC0(line, ras1_tref,cc0) \
|
||||
FAST_GPFLAGSET(line, ras1_tref,cc0,RAS1_TREF_CC0)
|
||||
|
||||
#define SC_RAS1_TREF_SET_PAD0(line, ras1_tref,pad0) \
|
||||
FAST_GPFLAGSET(line, ras1_tref,pad0,RAS1_TREF_PAD0)
|
||||
|
||||
#define SC_RAS1_TREF_SET_TI1(line, ras1_tref,ti1) \
|
||||
FAST_GPFLAGSET(line, ras1_tref,ti1,RAS1_TREF_TI1)
|
||||
|
||||
#define SC_RAS1_TREF_SET_TC1(line, ras1_tref,tc1) \
|
||||
FAST_GPFLAGSET(line, ras1_tref,tc1,RAS1_TREF_TC1)
|
||||
|
||||
#define SC_RAS1_TREF_SET_TE1(line, ras1_tref,te1) \
|
||||
FAST_GPFLAGSET(line, ras1_tref,te1,RAS1_TREF_TE1)
|
||||
|
||||
#define SC_RAS1_TREF_SET_CC1(line, ras1_tref,cc1) \
|
||||
FAST_GPFLAGSET(line, ras1_tref,cc1,RAS1_TREF_CC1)
|
||||
|
||||
#define SC_RAS1_TREF_SET_PAD1(line, ras1_tref,pad1) \
|
||||
FAST_GPFLAGSET(line, ras1_tref,pad1,RAS1_TREF_PAD1)
|
||||
|
||||
#define SC_RAS1_TREF_SET_RID(line, ras1_tref,rid) \
|
||||
FAST_GPFLAGSET(line, ras1_tref,rid,RAS1_TREF_RID)
|
||||
|
||||
#define SC_RAS_PERF_SET_SELA(line, ras_perf,selA) \
|
||||
FAST_GPFLAGSET(line, ras_perf,selA,RAS_PERF_SELA)
|
||||
|
||||
#define SC_RAS_PERF_SET_SELB(line, ras_perf,selB) \
|
||||
FAST_GPFLAGSET(line, ras_perf,selB,RAS_PERF_SELB)
|
||||
|
||||
#define SC_RAS_PERF_SET_NTEV(line, ras_perf,ntev) \
|
||||
FAST_GPFLAGSET(line, ras_perf,ntev,RAS_PERF_NTEV)
|
||||
|
||||
#define SC_RAS_PERF_SET_NBMP(line, ras_perf,nbmp) \
|
||||
FAST_GPFLAGSET(line, ras_perf,nbmp,RAS_PERF_NBMP)
|
||||
|
||||
#define SC_RAS_PERF_SET_NBR(line, ras_perf,nbr) \
|
||||
FAST_GPFLAGSET(line, ras_perf,nbr,RAS_PERF_NBR)
|
||||
|
||||
#define SC_RAS_PERF_SET_PAD0(line, ras_perf,pad0) \
|
||||
FAST_GPFLAGSET(line, ras_perf,pad0,RAS_PERF_PAD0)
|
||||
|
||||
#define SC_RAS_PERF_SET_RID(line, ras_perf,rid) \
|
||||
FAST_GPFLAGSET(line, ras_perf,rid,RAS_PERF_RID)
|
||||
|
||||
|
||||
#endif // RAS_REG
|
||||
@@ -0,0 +1,387 @@
|
||||
#ifndef SU_REG_H
|
||||
#define SU_REG_H
|
||||
|
||||
#define SU_LPSIZE_RID_SIZE 8
|
||||
#define SU_LPSIZE_RID_SHIFT 24
|
||||
#define SU_LPSIZE_RID_MASK 0xff000000
|
||||
#define SU_LPSIZE_GET_RID(su_lpsize) \
|
||||
((((unsigned long)(su_lpsize)) & SU_LPSIZE_RID_MASK) >> SU_LPSIZE_RID_SHIFT)
|
||||
|
||||
|
||||
#define SU_TS0_RID_SIZE 8
|
||||
#define SU_TS0_RID_SHIFT 24
|
||||
#define SU_TS0_RID_MASK 0xff000000
|
||||
#define SU_TS0_GET_RID(su_ts0) \
|
||||
((((unsigned long)(su_ts0)) & SU_TS0_RID_MASK) >> SU_TS0_RID_SHIFT)
|
||||
|
||||
#define SU_TS1_RID_SIZE 8
|
||||
#define SU_TS1_RID_SHIFT 24
|
||||
#define SU_TS1_RID_MASK 0xff000000
|
||||
#define SU_TS1_GET_RID(su_ts1) \
|
||||
((((unsigned long)(su_ts1)) & SU_TS1_RID_MASK) >> SU_TS1_RID_SHIFT)
|
||||
|
||||
#define SU_SCIS0_RID_SIZE 8
|
||||
#define SU_SCIS0_RID_SHIFT 24
|
||||
#define SU_SCIS0_RID_MASK 0xff000000
|
||||
#define SU_SCIS0_GET_RID(su_scis0) \
|
||||
((((unsigned long)(su_scis0)) & SU_SCIS0_RID_MASK) >> SU_SCIS0_RID_SHIFT)
|
||||
|
||||
#define SU_PERF_SELA_SIZE 3
|
||||
#define SU_PERF_SELA_SHIFT 0
|
||||
#define SU_PERF_SELA_MASK 0x00000007
|
||||
#define SU_PERF_GET_SELA(su_perf) \
|
||||
((((unsigned long)(su_perf)) & SU_PERF_SELA_MASK) >> SU_PERF_SELA_SHIFT)
|
||||
|
||||
#define SU_SCIS1_RID_SIZE 8
|
||||
#define SU_SCIS1_RID_SHIFT 24
|
||||
#define SU_SCIS1_RID_MASK 0xff000000
|
||||
#define SU_SCIS1_GET_RID(su_scis1) \
|
||||
((((unsigned long)(su_scis1)) & SU_SCIS1_RID_MASK) >> SU_SCIS1_RID_SHIFT)
|
||||
|
||||
#define SU_PERF_NTEX_SIZE 4
|
||||
#define SU_PERF_NTEX_SHIFT 6
|
||||
#define SU_PERF_NTEX_MASK 0x000003c0
|
||||
#define SU_PERF_GET_NTEX(su_perf) \
|
||||
((((unsigned long)(su_perf)) & SU_PERF_NTEX_MASK) >> SU_PERF_NTEX_SHIFT)
|
||||
|
||||
#define SU_PERF_NCOL_SIZE 2
|
||||
#define SU_PERF_NCOL_SHIFT 10
|
||||
#define SU_PERF_NCOL_MASK 0x00000c00
|
||||
#define SU_PERF_GET_NCOL(su_perf) \
|
||||
((((unsigned long)(su_perf)) & SU_PERF_NCOL_MASK) >> SU_PERF_NCOL_SHIFT)
|
||||
|
||||
#define SU_PERF_SELB_SIZE 3
|
||||
#define SU_PERF_SELB_SHIFT 3
|
||||
#define SU_PERF_SELB_MASK 0x00000038
|
||||
#define SU_PERF_GET_SELB(su_perf) \
|
||||
((((unsigned long)(su_perf)) & SU_PERF_SELB_MASK) >> SU_PERF_SELB_SHIFT)
|
||||
|
||||
#define SU_PERF_REJF_SIZE 2
|
||||
#define SU_PERF_REJF_SHIFT 12
|
||||
#define SU_PERF_REJF_MASK 0x00003000
|
||||
#define SU_PERF_GET_REJF(su_perf) \
|
||||
((((unsigned long)(su_perf)) & SU_PERF_REJF_MASK) >> SU_PERF_REJF_SHIFT)
|
||||
|
||||
#define SU_PERF_REJS_SIZE 2
|
||||
#define SU_PERF_REJS_SHIFT 14
|
||||
#define SU_PERF_REJS_MASK 0x0000c000
|
||||
#define SU_PERF_GET_REJS(su_perf) \
|
||||
((((unsigned long)(su_perf)) & SU_PERF_REJS_MASK) >> SU_PERF_REJS_SHIFT)
|
||||
|
||||
#define SU_PERF_CMD_SIZE 2
|
||||
#define SU_PERF_CMD_SHIFT 16
|
||||
#define SU_PERF_CMD_MASK 0x00030000
|
||||
#define SU_PERF_GET_CMD(su_perf) \
|
||||
((((unsigned long)(su_perf)) & SU_PERF_CMD_MASK) >> SU_PERF_CMD_SHIFT)
|
||||
|
||||
#define SU_PERF_PAD0_SIZE 2
|
||||
#define SU_PERF_PAD0_SHIFT 18
|
||||
#define SU_PERF_PAD0_MASK 0x000c0000
|
||||
#define SU_PERF_GET_PAD0(su_perf) \
|
||||
((((unsigned long)(su_perf)) & SU_PERF_PAD0_MASK) >> SU_PERF_PAD0_SHIFT)
|
||||
|
||||
#define SU_PERF_EN_SIZE 2
|
||||
#define SU_PERF_EN_SHIFT 20
|
||||
#define SU_PERF_EN_MASK 0x00300000
|
||||
#define SU_PERF_GET_EN(su_perf) \
|
||||
((((unsigned long)(su_perf)) & SU_PERF_EN_MASK) >> SU_PERF_EN_SHIFT)
|
||||
|
||||
#define SU_PERF_PWR_EN_SIZE 2
|
||||
#define SU_PERF_PWR_EN_SHIFT 22
|
||||
#define SU_PERF_PWR_EN_MASK 0x00c00000
|
||||
#define SU_PERF_GET_PWR_EN(su_perf) \
|
||||
((((unsigned long)(su_perf)) & SU_PERF_PWR_EN_MASK) >> SU_PERF_PWR_EN_SHIFT)
|
||||
|
||||
#define SU_PERF_RID_SIZE 8
|
||||
#define SU_PERF_RID_SHIFT 24
|
||||
#define SU_PERF_RID_MASK 0xff000000
|
||||
#define SU_PERF_GET_RID(su_perf) \
|
||||
((((unsigned long)(su_perf)) & SU_PERF_RID_MASK) >> SU_PERF_RID_SHIFT)
|
||||
|
||||
#define SU_PERF_TOTAL_SIZE 32
|
||||
#define SU_PERF(selA, selB, ntex, ncol, rejf, rejs, cmd, en, pwr_en, rid) \
|
||||
((((unsigned long)(selA)) << SU_PERF_SELA_SHIFT) | \
|
||||
(((unsigned long)(selB)) << SU_PERF_SELB_SHIFT) | \
|
||||
(((unsigned long)(ntex)) << SU_PERF_NTEX_SHIFT) | \
|
||||
(((unsigned long)(ncol)) << SU_PERF_NCOL_SHIFT) | \
|
||||
(((unsigned long)(rejf)) << SU_PERF_REJF_SHIFT) | \
|
||||
(((unsigned long)(rejs)) << SU_PERF_REJS_SHIFT) | \
|
||||
(((unsigned long)(cmd)) << SU_PERF_CMD_SHIFT) | \
|
||||
(((unsigned long)(en)) << SU_PERF_EN_SHIFT) | \
|
||||
(((unsigned long)(pwr_en)) << SU_PERF_PWR_EN_SHIFT) | \
|
||||
(((unsigned long)(rid)) << SU_PERF_RID_SHIFT))
|
||||
|
||||
#define SU_LPSIZE_LSIZE_SIZE 8
|
||||
#define SU_LPSIZE_LSIZE_SHIFT 0
|
||||
#define SU_LPSIZE_LSIZE_MASK 0x000000ff
|
||||
#define SU_LPSIZE_GET_LSIZE(su_lpsize) \
|
||||
((((unsigned long)(su_lpsize)) & SU_LPSIZE_LSIZE_MASK) >> SU_LPSIZE_LSIZE_SHIFT)
|
||||
|
||||
#define SU_LPSIZE_PSIZE_SIZE 8
|
||||
#define SU_LPSIZE_PSIZE_SHIFT 8
|
||||
#define SU_LPSIZE_PSIZE_MASK 0x0000ff00
|
||||
#define SU_LPSIZE_GET_PSIZE(su_lpsize) \
|
||||
((((unsigned long)(su_lpsize)) & SU_LPSIZE_PSIZE_MASK) >> SU_LPSIZE_PSIZE_SHIFT)
|
||||
|
||||
#define SU_LPSIZE_LTOFF_SIZE 3
|
||||
#define SU_LPSIZE_LTOFF_SHIFT 16
|
||||
#define SU_LPSIZE_LTOFF_MASK 0x00070000
|
||||
#define SU_LPSIZE_GET_LTOFF(su_lpsize) \
|
||||
((((unsigned long)(su_lpsize)) & SU_LPSIZE_LTOFF_MASK) >> SU_LPSIZE_LTOFF_SHIFT)
|
||||
|
||||
#define SU_LPSIZE_PTOFF_SIZE 3
|
||||
#define SU_LPSIZE_PTOFF_SHIFT 19
|
||||
#define SU_LPSIZE_PTOFF_MASK 0x00380000
|
||||
#define SU_LPSIZE_GET_PTOFF(su_lpsize) \
|
||||
((((unsigned long)(su_lpsize)) & SU_LPSIZE_PTOFF_MASK) >> SU_LPSIZE_PTOFF_SHIFT)
|
||||
|
||||
#define SU_LPSIZE_FIELDMODE_SIZE 1
|
||||
#define SU_LPSIZE_FIELDMODE_SHIFT 22
|
||||
#define SU_LPSIZE_FIELDMODE_MASK 0x00400000
|
||||
#define SU_LPSIZE_GET_FIELDMODE(su_lpsize) \
|
||||
((((unsigned long)(su_lpsize)) & SU_LPSIZE_FIELDMODE_MASK) >> SU_LPSIZE_FIELDMODE_SHIFT)
|
||||
|
||||
#define SU_LPSIZE_PAD0_SIZE 1
|
||||
#define SU_LPSIZE_PAD0_SHIFT 23
|
||||
#define SU_LPSIZE_PAD0_MASK 0x00800000
|
||||
#define SU_LPSIZE_GET_PAD0(su_lpsize) \
|
||||
((((unsigned long)(su_lpsize)) & SU_LPSIZE_PAD0_MASK) >> SU_LPSIZE_PAD0_SHIFT)
|
||||
|
||||
#define SU_LPSIZE_RID_SIZE 8
|
||||
#define SU_LPSIZE_RID_SHIFT 24
|
||||
#define SU_LPSIZE_RID_MASK 0xff000000
|
||||
#define SU_LPSIZE_GET_RID(su_lpsize) \
|
||||
((((unsigned long)(su_lpsize)) & SU_LPSIZE_RID_MASK) >> SU_LPSIZE_RID_SHIFT)
|
||||
|
||||
#define SU_TS0_SSIZE_SIZE 16
|
||||
#define SU_TS0_SSIZE_SHIFT 0
|
||||
#define SU_TS0_SSIZE_MASK 0x0000ffff
|
||||
#define SU_TS0_GET_SSIZE(su_ts0) \
|
||||
((((unsigned long)(su_ts0)) & SU_TS0_SSIZE_MASK) >> SU_TS0_SSIZE_SHIFT)
|
||||
|
||||
#define SU_TS0_BS_SIZE 1
|
||||
#define SU_TS0_BS_SHIFT 16
|
||||
#define SU_TS0_BS_MASK 0x00010000
|
||||
#define SU_TS0_GET_BS(su_ts0) \
|
||||
((((unsigned long)(su_ts0)) & SU_TS0_BS_MASK) >> SU_TS0_BS_SHIFT)
|
||||
|
||||
#define SU_TS0_WS_SIZE 1
|
||||
#define SU_TS0_WS_SHIFT 17
|
||||
#define SU_TS0_WS_MASK 0x00020000
|
||||
#define SU_TS0_GET_WS(su_ts0) \
|
||||
((((unsigned long)(su_ts0)) & SU_TS0_WS_MASK) >> SU_TS0_WS_SHIFT)
|
||||
|
||||
#define SU_TS0_LF_SIZE 1
|
||||
#define SU_TS0_LF_SHIFT 18
|
||||
#define SU_TS0_LF_MASK 0x00040000
|
||||
#define SU_TS0_GET_LF(su_ts0) \
|
||||
((((unsigned long)(su_ts0)) & SU_TS0_LF_MASK) >> SU_TS0_LF_SHIFT)
|
||||
|
||||
#define SU_TS0_PF_SIZE 1
|
||||
#define SU_TS0_PF_SHIFT 19
|
||||
#define SU_TS0_PF_MASK 0x00080000
|
||||
#define SU_TS0_GET_PF(su_ts0) \
|
||||
((((unsigned long)(su_ts0)) & SU_TS0_PF_MASK) >> SU_TS0_PF_SHIFT)
|
||||
|
||||
#define SU_TS0_PAD0_SIZE 4
|
||||
#define SU_TS0_PAD0_SHIFT 20
|
||||
#define SU_TS0_PAD0_MASK 0x00f00000
|
||||
#define SU_TS0_GET_PAD0(su_ts0) \
|
||||
((((unsigned long)(su_ts0)) & SU_TS0_PAD0_MASK) >> SU_TS0_PAD0_SHIFT)
|
||||
|
||||
#define SU_TS0_RID_SIZE 8
|
||||
#define SU_TS0_RID_SHIFT 24
|
||||
#define SU_TS0_RID_MASK 0xff000000
|
||||
#define SU_TS0_GET_RID(su_ts0) \
|
||||
((((unsigned long)(su_ts0)) & SU_TS0_RID_MASK) >> SU_TS0_RID_SHIFT)
|
||||
|
||||
#define SU_SSMASK_SSMASK_SIZE 24
|
||||
#define SU_SSMASK_SSMASK_SHIFT 0
|
||||
#define SU_SSMASK_SSMASK_MASK 0x00ffffff
|
||||
#define SU_SSMASK_GET_SSMASK(su_ssmask) \
|
||||
((((unsigned long)(su_ssmask)) & SU_SSMASK_SSMASK_MASK) >> SU_SSMASK_SSMASK_SHIFT)
|
||||
|
||||
#define SU_SSMASK_RID_SIZE 8
|
||||
#define SU_SSMASK_RID_SHIFT 24
|
||||
#define SU_SSMASK_RID_MASK 0xff000000
|
||||
#define SU_SSMASK_GET_RID(su_ssmask) \
|
||||
((((unsigned long)(su_ssmask)) & SU_SSMASK_RID_MASK) >> SU_SSMASK_RID_SHIFT)
|
||||
|
||||
#define SU_SSMASK_TOTAL_SIZE 32
|
||||
#define SU_SSMASK(ssmask, rid) \
|
||||
((((unsigned long)(ssmask)) << SU_SSMASK_SSMASK_SHIFT) | \
|
||||
(((unsigned long)(rid)) << SU_SSMASK_RID_SHIFT))
|
||||
|
||||
#define SU_SCIS0_SY0_SIZE 11
|
||||
#define SU_SCIS0_SY0_SHIFT 0
|
||||
#define SU_SCIS0_SY0_MASK 0x000007ff
|
||||
#define SU_SCIS0_GET_SY0(su_scis0) \
|
||||
((((unsigned long)(su_scis0)) & SU_SCIS0_SY0_MASK) >> SU_SCIS0_SY0_SHIFT)
|
||||
#define SU_SCIS0_SET_SY0(su_scis0, sy0) { \
|
||||
su_scis0 = (((unsigned long)(su_scis0)) & ~SU_SCIS0_SY0_MASK) | (((unsigned long)(sy0)) << SU_SCIS0_SY0_SHIFT);\
|
||||
}
|
||||
|
||||
#define SU_SCIS0_SX0_SIZE 11
|
||||
#define SU_SCIS0_SX0_SHIFT 12
|
||||
#define SU_SCIS0_SX0_MASK 0x007ff000
|
||||
#define SU_SCIS0_GET_SX0(su_scis0) \
|
||||
((((unsigned long)(su_scis0)) & SU_SCIS0_SX0_MASK) >> SU_SCIS0_SX0_SHIFT)
|
||||
#define SU_SCIS0_SET_SX0(su_scis0, sx0) { \
|
||||
su_scis0 = (((unsigned long)(su_scis0)) & ~SU_SCIS0_SX0_MASK) | (((unsigned long)(sx0)) << SU_SCIS0_SX0_SHIFT);\
|
||||
}
|
||||
|
||||
#define SU_SCIS0_PAD1_SIZE 1
|
||||
#define SU_SCIS0_PAD1_SHIFT 23
|
||||
#define SU_SCIS0_PAD1_MASK 0x00800000
|
||||
#define SU_SCIS0_GET_PAD1(su_scis0) \
|
||||
((((unsigned long)(su_scis0)) & SU_SCIS0_PAD1_MASK) >> SU_SCIS0_PAD1_SHIFT)
|
||||
#define SU_SCIS0_SET_PAD1(su_scis0, pad1) { \
|
||||
su_scis0 = (((unsigned long)(su_scis0)) & ~SU_SCIS0_PAD1_MASK) | (((unsigned long)(pad1)) << SU_SCIS0_PAD1_SHIFT);\
|
||||
}
|
||||
|
||||
#define SU_SCIS1_SY1_SIZE 11
|
||||
#define SU_SCIS1_SY1_SHIFT 0
|
||||
#define SU_SCIS1_SY1_MASK 0x000007ff
|
||||
#define SU_SCIS1_GET_SY1(su_scis1) \
|
||||
((((unsigned long)(su_scis1)) & SU_SCIS1_SY1_MASK) >> SU_SCIS1_SY1_SHIFT)
|
||||
#define SU_SCIS1_SET_SY1(su_scis1, sy1) { \
|
||||
su_scis1 = (((unsigned long)(su_scis1)) & ~SU_SCIS1_SY1_MASK) | (((unsigned long)(sy1)) << SU_SCIS1_SY1_SHIFT);\
|
||||
}
|
||||
|
||||
#define SU_SCIS1_SX1_SIZE 11
|
||||
#define SU_SCIS1_SX1_SHIFT 12
|
||||
#define SU_SCIS1_SX1_MASK 0x007ff000
|
||||
#define SU_SCIS1_GET_SX1(su_scis1) \
|
||||
((((unsigned long)(su_scis1)) & SU_SCIS1_SX1_MASK) >> SU_SCIS1_SX1_SHIFT)
|
||||
#define SU_SCIS1_SET_SX1(su_scis1, sx1) { \
|
||||
su_scis1 = (((unsigned long)(su_scis1)) & ~SU_SCIS1_SX1_MASK) | (((unsigned long)(sx1)) << SU_SCIS1_SX1_SHIFT);\
|
||||
}
|
||||
|
||||
#define SC_SU_SCIS0_SET_SY0(line, su_scis0,sy0) \
|
||||
FAST_GPFLAGSET(line, su_scis0,sy0,SU_SCIS0_SY0)
|
||||
|
||||
#define SC_SU_SCIS0_SET_PAD0(line, su_scis0,pad0) \
|
||||
FAST_GPFLAGSET(line, su_scis0,pad0,SU_SCIS0_PAD0)
|
||||
|
||||
#define SC_SU_SCIS0_SET_SX0(line, su_scis0,sx0) \
|
||||
FAST_GPFLAGSET(line, su_scis0,sx0,SU_SCIS0_SX0)
|
||||
|
||||
#define SC_SU_SCIS0_SET_PAD1(line, su_scis0,pad1) \
|
||||
FAST_GPFLAGSET(line, su_scis0,pad1,SU_SCIS0_PAD1)
|
||||
|
||||
#define SC_SU_SCIS0_SET_RID(line, su_scis0,rid) \
|
||||
FAST_GPFLAGSET(line, su_scis0,rid,SU_SCIS0_RID)
|
||||
|
||||
#define SC_SU_SCIS1_SET_SY1(line, su_scis1,sy1) \
|
||||
FAST_GPFLAGSET(line, su_scis1,sy1,SU_SCIS1_SY1)
|
||||
|
||||
#define SC_SU_SCIS1_SET_PAD0(line, su_scis1,pad0) \
|
||||
FAST_GPFLAGSET(line, su_scis1,pad0,SU_SCIS1_PAD0)
|
||||
|
||||
#define SC_SU_SCIS1_SET_SX1(line, su_scis1,sx1) \
|
||||
FAST_GPFLAGSET(line, su_scis1,sx1,SU_SCIS1_SX1)
|
||||
|
||||
#define SC_SU_SCIS1_SET_PAD1(line, su_scis1,pad1) \
|
||||
FAST_GPFLAGSET(line, su_scis1,pad1,SU_SCIS1_PAD1)
|
||||
|
||||
#define SC_SU_SCIS1_SET_RID(line, su_scis1,rid) \
|
||||
FAST_GPFLAGSET(line, su_scis1,rid,SU_SCIS1_RID)
|
||||
|
||||
#define SC_SU_LPSIZE_SET_LSIZE(line, su_lpsize,lsize) \
|
||||
FAST_GPFLAGSET(line, su_lpsize,lsize,SU_LPSIZE_LSIZE)
|
||||
|
||||
#define SC_SU_LPSIZE_SET_PSIZE(line, su_lpsize,psize) \
|
||||
FAST_GPFLAGSET(line, su_lpsize,psize,SU_LPSIZE_PSIZE)
|
||||
|
||||
#define SC_SU_LPSIZE_SET_LTOFF(line, su_lpsize,ltoff) \
|
||||
FAST_GPFLAGSET(line, su_lpsize,ltoff,SU_LPSIZE_LTOFF)
|
||||
|
||||
#define SC_SU_LPSIZE_SET_PTOFF(line, su_lpsize,ptoff) \
|
||||
FAST_GPFLAGSET(line, su_lpsize,ptoff,SU_LPSIZE_PTOFF)
|
||||
|
||||
#define SC_SU_LPSIZE_SET_FIELDMODE(line, su_lpsize,fieldmode) \
|
||||
FAST_GPFLAGSET(line, su_lpsize,fieldmode,SU_LPSIZE_FIELDMODE)
|
||||
|
||||
#define SC_SU_LPSIZE_SET_PAD0(line, su_lpsize,pad0) \
|
||||
FAST_GPFLAGSET(line, su_lpsize,pad0,SU_LPSIZE_PAD0)
|
||||
|
||||
#define SC_SU_LPSIZE_SET_RID(line, su_lpsize,rid) \
|
||||
FAST_GPFLAGSET(line, su_lpsize,rid,SU_LPSIZE_RID)
|
||||
|
||||
#define SC_SU_TS0_SET_SSIZE(line, su_ts0,ssize) \
|
||||
FAST_GPFLAGSET(line, su_ts0,ssize,SU_TS0_SSIZE)
|
||||
|
||||
#define SC_SU_TS0_SET_BS(line, su_ts0,bs) \
|
||||
FAST_GPFLAGSET(line, su_ts0,bs,SU_TS0_BS)
|
||||
|
||||
#define SC_SU_TS0_SET_WS(line, su_ts0,ws) \
|
||||
FAST_GPFLAGSET(line, su_ts0,ws,SU_TS0_WS)
|
||||
|
||||
#define SC_SU_TS0_SET_LF(line, su_ts0,lf) \
|
||||
FAST_GPFLAGSET(line, su_ts0,lf,SU_TS0_LF)
|
||||
|
||||
#define SC_SU_TS0_SET_PF(line, su_ts0,pf) \
|
||||
FAST_GPFLAGSET(line, su_ts0,pf,SU_TS0_PF)
|
||||
|
||||
#define SC_SU_TS0_SET_PAD0(line, su_ts0,pad0) \
|
||||
FAST_GPFLAGSET(line, su_ts0,pad0,SU_TS0_PAD0)
|
||||
|
||||
#define SC_SU_TS0_SET_RID(line, su_ts0,rid) \
|
||||
FAST_GPFLAGSET(line, su_ts0,rid,SU_TS0_RID)
|
||||
|
||||
#define SC_SU_TS1_SET_TSIZE(line, su_ts1,tsize) \
|
||||
FAST_GPFLAGSET(line, su_ts1,tsize,SU_TS1_TSIZE)
|
||||
|
||||
#define SC_SU_TS1_SET_BT(line, su_ts1,bt) \
|
||||
FAST_GPFLAGSET(line, su_ts1,bt,SU_TS1_BT)
|
||||
|
||||
#define SC_SU_TS1_SET_WT(line, su_ts1,wt) \
|
||||
FAST_GPFLAGSET(line, su_ts1,wt,SU_TS1_WT)
|
||||
|
||||
#define SC_SU_TS1_SET_PAD0(line, su_ts1,pad0) \
|
||||
FAST_GPFLAGSET(line, su_ts1,pad0,SU_TS1_PAD0)
|
||||
|
||||
#define SC_SU_TS1_SET_RID(line, su_ts1,rid) \
|
||||
FAST_GPFLAGSET(line, su_ts1,rid,SU_TS1_RID)
|
||||
|
||||
#define SC_SU_PERF_SET_SELA(line, su_perf,selA) \
|
||||
FAST_GPFLAGSET(line, su_perf,selA,SU_PERF_SELA)
|
||||
|
||||
#define SC_SU_PERF_SET_SELB(line, su_perf,selB) \
|
||||
FAST_GPFLAGSET(line, su_perf,selB,SU_PERF_SELB)
|
||||
|
||||
#define SC_SU_PERF_SET_NTEX(line, su_perf,ntex) \
|
||||
FAST_GPFLAGSET(line, su_perf,ntex,SU_PERF_NTEX)
|
||||
|
||||
#define SC_SU_PERF_SET_NCOL(line, su_perf,ncol) \
|
||||
FAST_GPFLAGSET(line, su_perf,ncol,SU_PERF_NCOL)
|
||||
|
||||
#define SC_SU_PERF_SET_REJF(line, su_perf,rejf) \
|
||||
FAST_GPFLAGSET(line, su_perf,rejf,SU_PERF_REJF)
|
||||
|
||||
#define SC_SU_PERF_SET_REJS(line, su_perf,rejs) \
|
||||
FAST_GPFLAGSET(line, su_perf,rejs,SU_PERF_REJS)
|
||||
|
||||
#define SC_SU_PERF_SET_CMD(line, su_perf,cmd) \
|
||||
FAST_GPFLAGSET(line, su_perf,cmd,SU_PERF_CMD)
|
||||
|
||||
#define SC_SU_PERF_SET_PAD0(line, su_perf,pad0) \
|
||||
FAST_GPFLAGSET(line, su_perf,pad0,SU_PERF_PAD0)
|
||||
|
||||
#define SC_SU_PERF_SET_EN(line, su_perf,en) \
|
||||
FAST_GPFLAGSET(line, su_perf,en,SU_PERF_EN)
|
||||
|
||||
#define SC_SU_PERF_SET_PWR_EN(line, su_perf,pwr_en) \
|
||||
FAST_GPFLAGSET(line, su_perf,pwr_en,SU_PERF_PWR_EN)
|
||||
|
||||
#define SC_SU_PERF_SET_RID(line, su_perf,rid) \
|
||||
FAST_GPFLAGSET(line, su_perf,rid,SU_PERF_RID)
|
||||
|
||||
#define SC_SU_SSMASK_SET_SSMASK(line, su_ssmask,ssmask) \
|
||||
FAST_GPFLAGSET(line, su_ssmask,ssmask,SU_SSMASK_SSMASK)
|
||||
|
||||
#define SC_SU_SSMASK_SET_RID(line, su_ssmask,rid) \
|
||||
FAST_GPFLAGSET(line, su_ssmask,rid,SU_SSMASK_RID)
|
||||
|
||||
|
||||
#endif // SU_REG_H
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user