encounter/objdiff
0
0
Fork 0
mirror of https://github.com/encounter/objdiff.git synced 2026-07-10 12:18:36 -07:00
Code Issues Packages Projects Releases Wiki Activity

Improve local branch relocation handling

Browse Source 
Reworks the local-branch handling logic to be more
unified: scan_instructions does all the work up front,
and process_instruction / display_instruction can
simply use the calculated branch destination instead
of performing their own is-relocation-target-
function-local checks.

(Hopefully) Fixes #192
This commit is contained in:
Luke Street
2025-05-07 22:53:10 -06:00
parent 34220a8e26
commit 0c48d711c7
21 changed files with 1253 additions and 226 deletions
Download Patch File Download Diff File Expand all files Collapse all files
objdiff-core/src/arch/arm.rs
+16 -18
View File
@@ -15,7 +15,7 @@ use crate::{
diff::{ArmArchVersion, ArmR9Usage, DiffObjConfig, display::InstructionPart},
obj::{
InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef, ResolvedRelocation,
ScannedInstruction, Section, SectionKind, Symbol, SymbolFlag, SymbolFlagSet, SymbolKind,
Section, SectionKind, Symbol, SymbolFlag, SymbolFlagSet, SymbolKind,
},
};
@@ -187,14 +187,14 @@ impl Arch for ArchArm {
self.disasm_modes = Self::get_mapping_symbols(sections, symbols);
}
fn scan_instructions(
fn scan_instructions_internal(
&self,
address: u64,
code: &[u8],
section_index: usize,
_relocations: &[Relocation],
diff_config: &DiffObjConfig,
) -> Result<Vec<ScannedInstruction>> {
) -> Result<Vec<InstructionRef>> {
let start_addr = address as u32;
let end_addr = start_addr + code.len() as u32;
@@ -219,7 +219,7 @@ impl Arch for ArchArm {
let mut next_mapping = mappings_iter.next();
let ins_count = code.len() / mode.instruction_size(start_addr);
let mut ops = Vec::<ScannedInstruction>::with_capacity(ins_count);
let mut ops = Vec::<InstructionRef>::with_capacity(ins_count);
let parse_flags = self.parse_flags(diff_config);
@@ -235,12 +235,10 @@ impl Arch for ArchArm {
let data = &code[(address - start_addr) as usize..];
if data.len() < ins_size {
// Push the remainder as data
ops.push(ScannedInstruction {
ins_ref: InstructionRef {
address: address as u64,
size: data.len() as u8,
opcode: u16::MAX,
},
ops.push(InstructionRef {
address: address as u64,
size: data.len() as u8,
opcode: u16::MAX,
branch_dest: None,
});
break;
@@ -256,12 +254,10 @@ impl Arch for ArchArm {
}
_ => {
// Invalid instruction size
ops.push(ScannedInstruction {
ins_ref: InstructionRef {
address: address as u64,
size: ins_size as u8,
opcode: u16::MAX,
},
ops.push(InstructionRef {
address: address as u64,
size: ins_size as u8,
opcode: u16::MAX,
branch_dest: None,
});
address += ins_size as u32;
@@ -325,8 +321,10 @@ impl Arch for ArchArm {
unarm::ParseMode::Data => (u16::MAX, None),
};
ops.push(ScannedInstruction {
ins_ref: InstructionRef { address: address as u64, size: ins_size as u8, opcode },
ops.push(InstructionRef {
address: address as u64,
size: ins_size as u8,
opcode,
branch_dest: branch_dest.map(|x| x as u64),
});
address += ins_size as u32;
objdiff-core/src/arch/arm64.rs
+15 -14
View File
@@ -18,7 +18,6 @@ use crate::{
diff::{DiffObjConfig, display::InstructionPart},
obj::{
InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef, ResolvedRelocation,
ScannedInstruction,
},
};
@@ -30,16 +29,16 @@ impl ArchArm64 {
}
impl Arch for ArchArm64 {
fn scan_instructions(
fn scan_instructions_internal(
&self,
address: u64,
code: &[u8],
_section_index: usize,
_relocations: &[Relocation],
_diff_config: &DiffObjConfig,
) -> Result<Vec<ScannedInstruction>> {
) -> Result<Vec<InstructionRef>> {
let start_address = address;
let mut ops = Vec::<ScannedInstruction>::with_capacity(code.len() / 4);
let mut ops = Vec::<InstructionRef>::with_capacity(code.len() / 4);
let mut reader = U8Reader::new(code);
let decoder = InstDecoder::default();
@@ -58,8 +57,10 @@ impl Arch for ArchArm64 {
DecodeError::InvalidOpcode
| DecodeError::InvalidOperand
| DecodeError::IncompleteDecoder => {
ops.push(ScannedInstruction {
ins_ref: InstructionRef { address, size: 4, opcode: u16::MAX },
ops.push(InstructionRef {
address,
size: 4,
opcode: u16::MAX,
branch_dest: None,
});
continue;
@@ -68,9 +69,9 @@ impl Arch for ArchArm64 {
}
let opcode = opcode_to_u16(ins.opcode);
let ins_ref = InstructionRef { address, size: 4, opcode };
let branch_dest = branch_dest(ins_ref, &code[offset as usize..offset as usize + 4]);
ops.push(ScannedInstruction { ins_ref, branch_dest });
let branch_dest =
branch_dest(opcode, address, &code[offset as usize..offset as usize + 4]);
ops.push(InstructionRef { address, size: 4, opcode, branch_dest });
}
Ok(ops)
@@ -163,7 +164,7 @@ impl Arch for ArchArm64 {
}
}
fn branch_dest(ins_ref: InstructionRef, code: &[u8]) -> Option<u64> {
fn branch_dest(opcode: u16, address: u64, code: &[u8]) -> Option<u64> {
const OPCODE_B: u16 = opcode_to_u16(Opcode::B);
const OPCODE_BL: u16 = opcode_to_u16(Opcode::BL);
const OPCODE_BCC: u16 = opcode_to_u16(Opcode::Bcc(0));
@@ -173,21 +174,21 @@ fn branch_dest(ins_ref: InstructionRef, code: &[u8]) -> Option<u64> {
const OPCODE_TBNZ: u16 = opcode_to_u16(Opcode::TBNZ);
let word = u32::from_le_bytes(code.try_into().ok()?);
match ins_ref.opcode {
match opcode {
OPCODE_B | OPCODE_BL => {
let offset = ((word & 0x03ff_ffff) << 2) as i32;
let extended_offset = (offset << 4) >> 4;
ins_ref.address.checked_add_signed(extended_offset as i64)
address.checked_add_signed(extended_offset as i64)
}
OPCODE_BCC | OPCODE_CBZ | OPCODE_CBNZ => {
let offset = (word as i32 & 0x00ff_ffe0) >> 3;
let extended_offset = (offset << 11) >> 11;
ins_ref.address.checked_add_signed(extended_offset as i64)
address.checked_add_signed(extended_offset as i64)
}
OPCODE_TBZ | OPCODE_TBNZ => {
let offset = (word as i32 & 0x0007_ffe0) >> 3;
let extended_offset = (offset << 16) >> 16;
ins_ref.address.checked_add_signed(extended_offset as i64)
address.checked_add_signed(extended_offset as i64)
}
_ => None,
}
objdiff-core/src/arch/mips.rs
+7 -38
View File
@@ -3,7 +3,6 @@ use alloc::{
string::{String, ToString},
vec::Vec,
};
use core::ops::Range;
use anyhow::{Result, bail};
use object::{Endian as _, Object as _, ObjectSection as _, ObjectSymbol as _, elf};
@@ -19,7 +18,7 @@ use crate::{
diff::{DiffObjConfig, MipsAbi, MipsInstrCategory, display::InstructionPart},
obj::{
InstructionArg, InstructionArgValue, InstructionRef, Relocation, RelocationFlags,
ResolvedInstructionRef, ResolvedRelocation, ScannedInstruction, SymbolFlag, SymbolFlagSet,
ResolvedInstructionRef, ResolvedRelocation, SymbolFlag, SymbolFlagSet,
},
};
@@ -189,16 +188,16 @@ impl ArchMips {
}
impl Arch for ArchMips {
fn scan_instructions(
fn scan_instructions_internal(
&self,
address: u64,
code: &[u8],
_section_index: usize,
_relocations: &[Relocation],
diff_config: &DiffObjConfig,
) -> Result<Vec<ScannedInstruction>> {
) -> Result<Vec<InstructionRef>> {
let instruction_flags = self.instruction_flags(diff_config);
let mut ops = Vec::<ScannedInstruction>::with_capacity(code.len() / 4);
let mut ops = Vec::<InstructionRef>::with_capacity(code.len() / 4);
let mut cur_addr = address as u32;
for chunk in code.chunks_exact(4) {
let code = self.endianness.read_u32_bytes(chunk.try_into()?);
@@ -206,10 +205,7 @@ impl Arch for ArchMips {
rabbitizer::Instruction::new(code, Vram::new(cur_addr), instruction_flags);
let opcode = instruction.opcode() as u16;
let branch_dest = instruction.get_branch_vram_generic().map(|v| v.inner() as u64);
ops.push(ScannedInstruction {
ins_ref: InstructionRef { address: cur_addr as u64, size: 4, opcode },
branch_dest,
});
ops.push(InstructionRef { address: cur_addr as u64, size: 4, opcode, branch_dest });
cur_addr += 4;
}
Ok(ops)
@@ -225,16 +221,7 @@ impl Arch for ArchMips {
let display_flags = self.instruction_display_flags(diff_config);
let opcode = instruction.opcode();
cb(InstructionPart::opcode(opcode.name(), opcode as u16))?;
let start_address = resolved.symbol.address;
let function_range = start_address..start_address + resolved.symbol.size;
push_args(
&instruction,
resolved.relocation,
function_range,
resolved.section_index,
&display_flags,
cb,
)?;
push_args(&instruction, resolved.relocation, &display_flags, cb)?;
Ok(())
}
@@ -338,8 +325,6 @@ impl Arch for ArchMips {
fn push_args(
instruction: &rabbitizer::Instruction,
relocation: Option<ResolvedRelocation>,
function_range: Range<u64>,
section_index: usize,
display_flags: &rabbitizer::InstructionDisplayFlags,
mut arg_cb: impl FnMut(InstructionPart) -> Result<()>,
) -> Result<()> {
@@ -362,23 +347,7 @@ fn push_args(
}
ValuedOperand::core_label(..) | ValuedOperand::core_branch_target_label(..) => {
if let Some(resolved) = relocation {
// If the relocation target is within the current function, we can
// convert it into a relative branch target. Note that we check
// target_address > start_address instead of >= so that recursive
// tail calls are not considered branch targets.
let target_address =
resolved.symbol.address.checked_add_signed(resolved.relocation.addend);
if resolved.symbol.section == Some(section_index)
&& target_address.is_some_and(|addr| {
addr > function_range.start && addr < function_range.end
})
{
// TODO move this logic up a level
let target_address = target_address.unwrap();
arg_cb(InstructionPart::branch_dest(target_address))?;
} else {
push_reloc(resolved.relocation, &mut arg_cb)?;
}
push_reloc(resolved.relocation, &mut arg_cb)?;
} else if let Some(branch_dest) = instruction
.get_branch_offset_generic()
.map(|o| (instruction.vram() + o).inner() as u64)
objdiff-core/src/arch/mod.rs
+103 -21
View File
@@ -11,8 +11,8 @@ use crate::{
display::{ContextItem, HoverItem, InstructionPart},
},
obj::{
InstructionArg, Object, ParsedInstruction, Relocation, RelocationFlags,
ResolvedInstructionRef, ScannedInstruction, Section, Symbol, SymbolFlagSet, SymbolKind,
InstructionArg, InstructionRef, Object, ParsedInstruction, Relocation, RelocationFlags,
ResolvedInstructionRef, ResolvedSymbol, Section, Symbol, SymbolFlagSet, SymbolKind,
},
util::ReallySigned,
};
@@ -182,46 +182,108 @@ impl DataType {
}
}
pub trait Arch: Send + Sync + Debug {
// Finishes arch-specific initialization that must be done after sections have been combined.
fn post_init(&mut self, _sections: &[Section], _symbols: &[Symbol]) {}
impl dyn Arch {
/// Generate a list of instructions references (offset, size, opcode) from the given code.
///
/// The opcode IDs are used to generate the initial diff. Implementations should do as little
/// parsing as possible here: just enough to identify the base instruction opcode, size, and
/// possible branch destination (for visual representation). As needed, instructions are parsed
/// via `process_instruction` to compare their arguments.
fn scan_instructions(
/// See [`scan_instructions_internal`] for more details.
pub fn scan_instructions(
&self,
address: u64,
code: &[u8],
section_index: usize,
relocations: &[Relocation],
resolved: ResolvedSymbol,
diff_config: &DiffObjConfig,
) -> Result<Vec<ScannedInstruction>>;
) -> Result<Vec<InstructionRef>> {
let mut result = self.scan_instructions_internal(
resolved.symbol.address,
resolved.data,
resolved.section_index,
&resolved.section.relocations,
diff_config,
)?;
let function_start = resolved.symbol.address;
let function_end = function_start + resolved.symbol.size;
// Remove any branch destinations that are outside the function range
for ins in result.iter_mut() {
if let Some(branch_dest) = ins.branch_dest {
if branch_dest < function_start || branch_dest >= function_end {
ins.branch_dest = None;
}
}
}
// Resolve relocation targets within the same function to branch destinations
let mut ins_iter = result.iter_mut().peekable();
'outer: for reloc in resolved
.section
.relocations
.iter()
.skip_while(|r| r.address < function_start)
.take_while(|r| r.address < function_end)
{
let ins = loop {
let Some(ins) = ins_iter.peek_mut() else {
break 'outer;
};
if reloc.address < ins.address {
continue 'outer;
}
let ins = ins_iter.next().unwrap();
if reloc.address >= ins.address && reloc.address < ins.address + ins.size as u64 {
break ins;
}
};
// Clear existing branch destination for instructions with relocations
ins.branch_dest = None;
let Some(target) = resolved.obj.symbols.get(reloc.target_symbol) else {
continue;
};
if target.section != Some(resolved.section_index) {
continue;
}
let Some(target_address) = target.address.checked_add_signed(reloc.addend) else {
continue;
};
// If the target address is within the function range, set it as a branch destination
if target_address >= function_start && target_address < function_end {
ins.branch_dest = Some(target_address);
}
}
Ok(result)
}
/// Parse an instruction to gather its mnemonic and arguments for more detailed comparison.
///
/// This is called only when we need to compare the arguments of an instruction.
fn process_instruction(
pub fn process_instruction(
&self,
resolved: ResolvedInstructionRef,
diff_config: &DiffObjConfig,
) -> Result<ParsedInstruction> {
let mut mnemonic = None;
let mut args = Vec::with_capacity(8);
let mut relocation_emitted = false;
self.display_instruction(resolved, diff_config, &mut |part| {
match part {
InstructionPart::Opcode(m, _) => mnemonic = Some(Cow::Owned(m.into_owned())),
InstructionPart::Arg(arg) => args.push(arg.into_static()),
InstructionPart::Arg(arg) => {
if arg == InstructionArg::Reloc {
relocation_emitted = true;
// If the relocation was resolved to a branch destination, emit that instead.
if let Some(dest) = resolved.ins_ref.branch_dest {
args.push(InstructionArg::BranchDest(dest));
return Ok(());
}
}
args.push(arg.into_static());
}
_ => {}
}
Ok(())
})?;
// If the instruction has a relocation, but we didn't format it in the display, add it to
// the end of the arguments list.
if resolved.relocation.is_some() && !args.contains(&InstructionArg::Reloc) {
if resolved.relocation.is_some() && !relocation_emitted {
args.push(InstructionArg::Reloc);
}
Ok(ParsedInstruction {
@@ -230,6 +292,26 @@ pub trait Arch: Send + Sync + Debug {
args,
})
}
}
pub trait Arch: Send + Sync + Debug {
/// Finishes arch-specific initialization that must be done after sections have been combined.
fn post_init(&mut self, _sections: &[Section], _symbols: &[Symbol]) {}
/// Generate a list of instructions references (offset, size, opcode) from the given code.
///
/// The opcode IDs are used to generate the initial diff. Implementations should do as little
/// parsing as possible here: just enough to identify the base instruction opcode, size, and
/// possible branch destination (for visual representation). As needed, instructions are parsed
/// via `process_instruction` to compare their arguments.
fn scan_instructions_internal(
&self,
address: u64,
code: &[u8],
section_index: usize,
relocations: &[Relocation],
diff_config: &DiffObjConfig,
) -> Result<Vec<InstructionRef>>;
/// Format an instruction for display.
///
@@ -332,14 +414,14 @@ impl ArchDummy {
}
impl Arch for ArchDummy {
fn scan_instructions(
fn scan_instructions_internal(
&self,
_address: u64,
_code: &[u8],
_section_index: usize,
_relocations: &[Relocation],
_diff_config: &DiffObjConfig,
) -> Result<Vec<ScannedInstruction>> {
) -> Result<Vec<InstructionRef>> {
Ok(Vec::new())
}
objdiff-core/src/arch/ppc.rs
+8 -10
View File
@@ -19,7 +19,7 @@ use crate::{
},
obj::{
InstructionRef, Object, Relocation, RelocationFlags, ResolvedInstructionRef,
ResolvedRelocation, ScannedInstruction, Symbol, SymbolFlag, SymbolFlagSet,
ResolvedRelocation, Symbol, SymbolFlag, SymbolFlagSet,
},
};
@@ -82,24 +82,22 @@ impl ArchPpc {
}
impl Arch for ArchPpc {
fn scan_instructions(
fn scan_instructions_internal(
&self,
address: u64,
code: &[u8],
_section_index: usize,
_relocations: &[Relocation],
_diff_config: &DiffObjConfig,
) -> Result<Vec<ScannedInstruction>> {
) -> Result<Vec<InstructionRef>> {
ensure!(code.len() & 3 == 0, "Code length must be a multiple of 4");
let ins_count = code.len() / 4;
let mut insts = Vec::<ScannedInstruction>::with_capacity(ins_count);
let mut insts = Vec::<InstructionRef>::with_capacity(ins_count);
for (cur_addr, ins) in ppc750cl::InsIter::new(code, address as u32) {
insts.push(ScannedInstruction {
ins_ref: InstructionRef {
address: cur_addr as u64,
size: 4,
opcode: u8::from(ins.op) as u16,
},
insts.push(InstructionRef {
address: cur_addr as u64,
size: 4,
opcode: u8::from(ins.op) as u16,
branch_dest: ins.branch_dest(cur_addr).map(u64::from),
});
}
objdiff-core/src/arch/superh/mod.rs
+57 -21
View File
@@ -6,9 +6,7 @@ use object::elf;
use crate::{
arch::{Arch, superh::disasm::sh2_disasm},
diff::{DiffObjConfig, display::InstructionPart},
obj::{
InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef, ScannedInstruction,
},
obj::{InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef},
};
pub mod disasm;
@@ -26,15 +24,15 @@ struct DataInfo {
}
impl Arch for ArchSuperH {
fn scan_instructions(
fn scan_instructions_internal(
&self,
address: u64,
code: &[u8],
_section_index: usize,
_relocations: &[Relocation],
_diff_config: &DiffObjConfig,
) -> Result<Vec<ScannedInstruction>> {
let mut ops = Vec::<ScannedInstruction>::with_capacity(code.len() / 2);
) -> Result<Vec<InstructionRef>> {
let mut ops = Vec::<InstructionRef>::with_capacity(code.len() / 2);
let mut offset = address;
for chunk in code.chunks_exact(2) {
@@ -55,9 +53,7 @@ impl Arch for ArchSuperH {
Some(InstructionPart::Opcode(_, val)) => *val,
_ => 0,
};
let ins_ref: InstructionRef =
InstructionRef { address: offset, size: 2, opcode: opcode_enum };
ops.push(ScannedInstruction { ins_ref, branch_dest });
ops.push(InstructionRef { address: offset, size: 2, opcode: opcode_enum, branch_dest });
offset += 2;
}
@@ -256,7 +252,7 @@ mod test {
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: 0x1000, size: 2, opcode },
ins_ref: InstructionRef { address: 0x1000, size: 2, opcode, branch_dest: None },
code: &code,
..Default::default()
},
@@ -334,7 +330,7 @@ mod test {
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: 0x1000, size: 2, opcode },
ins_ref: InstructionRef { address: 0x1000, size: 2, opcode, branch_dest: None },
code: &code,
..Default::default()
},
@@ -417,7 +413,7 @@ mod test {
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: 0x1000, size: 2, opcode },
ins_ref: InstructionRef { address: 0x1000, size: 2, opcode, branch_dest: None },
code: &code,
..Default::default()
},
@@ -454,7 +450,7 @@ mod test {
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: 0x1000, size: 2, opcode },
ins_ref: InstructionRef { address: 0x1000, size: 2, opcode, branch_dest: None },
code: &code,
..Default::default()
},
@@ -503,7 +499,12 @@ mod test {
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: addr as u64, size: 2, opcode },
ins_ref: InstructionRef {
address: addr as u64,
size: 2,
opcode,
branch_dest: None,
},
code: &code,
..Default::default()
},
@@ -539,7 +540,12 @@ mod test {
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: addr as u64, size: 2, opcode },
ins_ref: InstructionRef {
address: addr as u64,
size: 2,
opcode,
branch_dest: None,
},
code: &code,
..Default::default()
},
@@ -578,7 +584,12 @@ mod test {
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: addr as u64, size: 2, opcode },
ins_ref: InstructionRef {
address: addr as u64,
size: 2,
opcode,
branch_dest: None,
},
code: &code,
..Default::default()
},
@@ -617,7 +628,12 @@ mod test {
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: addr as u64, size: 2, opcode },
ins_ref: InstructionRef {
address: addr as u64,
size: 2,
opcode,
branch_dest: None,
},
code: &code,
..Default::default()
},
@@ -649,7 +665,12 @@ mod test {
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: addr as u64, size: 2, opcode },
ins_ref: InstructionRef {
address: addr as u64,
size: 2,
opcode,
branch_dest: None,
},
code: &code,
..Default::default()
},
@@ -678,7 +699,12 @@ mod test {
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: addr as u64, size: 2, opcode },
ins_ref: InstructionRef {
address: addr as u64,
size: 2,
opcode,
branch_dest: None,
},
code: &code,
..Default::default()
},
@@ -710,7 +736,12 @@ mod test {
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: addr as u64, size: 2, opcode },
ins_ref: InstructionRef {
address: addr as u64,
size: 2,
opcode,
branch_dest: None,
},
code: &opcode.to_be_bytes(),
symbol: &Symbol {
address: 0x0606F378, // func base address
@@ -755,7 +786,12 @@ mod test {
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: addr as u64, size: 2, opcode },
ins_ref: InstructionRef {
address: addr as u64,
size: 2,
opcode,
branch_dest: None,
},
code: &opcode.to_be_bytes(),
symbol: &Symbol {
address: 0x0606F378, // func base address
objdiff-core/src/arch/x86.rs
+26 -31
View File
@@ -11,9 +11,7 @@ use object::{Endian as _, Object as _, ObjectSection as _, pe};
use crate::{
arch::Arch,
diff::{DiffObjConfig, X86Formatter, display::InstructionPart},
obj::{
InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef, ScannedInstruction,
},
obj::{InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef},
};
#[derive(Debug)]
@@ -86,14 +84,14 @@ impl ArchX86 {
const DATA_OPCODE: u16 = u16::MAX - 1;
impl Arch for ArchX86 {
fn scan_instructions(
fn scan_instructions_internal(
&self,
address: u64,
code: &[u8],
_section_index: usize,
relocations: &[Relocation],
_diff_config: &DiffObjConfig,
) -> Result<Vec<ScannedInstruction>> {
) -> Result<Vec<InstructionRef>> {
let mut out = Vec::with_capacity(code.len() / 2);
let mut decoder = self.decoder(code, address);
let mut instruction = Instruction::default();
@@ -112,12 +110,10 @@ impl Arch for ArchX86 {
})?;
if decoder.set_position(decoder.position() + size).is_ok() {
decoder.set_ip(address + size as u64);
out.push(ScannedInstruction {
ins_ref: InstructionRef {
address,
size: size as u8,
opcode: DATA_OPCODE,
},
out.push(InstructionRef {
address,
size: size as u8,
opcode: DATA_OPCODE,
branch_dest: None,
});
reloc_iter.next();
@@ -134,12 +130,10 @@ impl Arch for ArchX86 {
OpKind::NearBranch64 => Some(instruction.near_branch64()),
_ => None,
};
out.push(ScannedInstruction {
ins_ref: InstructionRef {
address,
size: instruction.len() as u8,
opcode: instruction.mnemonic() as u16,
},
out.push(InstructionRef {
address,
size: instruction.len() as u8,
opcode: instruction.mnemonic() as u16,
branch_dest,
});
}
@@ -457,15 +451,16 @@ mod test {
0xc7, 0x85, 0x68, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x8b, 0x04, 0x85, 0x00,
0x00, 0x00, 0x00,
];
let scanned = arch.scan_instructions(0, &code, 0, &[], &DiffObjConfig::default()).unwrap();
let scanned =
arch.scan_instructions_internal(0, &code, 0, &[], &DiffObjConfig::default()).unwrap();
assert_eq!(scanned.len(), 2);
assert_eq!(scanned[0].ins_ref.address, 0);
assert_eq!(scanned[0].ins_ref.size, 10);
assert_eq!(scanned[0].ins_ref.opcode, iced_x86::Mnemonic::Mov as u16);
assert_eq!(scanned[0].address, 0);
assert_eq!(scanned[0].size, 10);
assert_eq!(scanned[0].opcode, iced_x86::Mnemonic::Mov as u16);
assert_eq!(scanned[0].branch_dest, None);
assert_eq!(scanned[1].ins_ref.address, 10);
assert_eq!(scanned[1].ins_ref.size, 7);
assert_eq!(scanned[1].ins_ref.opcode, iced_x86::Mnemonic::Mov as u16);
assert_eq!(scanned[1].address, 10);
assert_eq!(scanned[1].size, 7);
assert_eq!(scanned[1].opcode, iced_x86::Mnemonic::Mov as u16);
assert_eq!(scanned[1].branch_dest, None);
}
@@ -477,7 +472,7 @@ mod test {
let mut parts = Vec::new();
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: 0x1234, size: 10, opcode },
ins_ref: InstructionRef { address: 0x1234, size: 10, opcode, branch_dest: None },
code: &code,
..Default::default()
},
@@ -513,7 +508,7 @@ mod test {
let mut parts = Vec::new();
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: 0x1234, size: 10, opcode },
ins_ref: InstructionRef { address: 0x1234, size: 10, opcode, branch_dest: None },
code: &code,
relocation: Some(ResolvedRelocation {
relocation: &Relocation {
@@ -558,7 +553,7 @@ mod test {
let mut parts = Vec::new();
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: 0x1234, size: 7, opcode },
ins_ref: InstructionRef { address: 0x1234, size: 7, opcode, branch_dest: None },
code: &code,
relocation: Some(ResolvedRelocation {
relocation: &Relocation {
@@ -601,7 +596,7 @@ mod test {
let mut parts = Vec::new();
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: 0x1234, size: 5, opcode },
ins_ref: InstructionRef { address: 0x1234, size: 5, opcode, branch_dest: None },
code: &code,
relocation: Some(ResolvedRelocation {
relocation: &Relocation {
@@ -632,7 +627,7 @@ mod test {
let mut parts = Vec::new();
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: 0x1234, size: 6, opcode },
ins_ref: InstructionRef { address: 0x1234, size: 6, opcode, branch_dest: None },
code: &code,
relocation: Some(ResolvedRelocation {
relocation: &Relocation {
@@ -671,7 +666,7 @@ mod test {
let mut parts = Vec::new();
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: 0x1234, size: 7, opcode },
ins_ref: InstructionRef { address: 0x1234, size: 7, opcode, branch_dest: None },
code: &code,
relocation: Some(ResolvedRelocation {
relocation: &Relocation {
@@ -710,7 +705,7 @@ mod test {
let mut parts = Vec::new();
arch.display_instruction(
ResolvedInstructionRef {
ins_ref: InstructionRef { address: 0x1234, size: 5, opcode },
ins_ref: InstructionRef { address: 0x1234, size: 5, opcode, branch_dest: None },
code: &code,
relocation: Some(ResolvedRelocation {
relocation: &Relocation {
objdiff-core/src/diff/code.rs
+43 -52
View File
@@ -14,15 +14,15 @@ use super::{
};
use crate::obj::{
InstructionArg, InstructionArgValue, InstructionRef, Object, ResolvedInstructionRef,
ResolvedRelocation, ScannedInstruction, SymbolFlag, SymbolKind,
ResolvedRelocation, ResolvedSymbol, SymbolFlag, SymbolKind,
};
pub fn no_diff_code(
obj: &Object,
symbol_idx: usize,
symbol_index: usize,
diff_config: &DiffObjConfig,
) -> Result<SymbolDiff> {
let symbol = &obj.symbols[symbol_idx];
let symbol = &obj.symbols[symbol_index];
let section_index = symbol.section.ok_or_else(|| anyhow!("Missing section for symbol"))?;
let section = &obj.sections[section_index];
let data = section.data_range(symbol.address, symbol.size as usize).ok_or_else(|| {
@@ -33,18 +33,14 @@ pub fn no_diff_code(
)
})?;
let ops = obj.arch.scan_instructions(
symbol.address,
data,
section_index,
&section.relocations,
ResolvedSymbol { obj, symbol_index, symbol, section_index, section, data },
diff_config,
)?;
let mut instruction_rows = Vec::<InstructionDiffRow>::new();
for i in &ops {
instruction_rows
.push(InstructionDiffRow { ins_ref: Some(i.ins_ref), ..Default::default() });
instruction_rows.push(InstructionDiffRow { ins_ref: Some(*i), ..Default::default() });
}
resolve_branches(obj, section_index, &ops, &mut instruction_rows);
resolve_branches(&ops, &mut instruction_rows);
Ok(SymbolDiff { target_symbol: None, match_percent: None, diff_score: None, instruction_rows })
}
@@ -92,22 +88,30 @@ pub fn diff_code(
let left_section_idx = left_symbol.section.unwrap();
let right_section_idx = right_symbol.section.unwrap();
let left_ops = left_obj.arch.scan_instructions(
left_symbol.address,
left_data,
left_section_idx,
&left_section.relocations,
ResolvedSymbol {
obj: left_obj,
symbol_index: left_symbol_idx,
symbol: left_symbol,
section_index: left_section_idx,
section: left_section,
data: left_data,
},
diff_config,
)?;
let right_ops = right_obj.arch.scan_instructions(
right_symbol.address,
right_data,
right_section_idx,
&right_section.relocations,
ResolvedSymbol {
obj: right_obj,
symbol_index: right_symbol_idx,
symbol: right_symbol,
section_index: right_section_idx,
section: right_section,
data: right_data,
},
diff_config,
)?;
let (mut left_rows, mut right_rows) = diff_instructions(&left_ops, &right_ops)?;
resolve_branches(left_obj, left_section_idx, &left_ops, &mut left_rows);
resolve_branches(right_obj, right_section_idx, &right_ops, &mut right_rows);
resolve_branches(&left_ops, &mut left_rows);
resolve_branches(&right_ops, &mut right_rows);
let mut diff_state = InstructionDiffState::default();
for (left_row, right_row) in left_rows.iter_mut().zip(right_rows.iter_mut()) {
@@ -154,21 +158,21 @@ pub fn diff_code(
}
fn diff_instructions(
left_insts: &[ScannedInstruction],
right_insts: &[ScannedInstruction],
left_insts: &[InstructionRef],
right_insts: &[InstructionRef],
) -> Result<(Vec<InstructionDiffRow>, Vec<InstructionDiffRow>)> {
let left_ops = left_insts.iter().map(|i| i.ins_ref.opcode).collect::<Vec<_>>();
let right_ops = right_insts.iter().map(|i| i.ins_ref.opcode).collect::<Vec<_>>();
let left_ops = left_insts.iter().map(|i| i.opcode).collect::<Vec<_>>();
let right_ops = right_insts.iter().map(|i| i.opcode).collect::<Vec<_>>();
let ops = similar::capture_diff_slices(similar::Algorithm::Patience, &left_ops, &right_ops);
if ops.is_empty() {
ensure!(left_insts.len() == right_insts.len());
let left_diff = left_insts
.iter()
.map(|i| InstructionDiffRow { ins_ref: Some(i.ins_ref), ..Default::default() })
.map(|i| InstructionDiffRow { ins_ref: Some(*i), ..Default::default() })
.collect();
let right_diff = right_insts
.iter()
.map(|i| InstructionDiffRow { ins_ref: Some(i.ins_ref), ..Default::default() })
.map(|i| InstructionDiffRow { ins_ref: Some(*i), ..Default::default() })
.collect();
return Ok((left_diff, right_diff));
}
@@ -187,14 +191,17 @@ fn diff_instructions(
for op in ops {
let (_tag, left_range, right_range) = op.as_tag_tuple();
let len = left_range.len().max(right_range.len());
left_diff.extend(left_range.clone().map(|i| InstructionDiffRow {
ins_ref: Some(left_insts[i].ins_ref),
..Default::default()
}));
right_diff.extend(right_range.clone().map(|i| InstructionDiffRow {
ins_ref: Some(right_insts[i].ins_ref),
..Default::default()
}));
left_diff.extend(
left_range
.clone()
.map(|i| InstructionDiffRow { ins_ref: Some(left_insts[i]), ..Default::default() }),
);
right_diff.extend(
right_range.clone().map(|i| InstructionDiffRow {
ins_ref: Some(right_insts[i]),
..Default::default()
}),
);
if left_range.len() < len {
left_diff.extend((left_range.len()..len).map(|_| InstructionDiffRow::default()));
}
@@ -215,13 +222,7 @@ fn arg_to_string(arg: &InstructionArg, reloc: Option<ResolvedRelocation>) -> Str
}
}
fn resolve_branches(
obj: &Object,
section_index: usize,
ops: &[ScannedInstruction],
rows: &mut [InstructionDiffRow],
) {
let section = &obj.sections[section_index];
fn resolve_branches(ops: &[InstructionRef], rows: &mut [InstructionDiffRow]) {
let mut branch_idx = 0u32;
// Map addresses to indices
let mut addr_map = BTreeMap::<u64, u32>::new();
@@ -235,17 +236,7 @@ fn resolve_branches(
for ((i, ins_diff), ins) in
rows.iter_mut().enumerate().filter(|(_, row)| row.ins_ref.is_some()).zip(ops)
{
let branch_dest = if let Some(resolved) = section.relocation_at(obj, ins.ins_ref) {
if resolved.symbol.section == Some(section_index) {
// If the relocation target is in the same section, use it as the branch destination
resolved.symbol.address.checked_add_signed(resolved.relocation.addend)
} else {
None
}
} else {
ins.branch_dest
};
if let Some(ins_idx) = branch_dest.and_then(|a| addr_map.get(&a).copied()) {
if let Some(ins_idx) = ins.branch_dest.and_then(|a| addr_map.get(&a).copied()) {
match branches.entry(ins_idx) {
btree_map::Entry::Vacant(e) => {
ins_diff.branch_to = Some(InstructionBranchTo { ins_idx, branch_idx });
objdiff-core/src/diff/display.rs
+9 -5
View File
@@ -205,16 +205,18 @@ pub fn display_row(
InstructionPart::Arg(arg) => {
let diff_index = ins_row.arg_diff.get(arg_idx).copied().unwrap_or_default();
arg_idx += 1;
match arg {
InstructionArg::Value(value) => cb(DiffTextSegment {
if arg == InstructionArg::Reloc {
displayed_relocation = true;
}
match (arg, resolved.ins_ref.branch_dest) {
(InstructionArg::Value(value), _) => cb(DiffTextSegment {
text: DiffText::Argument(value),
color: diff_index
.get()
.map_or(base_color, |i| DiffTextColor::Rotating(i as u8)),
pad_to: 0,
}),
InstructionArg::Reloc => {
displayed_relocation = true;
(InstructionArg::Reloc, None) => {
let resolved = resolved.relocation.unwrap();
let color = diff_index
.get()
@@ -233,7 +235,9 @@ pub fn display_row(
}
Ok(())
}
InstructionArg::BranchDest(dest) => {
(InstructionArg::BranchDest(dest), _) |
// If the relocation was resolved to a branch destination, emit that instead.
(InstructionArg::Reloc, Some(dest)) => {
if let Some(addr) = dest.checked_sub(resolved.symbol.address) {
cb(DiffTextSegment {
text: DiffText::BranchDest(addr),
objdiff-core/src/obj/mod.rs
+10 -5
View File
@@ -214,11 +214,6 @@ pub struct InstructionRef {
pub address: u64,
pub size: u8,
pub opcode: u16,
}
#[derive(Copy, Clone, Debug)]
pub struct ScannedInstruction {
pub ins_ref: InstructionRef,
pub branch_dest: Option<u64>,
}
@@ -335,6 +330,16 @@ pub struct ResolvedRelocation<'a> {
pub symbol: &'a Symbol,
}
#[derive(Debug, Copy, Clone)]
pub struct ResolvedSymbol<'obj> {
pub obj: &'obj Object,
pub symbol_index: usize,
pub symbol: &'obj Symbol,
pub section_index: usize,
pub section: &'obj Section,
pub data: &'obj [u8],
}
#[derive(Debug, Copy, Clone)]
pub struct ResolvedInstructionRef<'obj> {
pub ins_ref: InstructionRef,
objdiff-core/tests/snapshots/arch_arm__combine_text_sections.snap
+3 -1
View File
@@ -1,6 +1,5 @@
---
source: objdiff-core/tests/arch_arm.rs
assertion_line: 43
expression: diff.instruction_rows
---
[
@@ -10,6 +9,7 @@ expression: diff.instruction_rows
address: 76,
size: 4,
opcode: 32799,
branch_dest: None,
},
),
kind: None,
@@ -23,6 +23,7 @@ expression: diff.instruction_rows
address: 80,
size: 4,
opcode: 32779,
branch_dest: None,
},
),
kind: None,
@@ -36,6 +37,7 @@ expression: diff.instruction_rows
address: 84,
size: 4,
opcode: 65535,
branch_dest: None,
},
),
kind: None,
objdiff-core/tests/snapshots/arch_arm__read_arm-2.snap
+172
View File
File diff suppressed because it is too large Load Diff
objdiff-core/tests/snapshots/arch_arm__read_arm-3.snap
+1 -2
View File
@@ -1,6 +1,5 @@
---
source: objdiff-core/tests/arch_arm.rs
assertion_line: 16
expression: output
---
[(Address(0), Normal, 5), (Spacing(4), Normal, 0), (Opcode("stmdb", 32895), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Argument(Opaque("!")), Normal, 0), (Basic(", "), Normal, 0), (Basic("{"), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("lr")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
@@ -28,7 +27,7 @@ expression: output
[(Address(88), Normal, 5), (Spacing(4), Normal, 0), (Opcode("ldrb", 32800), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(224)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
[(Address(92), Normal, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 32786), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
[(Address(96), Normal, 5), (Spacing(4), Normal, 0), (Opcode("bne", 32773), Normal, 10), (BranchDest(108), Normal, 0), (Basic(" ~>"), Rotating(7), 0), (Eol, Normal, 0)]
[(Address(100), Normal, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32774), Normal, 10), (Symbol(Symbol { name: "_ZN13LinkStateItem15GetEquipBombchuEv", demangled_name: Some("LinkStateItem::GetEquipBombchu()"), address: 472, size: 16, kind: Function, section: Some(0), flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-8), Bright, 0), (Basic(" ~>"), Rotating(8), 0), (Eol, Normal, 0)]
[(Address(100), Normal, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32774), Normal, 10), (BranchDest(424), Normal, 0), (Basic(" ~>"), Rotating(8), 0), (Eol, Normal, 0)]
[(Address(104), Normal, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32774), Normal, 10), (Symbol(Symbol { name: "_ZN12EquipBombchu19func_ov014_0213ec64Ev", demangled_name: Some("EquipBombchu::func_ov014_0213ec64()"), address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Addend(-8), Bright, 0), (Eol, Normal, 0)]
[(Address(108), Normal, 5), (Basic(" ~> "), Rotating(7), 0), (Opcode("ldr", 32799), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(308)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(424), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
[(Address(112), Normal, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32799), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
objdiff-core/tests/snapshots/arch_arm__read_thumb-2.snap
+128
View File
File diff suppressed because it is too large Load Diff
objdiff-core/tests/snapshots/arch_mips__read_mips-2.snap
+54
View File
@@ -9,6 +9,7 @@ expression: diff.instruction_rows
address: 0,
size: 4,
opcode: 12,
branch_dest: None,
},
),
kind: None,
@@ -22,6 +23,7 @@ expression: diff.instruction_rows
address: 4,
size: 4,
opcode: 44,
branch_dest: None,
},
),
kind: None,
@@ -35,6 +37,7 @@ expression: diff.instruction_rows
address: 8,
size: 4,
opcode: 44,
branch_dest: None,
},
),
kind: None,
@@ -48,6 +51,7 @@ expression: diff.instruction_rows
address: 12,
size: 4,
opcode: 44,
branch_dest: None,
},
),
kind: None,
@@ -61,6 +65,7 @@ expression: diff.instruction_rows
address: 16,
size: 4,
opcode: 44,
branch_dest: None,
},
),
kind: None,
@@ -74,6 +79,7 @@ expression: diff.instruction_rows
address: 20,
size: 4,
opcode: 2,
branch_dest: None,
},
),
kind: None,
@@ -87,6 +93,7 @@ expression: diff.instruction_rows
address: 24,
size: 4,
opcode: 113,
branch_dest: None,
},
),
kind: None,
@@ -100,6 +107,7 @@ expression: diff.instruction_rows
address: 28,
size: 4,
opcode: 26,
branch_dest: None,
},
),
kind: None,
@@ -113,6 +121,7 @@ expression: diff.instruction_rows
address: 32,
size: 4,
opcode: 20,
branch_dest: None,
},
),
kind: None,
@@ -126,6 +135,7 @@ expression: diff.instruction_rows
address: 36,
size: 4,
opcode: 97,
branch_dest: None,
},
),
kind: None,
@@ -139,6 +149,7 @@ expression: diff.instruction_rows
address: 40,
size: 4,
opcode: 2,
branch_dest: None,
},
),
kind: None,
@@ -152,6 +163,7 @@ expression: diff.instruction_rows
address: 44,
size: 4,
opcode: 12,
branch_dest: None,
},
),
kind: None,
@@ -165,6 +177,7 @@ expression: diff.instruction_rows
address: 48,
size: 4,
opcode: 20,
branch_dest: None,
},
),
kind: None,
@@ -178,6 +191,7 @@ expression: diff.instruction_rows
address: 52,
size: 4,
opcode: 26,
branch_dest: None,
},
),
kind: None,
@@ -191,6 +205,7 @@ expression: diff.instruction_rows
address: 56,
size: 4,
opcode: 2,
branch_dest: None,
},
),
kind: None,
@@ -204,6 +219,7 @@ expression: diff.instruction_rows
address: 60,
size: 4,
opcode: 12,
branch_dest: None,
},
),
kind: None,
@@ -217,6 +233,7 @@ expression: diff.instruction_rows
address: 64,
size: 4,
opcode: 26,
branch_dest: None,
},
),
kind: None,
@@ -230,6 +247,7 @@ expression: diff.instruction_rows
address: 68,
size: 4,
opcode: 97,
branch_dest: None,
},
),
kind: None,
@@ -243,6 +261,7 @@ expression: diff.instruction_rows
address: 72,
size: 4,
opcode: 2,
branch_dest: None,
},
),
kind: None,
@@ -256,6 +275,7 @@ expression: diff.instruction_rows
address: 76,
size: 4,
opcode: 97,
branch_dest: None,
},
),
kind: None,
@@ -269,6 +289,7 @@ expression: diff.instruction_rows
address: 80,
size: 4,
opcode: 2,
branch_dest: None,
},
),
kind: None,
@@ -289,6 +310,7 @@ expression: diff.instruction_rows
address: 84,
size: 4,
opcode: 97,
branch_dest: None,
},
),
kind: None,
@@ -302,6 +324,9 @@ expression: diff.instruction_rows
address: 88,
size: 4,
opcode: 56,
branch_dest: Some(
80,
),
},
),
kind: None,
@@ -320,6 +345,7 @@ expression: diff.instruction_rows
address: 92,
size: 4,
opcode: 113,
branch_dest: None,
},
),
kind: None,
@@ -333,6 +359,7 @@ expression: diff.instruction_rows
address: 96,
size: 4,
opcode: 2,
branch_dest: None,
},
),
kind: None,
@@ -346,6 +373,7 @@ expression: diff.instruction_rows
address: 100,
size: 4,
opcode: 20,
branch_dest: None,
},
),
kind: None,
@@ -359,6 +387,7 @@ expression: diff.instruction_rows
address: 104,
size: 4,
opcode: 2,
branch_dest: None,
},
),
kind: None,
@@ -372,6 +401,7 @@ expression: diff.instruction_rows
address: 108,
size: 4,
opcode: 12,
branch_dest: None,
},
),
kind: None,
@@ -385,6 +415,7 @@ expression: diff.instruction_rows
address: 112,
size: 4,
opcode: 2,
branch_dest: None,
},
),
kind: None,
@@ -398,6 +429,7 @@ expression: diff.instruction_rows
address: 116,
size: 4,
opcode: 16,
branch_dest: None,
},
),
kind: None,
@@ -411,6 +443,7 @@ expression: diff.instruction_rows
address: 120,
size: 4,
opcode: 20,
branch_dest: None,
},
),
kind: None,
@@ -424,6 +457,7 @@ expression: diff.instruction_rows
address: 124,
size: 4,
opcode: 12,
branch_dest: None,
},
),
kind: None,
@@ -437,6 +471,7 @@ expression: diff.instruction_rows
address: 128,
size: 4,
opcode: 2,
branch_dest: None,
},
),
kind: None,
@@ -459,6 +494,7 @@ expression: diff.instruction_rows
address: 132,
size: 4,
opcode: 12,
branch_dest: None,
},
),
kind: None,
@@ -472,6 +508,7 @@ expression: diff.instruction_rows
address: 136,
size: 4,
opcode: 2,
branch_dest: None,
},
),
kind: None,
@@ -485,6 +522,7 @@ expression: diff.instruction_rows
address: 140,
size: 4,
opcode: 113,
branch_dest: None,
},
),
kind: None,
@@ -498,6 +536,9 @@ expression: diff.instruction_rows
address: 144,
size: 4,
opcode: 55,
branch_dest: Some(
128,
),
},
),
kind: None,
@@ -516,6 +557,7 @@ expression: diff.instruction_rows
address: 148,
size: 4,
opcode: 90,
branch_dest: None,
},
),
kind: None,
@@ -529,6 +571,9 @@ expression: diff.instruction_rows
address: 152,
size: 4,
opcode: 3,
branch_dest: Some(
128,
),
},
),
kind: None,
@@ -547,6 +592,7 @@ expression: diff.instruction_rows
address: 156,
size: 4,
opcode: 113,
branch_dest: None,
},
),
kind: None,
@@ -560,6 +606,7 @@ expression: diff.instruction_rows
address: 160,
size: 4,
opcode: 2,
branch_dest: None,
},
),
kind: None,
@@ -573,6 +620,7 @@ expression: diff.instruction_rows
address: 164,
size: 4,
opcode: 60,
branch_dest: None,
},
),
kind: None,
@@ -586,6 +634,7 @@ expression: diff.instruction_rows
address: 168,
size: 4,
opcode: 77,
branch_dest: None,
},
),
kind: None,
@@ -599,6 +648,7 @@ expression: diff.instruction_rows
address: 172,
size: 4,
opcode: 113,
branch_dest: None,
},
),
kind: None,
@@ -612,6 +662,9 @@ expression: diff.instruction_rows
address: 176,
size: 4,
opcode: 54,
branch_dest: Some(
128,
),
},
),
kind: None,
@@ -630,6 +683,7 @@ expression: diff.instruction_rows
address: 180,
size: 4,
opcode: 113,
branch_dest: None,
},
),
kind: None,
objdiff-core/tests/snapshots/arch_ppc__diff_ppc-2.snap
+422
View File
File diff suppressed because it is too large Load Diff
objdiff-core/tests/snapshots/arch_ppc__read_ppc-2.snap
+90
View File
@@ -9,6 +9,7 @@ expression: diff.instruction_rows
address: 0,
size: 4,
opcode: 60,
branch_dest: None,
},
),
kind: None,
@@ -22,6 +23,7 @@ expression: diff.instruction_rows
address: 4,
size: 4,
opcode: 38,
branch_dest: None,
},
),
kind: None,
@@ -35,6 +37,9 @@ expression: diff.instruction_rows
address: 8,
size: 4,
opcode: 43,
branch_dest: Some(
20,
),
},
),
kind: None,
@@ -53,6 +58,7 @@ expression: diff.instruction_rows
address: 12,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -66,6 +72,9 @@ expression: diff.instruction_rows
address: 16,
size: 4,
opcode: 45,
branch_dest: Some(
32,
),
},
),
kind: None,
@@ -84,6 +93,7 @@ expression: diff.instruction_rows
address: 20,
size: 4,
opcode: 42,
branch_dest: None,
},
),
kind: None,
@@ -104,6 +114,7 @@ expression: diff.instruction_rows
address: 24,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -117,6 +128,7 @@ expression: diff.instruction_rows
address: 28,
size: 4,
opcode: 94,
branch_dest: None,
},
),
kind: None,
@@ -130,6 +142,7 @@ expression: diff.instruction_rows
address: 32,
size: 4,
opcode: 60,
branch_dest: None,
},
),
kind: None,
@@ -150,6 +163,7 @@ expression: diff.instruction_rows
address: 36,
size: 4,
opcode: 166,
branch_dest: None,
},
),
kind: None,
@@ -163,6 +177,7 @@ expression: diff.instruction_rows
address: 40,
size: 4,
opcode: 38,
branch_dest: None,
},
),
kind: None,
@@ -176,6 +191,9 @@ expression: diff.instruction_rows
address: 44,
size: 4,
opcode: 43,
branch_dest: Some(
56,
),
},
),
kind: None,
@@ -194,6 +212,7 @@ expression: diff.instruction_rows
address: 48,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -207,6 +226,9 @@ expression: diff.instruction_rows
address: 52,
size: 4,
opcode: 45,
branch_dest: Some(
68,
),
},
),
kind: None,
@@ -225,6 +247,7 @@ expression: diff.instruction_rows
address: 56,
size: 4,
opcode: 42,
branch_dest: None,
},
),
kind: None,
@@ -245,6 +268,7 @@ expression: diff.instruction_rows
address: 60,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -258,6 +282,7 @@ expression: diff.instruction_rows
address: 64,
size: 4,
opcode: 94,
branch_dest: None,
},
),
kind: None,
@@ -271,6 +296,7 @@ expression: diff.instruction_rows
address: 68,
size: 4,
opcode: 60,
branch_dest: None,
},
),
kind: None,
@@ -291,6 +317,7 @@ expression: diff.instruction_rows
address: 72,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -304,6 +331,7 @@ expression: diff.instruction_rows
address: 76,
size: 4,
opcode: 38,
branch_dest: None,
},
),
kind: None,
@@ -317,6 +345,7 @@ expression: diff.instruction_rows
address: 80,
size: 4,
opcode: 166,
branch_dest: None,
},
),
kind: None,
@@ -330,6 +359,9 @@ expression: diff.instruction_rows
address: 84,
size: 4,
opcode: 43,
branch_dest: Some(
96,
),
},
),
kind: None,
@@ -348,6 +380,7 @@ expression: diff.instruction_rows
address: 88,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -361,6 +394,9 @@ expression: diff.instruction_rows
address: 92,
size: 4,
opcode: 45,
branch_dest: Some(
108,
),
},
),
kind: None,
@@ -379,6 +415,7 @@ expression: diff.instruction_rows
address: 96,
size: 4,
opcode: 42,
branch_dest: None,
},
),
kind: None,
@@ -399,6 +436,7 @@ expression: diff.instruction_rows
address: 100,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -412,6 +450,7 @@ expression: diff.instruction_rows
address: 104,
size: 4,
opcode: 94,
branch_dest: None,
},
),
kind: None,
@@ -425,6 +464,7 @@ expression: diff.instruction_rows
address: 108,
size: 4,
opcode: 60,
branch_dest: None,
},
),
kind: None,
@@ -445,6 +485,7 @@ expression: diff.instruction_rows
address: 112,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -458,6 +499,7 @@ expression: diff.instruction_rows
address: 116,
size: 4,
opcode: 38,
branch_dest: None,
},
),
kind: None,
@@ -471,6 +513,7 @@ expression: diff.instruction_rows
address: 120,
size: 4,
opcode: 166,
branch_dest: None,
},
),
kind: None,
@@ -484,6 +527,9 @@ expression: diff.instruction_rows
address: 124,
size: 4,
opcode: 43,
branch_dest: Some(
136,
),
},
),
kind: None,
@@ -502,6 +548,7 @@ expression: diff.instruction_rows
address: 128,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -515,6 +562,9 @@ expression: diff.instruction_rows
address: 132,
size: 4,
opcode: 45,
branch_dest: Some(
148,
),
},
),
kind: None,
@@ -533,6 +583,7 @@ expression: diff.instruction_rows
address: 136,
size: 4,
opcode: 42,
branch_dest: None,
},
),
kind: None,
@@ -553,6 +604,7 @@ expression: diff.instruction_rows
address: 140,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -566,6 +618,7 @@ expression: diff.instruction_rows
address: 144,
size: 4,
opcode: 94,
branch_dest: None,
},
),
kind: None,
@@ -579,6 +632,7 @@ expression: diff.instruction_rows
address: 148,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -599,6 +653,7 @@ expression: diff.instruction_rows
address: 152,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -612,6 +667,7 @@ expression: diff.instruction_rows
address: 156,
size: 4,
opcode: 166,
branch_dest: None,
},
),
kind: None,
@@ -625,6 +681,7 @@ expression: diff.instruction_rows
address: 160,
size: 4,
opcode: 42,
branch_dest: None,
},
),
kind: None,
@@ -638,6 +695,7 @@ expression: diff.instruction_rows
address: 164,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -651,6 +709,7 @@ expression: diff.instruction_rows
address: 168,
size: 4,
opcode: 166,
branch_dest: None,
},
),
kind: None,
@@ -664,6 +723,7 @@ expression: diff.instruction_rows
address: 172,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -677,6 +737,7 @@ expression: diff.instruction_rows
address: 176,
size: 4,
opcode: 162,
branch_dest: None,
},
),
kind: None,
@@ -690,6 +751,7 @@ expression: diff.instruction_rows
address: 180,
size: 4,
opcode: 94,
branch_dest: None,
},
),
kind: None,
@@ -703,6 +765,7 @@ expression: diff.instruction_rows
address: 184,
size: 4,
opcode: 66,
branch_dest: None,
},
),
kind: None,
@@ -716,6 +779,9 @@ expression: diff.instruction_rows
address: 188,
size: 4,
opcode: 43,
branch_dest: Some(
196,
),
},
),
kind: None,
@@ -734,6 +800,7 @@ expression: diff.instruction_rows
address: 192,
size: 4,
opcode: 166,
branch_dest: None,
},
),
kind: None,
@@ -747,6 +814,7 @@ expression: diff.instruction_rows
address: 196,
size: 4,
opcode: 163,
branch_dest: None,
},
),
kind: None,
@@ -767,6 +835,7 @@ expression: diff.instruction_rows
address: 200,
size: 4,
opcode: 94,
branch_dest: None,
},
),
kind: None,
@@ -780,6 +849,7 @@ expression: diff.instruction_rows
address: 204,
size: 4,
opcode: 66,
branch_dest: None,
},
),
kind: None,
@@ -793,6 +863,9 @@ expression: diff.instruction_rows
address: 208,
size: 4,
opcode: 43,
branch_dest: Some(
216,
),
},
),
kind: None,
@@ -811,6 +884,7 @@ expression: diff.instruction_rows
address: 212,
size: 4,
opcode: 166,
branch_dest: None,
},
),
kind: None,
@@ -824,6 +898,7 @@ expression: diff.instruction_rows
address: 216,
size: 4,
opcode: 163,
branch_dest: None,
},
),
kind: None,
@@ -844,6 +919,7 @@ expression: diff.instruction_rows
address: 220,
size: 4,
opcode: 94,
branch_dest: None,
},
),
kind: None,
@@ -857,6 +933,7 @@ expression: diff.instruction_rows
address: 224,
size: 4,
opcode: 66,
branch_dest: None,
},
),
kind: None,
@@ -870,6 +947,9 @@ expression: diff.instruction_rows
address: 228,
size: 4,
opcode: 43,
branch_dest: Some(
236,
),
},
),
kind: None,
@@ -888,6 +968,7 @@ expression: diff.instruction_rows
address: 232,
size: 4,
opcode: 166,
branch_dest: None,
},
),
kind: None,
@@ -901,6 +982,7 @@ expression: diff.instruction_rows
address: 236,
size: 4,
opcode: 163,
branch_dest: None,
},
),
kind: None,
@@ -921,6 +1003,7 @@ expression: diff.instruction_rows
address: 240,
size: 4,
opcode: 94,
branch_dest: None,
},
),
kind: None,
@@ -934,6 +1017,7 @@ expression: diff.instruction_rows
address: 244,
size: 4,
opcode: 66,
branch_dest: None,
},
),
kind: None,
@@ -947,6 +1031,9 @@ expression: diff.instruction_rows
address: 248,
size: 4,
opcode: 43,
branch_dest: Some(
256,
),
},
),
kind: None,
@@ -965,6 +1052,7 @@ expression: diff.instruction_rows
address: 252,
size: 4,
opcode: 166,
branch_dest: None,
},
),
kind: None,
@@ -978,6 +1066,7 @@ expression: diff.instruction_rows
address: 256,
size: 4,
opcode: 41,
branch_dest: None,
},
),
kind: None,
@@ -998,6 +1087,7 @@ expression: diff.instruction_rows
address: 260,
size: 4,
opcode: 47,
branch_dest: None,
},
),
kind: None,
objdiff-core/tests/snapshots/arch_x86__read_x86-2.snap
+7
View File
@@ -9,6 +9,7 @@ expression: diff.instruction_rows
address: 0,
size: 1,
opcode: 640,
branch_dest: None,
},
),
kind: None,
@@ -22,6 +23,7 @@ expression: diff.instruction_rows
address: 1,
size: 2,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -35,6 +37,7 @@ expression: diff.instruction_rows
address: 3,
size: 5,
opcode: 640,
branch_dest: None,
},
),
kind: None,
@@ -48,6 +51,7 @@ expression: diff.instruction_rows
address: 8,
size: 5,
opcode: 59,
branch_dest: None,
},
),
kind: None,
@@ -61,6 +65,7 @@ expression: diff.instruction_rows
address: 13,
size: 3,
opcode: 7,
branch_dest: None,
},
),
kind: None,
@@ -74,6 +79,7 @@ expression: diff.instruction_rows
address: 16,
size: 1,
opcode: 590,
branch_dest: None,
},
),
kind: None,
@@ -87,6 +93,7 @@ expression: diff.instruction_rows
address: 17,
size: 1,
opcode: 662,
branch_dest: None,
},
),
kind: None,
objdiff-core/tests/snapshots/arch_x86__read_x86_64-2.snap
+21
View File
@@ -9,6 +9,7 @@ expression: diff.instruction_rows
address: 0,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -22,6 +23,7 @@ expression: diff.instruction_rows
address: 5,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -35,6 +37,7 @@ expression: diff.instruction_rows
address: 10,
size: 1,
opcode: 640,
branch_dest: None,
},
),
kind: None,
@@ -48,6 +51,7 @@ expression: diff.instruction_rows
address: 11,
size: 4,
opcode: 740,
branch_dest: None,
},
),
kind: None,
@@ -61,6 +65,7 @@ expression: diff.instruction_rows
address: 15,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -74,6 +79,7 @@ expression: diff.instruction_rows
address: 20,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -87,6 +93,7 @@ expression: diff.instruction_rows
address: 25,
size: 4,
opcode: 448,
branch_dest: None,
},
),
kind: None,
@@ -100,6 +107,7 @@ expression: diff.instruction_rows
address: 29,
size: 4,
opcode: 460,
branch_dest: None,
},
),
kind: None,
@@ -113,6 +121,7 @@ expression: diff.instruction_rows
address: 33,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -126,6 +135,7 @@ expression: diff.instruction_rows
address: 38,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -139,6 +149,7 @@ expression: diff.instruction_rows
address: 43,
size: 5,
opcode: 448,
branch_dest: None,
},
),
kind: None,
@@ -152,6 +163,7 @@ expression: diff.instruction_rows
address: 48,
size: 5,
opcode: 460,
branch_dest: None,
},
),
kind: None,
@@ -165,6 +177,7 @@ expression: diff.instruction_rows
address: 53,
size: 4,
opcode: 11,
branch_dest: None,
},
),
kind: None,
@@ -178,6 +191,7 @@ expression: diff.instruction_rows
address: 57,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -191,6 +205,7 @@ expression: diff.instruction_rows
address: 62,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -204,6 +219,7 @@ expression: diff.instruction_rows
address: 67,
size: 5,
opcode: 448,
branch_dest: None,
},
),
kind: None,
@@ -217,6 +233,7 @@ expression: diff.instruction_rows
address: 72,
size: 5,
opcode: 460,
branch_dest: None,
},
),
kind: None,
@@ -230,6 +247,7 @@ expression: diff.instruction_rows
address: 77,
size: 4,
opcode: 11,
branch_dest: None,
},
),
kind: None,
@@ -243,6 +261,7 @@ expression: diff.instruction_rows
address: 81,
size: 4,
opcode: 7,
branch_dest: None,
},
),
kind: None,
@@ -256,6 +275,7 @@ expression: diff.instruction_rows
address: 85,
size: 1,
opcode: 590,
branch_dest: None,
},
),
kind: None,
@@ -269,6 +289,7 @@ expression: diff.instruction_rows
address: 86,
size: 1,
opcode: 662,
branch_dest: None,
},
),
kind: None,
objdiff-core/tests/snapshots/arch_x86__read_x86_jumptable-2.snap
+53
View File
@@ -9,6 +9,7 @@ expression: diff.instruction_rows
address: 0,
size: 4,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -22,6 +23,7 @@ expression: diff.instruction_rows
address: 4,
size: 1,
opcode: 137,
branch_dest: None,
},
),
kind: None,
@@ -35,6 +37,7 @@ expression: diff.instruction_rows
address: 5,
size: 3,
opcode: 93,
branch_dest: None,
},
),
kind: None,
@@ -48,6 +51,9 @@ expression: diff.instruction_rows
address: 8,
size: 2,
opcode: 297,
branch_dest: Some(
58,
),
},
),
kind: None,
@@ -66,6 +72,9 @@ expression: diff.instruction_rows
address: 10,
size: 7,
opcode: 308,
branch_dest: Some(
60,
),
},
),
kind: None,
@@ -84,6 +93,7 @@ expression: diff.instruction_rows
address: 17,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -104,6 +114,7 @@ expression: diff.instruction_rows
address: 22,
size: 1,
opcode: 662,
branch_dest: None,
},
),
kind: None,
@@ -117,6 +128,7 @@ expression: diff.instruction_rows
address: 23,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -137,6 +149,7 @@ expression: diff.instruction_rows
address: 28,
size: 1,
opcode: 662,
branch_dest: None,
},
),
kind: None,
@@ -150,6 +163,7 @@ expression: diff.instruction_rows
address: 29,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -170,6 +184,7 @@ expression: diff.instruction_rows
address: 34,
size: 1,
opcode: 662,
branch_dest: None,
},
),
kind: None,
@@ -183,6 +198,7 @@ expression: diff.instruction_rows
address: 35,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -203,6 +219,7 @@ expression: diff.instruction_rows
address: 40,
size: 1,
opcode: 662,
branch_dest: None,
},
),
kind: None,
@@ -216,6 +233,7 @@ expression: diff.instruction_rows
address: 41,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -236,6 +254,7 @@ expression: diff.instruction_rows
address: 46,
size: 1,
opcode: 662,
branch_dest: None,
},
),
kind: None,
@@ -249,6 +268,7 @@ expression: diff.instruction_rows
address: 47,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -269,6 +289,7 @@ expression: diff.instruction_rows
address: 52,
size: 1,
opcode: 662,
branch_dest: None,
},
),
kind: None,
@@ -282,6 +303,7 @@ expression: diff.instruction_rows
address: 53,
size: 5,
opcode: 414,
branch_dest: None,
},
),
kind: None,
@@ -302,6 +324,7 @@ expression: diff.instruction_rows
address: 58,
size: 1,
opcode: 662,
branch_dest: None,
},
),
kind: None,
@@ -322,6 +345,7 @@ expression: diff.instruction_rows
address: 59,
size: 1,
opcode: 465,
branch_dest: None,
},
),
kind: None,
@@ -335,6 +359,9 @@ expression: diff.instruction_rows
address: 60,
size: 4,
opcode: 65534,
branch_dest: Some(
17,
),
},
),
kind: None,
@@ -360,6 +387,9 @@ expression: diff.instruction_rows
address: 64,
size: 4,
opcode: 65534,
branch_dest: Some(
23,
),
},
),
kind: None,
@@ -378,6 +408,9 @@ expression: diff.instruction_rows
address: 68,
size: 4,
opcode: 65534,
branch_dest: Some(
29,
),
},
),
kind: None,
@@ -396,6 +429,9 @@ expression: diff.instruction_rows
address: 72,
size: 4,
opcode: 65534,
branch_dest: Some(
35,
),
},
),
kind: None,
@@ -414,6 +450,9 @@ expression: diff.instruction_rows
address: 76,
size: 4,
opcode: 65534,
branch_dest: Some(
41,
),
},
),
kind: None,
@@ -432,6 +471,9 @@ expression: diff.instruction_rows
address: 80,
size: 4,
opcode: 65534,
branch_dest: Some(
47,
),
},
),
kind: None,
@@ -450,6 +492,9 @@ expression: diff.instruction_rows
address: 84,
size: 4,
opcode: 65534,
branch_dest: Some(
53,
),
},
),
kind: None,
@@ -468,6 +513,7 @@ expression: diff.instruction_rows
address: 88,
size: 1,
opcode: 465,
branch_dest: None,
},
),
kind: None,
@@ -481,6 +527,7 @@ expression: diff.instruction_rows
address: 89,
size: 1,
opcode: 465,
branch_dest: None,
},
),
kind: None,
@@ -494,6 +541,7 @@ expression: diff.instruction_rows
address: 90,
size: 1,
opcode: 465,
branch_dest: None,
},
),
kind: None,
@@ -507,6 +555,7 @@ expression: diff.instruction_rows
address: 91,
size: 1,
opcode: 465,
branch_dest: None,
},
),
kind: None,
@@ -520,6 +569,7 @@ expression: diff.instruction_rows
address: 92,
size: 1,
opcode: 465,
branch_dest: None,
},
),
kind: None,
@@ -533,6 +583,7 @@ expression: diff.instruction_rows
address: 93,
size: 1,
opcode: 465,
branch_dest: None,
},
),
kind: None,
@@ -546,6 +597,7 @@ expression: diff.instruction_rows
address: 94,
size: 1,
opcode: 465,
branch_dest: None,
},
),
kind: None,
@@ -559,6 +611,7 @@ expression: diff.instruction_rows
address: 95,
size: 1,
opcode: 465,
branch_dest: None,
},
),
kind: None,

Some files were not shown because too many files have changed in this diff Show More