Commit Graph

6467 Commits

Author SHA1 Message Date
Fangrui Song 0a301a194e [utils] Add utils/update_cc_test_checks.py
A utility to update LLVM IR in C/C++ FileCheck test files.

Example RUN lines in .c/.cc test files:

// RUN: %clang -S -Os -DXX %s -o - | FileCheck %s
// RUN: %clangxx -S -Os %s -o - | FileCheck -check-prefix=IR %s

Usage:

% utils/update_cc_test_checks.py --llvm-bin=release/bin test/a.cc
% utils/update_cc_test_checks.py --c-index-test=release/bin/c-index-test --clang=release/bin/clang /tmp/c/a.cc

    // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
    // RUN: %clang -emit-llvm -S -Os -DXX %s -o - | FileCheck -check-prefix=AA %s
    // RUN: %clangxx -emit-llvm -S -Os %s -o - | FileCheck -check-prefix=BB %s
    using T =
    #ifdef XX
        int __attribute__((vector_size(16)))
    #else
        short __attribute__((vector_size(16)))
    #endif
        ;

    // AA-LABEL: _Z3fooDv4_i:
    // AA:       entry:
    // AA-NEXT:    %add = shl <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
    // AA-NEXT:    ret <4 x i32> %add
    //
    // BB-LABEL: _Z3fooDv8_s:
    // BB:       entry:
    // BB-NEXT:    %add = shl <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
    // BB-NEXT:    ret <8 x i16> %add
    T foo(T a) {
      return a + a;
    }

Differential Revision: https://reviews.llvm.org/D42712

llvm-svn: 326591
2018-03-02 17:37:04 +00:00
Lei Huang 9db7bd5cab Losen time contraint to accommodate system loads
llvm-svn: 326359
2018-02-28 20:05:24 +00:00
Justin Bogner 35a9d1b17f update_mir_test_checks: Use the regexes from UpdateTestChecks.common
Some of the update_*_test_checks regexes have been moved into a
library, so we might as well use them in update_mir_test_checks.
Also includes minor bugfixes to the regexes that are there so we
don't regress update_mir_test_checks

llvm-svn: 326288
2018-02-28 00:56:24 +00:00
Justin Bogner d3eccb54b1 update_mir_test_checks: Drop support for vreg block checks
Since vregs are printed in the instruction stream now, checking the
vreg block is always redundant. Remove the temporary feature that
allowed us to do that.

This reverts r316134

llvm-svn: 326284
2018-02-28 00:44:46 +00:00
Ilya Biryukov d9d9bf8d13 Revert r326092: [gtest] Add PrintTo overload for StringRef.
It seems to break the following buildbot:
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/24729

Will resubmit after investigating and fixing it.

llvm-svn: 326096
2018-02-26 15:54:59 +00:00
Ilya Biryukov ab6554fefb [gtest] Add PrintTo overload for StringRef.
Summary:
It was printed using code for generic containers before, resulting in
unreadable output.

Reviewers: sammccall, labath

Reviewed By: sammccall, labath

Subscribers: labath, zturner, llvm-commits

Differential Revision: https://reviews.llvm.org/D43330

llvm-svn: 326092
2018-02-26 15:19:26 +00:00
Benjamin Kramer b941ababce Shrink various scheduling tables by using narrower types.
16 bits ought to be enough for everyone. This shrinks clang by ~1MB.

llvm-svn: 325941
2018-02-23 19:32:56 +00:00
Geoff Berry f8bf2ec0a8 [MachineOperand][Target] MachineOperand::isRenamable semantics changes
Summary:
Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers.  This is set to 0 by
default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
fields of all opcodes to be set to 1, causing
MachineOperand::isRenamable to always return false.

Set the AllowRegisterRenaming flag to 1 for all in-tree targets that
have lit tests that were effected by enabling COPY forwarding in
MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC,
RISCV, Sparc, SystemZ and X86).

Add some more comments describing the semantics of the
MachineOperand::isRenamable function and how it is set and maintained.

Change isRenamable to check the operand's opcode
hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of
relying on it being consistently reflected in the IsRenamable bit
setting.

Clear the IsRenamable bit when changing an operand's register value.

Remove target code that was clearing the IsRenamable bit when changing
registers/opcodes now that this is done conservatively by default.

Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in
one place covering all opcodes that have constant pipe read limit
restrictions.

Reviewers: qcolombet, MatzeB

Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D43042

llvm-svn: 325931
2018-02-23 18:25:08 +00:00
Pavel Labath 3b17b84b9c Resubmit r325107 (case folding DJB hash)
The issue was that the has function was generating different results depending
on the signedness of char on the host platform. This commit fixes the issue by
explicitly using an unsigned char type to prevent sign extension and
adds some extra tests.

The original commit message was:

This patch implements a variant of the DJB hash function which folds the
input according to the algorithm in the Dwarf 5 specification (Section
6.1.1.4.5), which in turn references the Unicode Standard (Section 5.18,
"Case Mappings").

To achieve this, I have added a llvm::sys::unicode::foldCharSimple
function, which performs this mapping. The implementation of this
function was generated from the CaseMatching.txt file from the Unicode
spec using a python script (which is also included in this patch). The
script tries to optimize the function by coalescing adjecant mappings
with the same shift and stride (terms I made up). Theoretically, it
could be made a bit smarter and merge adjecant blocks that were
interrupted by only one or two characters with exceptional mapping, but
this would save only a couple of branches, while it would greatly
complicate the implementation, so I deemed it was not worth it.

Since we assume that the vast majority of the input characters will be
US-ASCII, the folding hash function has a fast-path for handling these,
and only whips out the full decode+fold+encode logic if we encounter a
character outside of this range. It might be possible to implement the
folding directly on utf8 sequences, but this would also bring a lot of
complexity for the few cases where we will actually need to process
non-ascii characters.

Reviewers: JDevlieghere, aprantl, probinson, dblaikie

Subscribers: mgorny, hintonda, echristo, clayborg, vleschuk, llvm-commits

Differential Revision: https://reviews.llvm.org/D42740

llvm-svn: 325732
2018-02-21 22:36:31 +00:00
Mikhail Maltsev 581a7f0bef [vim] Recognize more FileCheck comments
Summary:
Currently vim syntax highlighting recognizes 'CHECK:' as a special
comment, but not CHECK-DAG, CHECK-NOT and other CHECKs. This patch
adds rules for these comments.

Reviewers: chandlerc, compnerd, rogfer01

Reviewed By: rogfer01

Subscribers: rogfer01, llvm-commits

Differential Revision: https://reviews.llvm.org/D43289

llvm-svn: 325599
2018-02-20 17:27:44 +00:00
Simon Pilgrim e4d40f9b7d Fix signed/unsigned comparison warning in AsmGenMatcher generated code. NFCI.
llvm-svn: 325428
2018-02-17 12:29:47 +00:00
Rui Ueyama 7c9ad29304 Remove "--full-shutdown" and instead use an environment variable LLD_IN_TEST.
We are running lld tests with "--full-shutdown" option because we don't
want to call _exit() in lld if it is running tests. Regular shutdown
is needed for leak sanitizer.

This patch changes the way how we tell lld that it is running tests.
Now "--full-shutdown" is removed, and LLD_IN_TEST environment variable
is used instead.

This patch enables full shutdown on all ports, e.g. ELF, COFF and wasm.
Previously, we enabled it only for ELF.

Differential Revision: https://reviews.llvm.org/D43410

llvm-svn: 325413
2018-02-16 23:41:48 +00:00
Aditya Nandakumar b63e763847 [GISel]: Make GlobalISelEmitter rule prioritization compatible with selectionDAG
This patch changes GlobalISelEmitter to rank patterns similar to how the
DAG does it (ie it computes a score for a pattern and adds the added
complexity to it).
This is so that the decision tree for GISelSelector remains compatible
with that of SelectionDAG.

https://reviews.llvm.org/D43270

llvm-svn: 325401
2018-02-16 22:37:15 +00:00
Rui Ueyama 14ee1140c1 Make sure we invoke ld64.lld and ld-wasm in the build directory.
llvm-svn: 325397
2018-02-16 22:19:38 +00:00
Rafael Auler de9ad4ba84 [X86][3DNOW] Teach decoder about AMD 3DNow! instrs
Summary:
This patch makes the decoder understand old AMD 3DNow!
instructions that have never been properly supported in the X86
disassembler, despite being supported in other subsystems. Hopefully
this should make the X86 decoder more complete with respect to binaries
containing legacy code.

Reviewers: craig.topper

Reviewed By: craig.topper

Subscribers: llvm-commits, maksfb, bruno

Differential Revision: https://reviews.llvm.org/D43311

llvm-svn: 325295
2018-02-15 21:20:31 +00:00
Pavel Labath 918f60056a Revert r325107 (case folding DJB hash) and subsequent build fix
The "knownValuesUnicode" test in the patch fails on ppc64 and arm64
bots. Reverting while I investigate.

llvm-svn: 325115
2018-02-14 11:06:39 +00:00
Pavel Labath f1440978a1 Implement a case-folding version of DJB hash
Summary:
This patch implements a variant of the DJB hash function which folds the
input according to the algorithm in the Dwarf 5 specification (Section
6.1.1.4.5), which in turn references the Unicode Standard (Section 5.18,
"Case Mappings").

To achieve this, I have added a llvm::sys::unicode::foldCharSimple
function, which performs this mapping. The implementation of this
function was generated from the CaseMatching.txt file from the Unicode
spec using a python script (which is also included in this patch). The
script tries to optimize the function by coalescing adjecant mappings
with the same shift and stride (terms I made up). Theoretically, it
could be made a bit smarter and merge adjecant blocks that were
interrupted by only one or two characters with exceptional mapping, but
this would save only a couple of branches, while it would greatly
complicate the implementation, so I deemed it was not worth it.

Since we assume that the vast majority of the input characters will be
US-ASCII, the folding hash function has a fast-path for handling these,
and only whips out the full decode+fold+encode logic if we encounter a
character outside of this range. It might be possible to implement the
folding directly on utf8 sequences, but this would also bring a lot of
complexity for the few cases where we will actually need to process
non-ascii characters.

Reviewers: JDevlieghere, aprantl, probinson, dblaikie

Subscribers: mgorny, hintonda, echristo, clayborg, vleschuk, llvm-commits

Differential Revision: https://reviews.llvm.org/D42740

llvm-svn: 325107
2018-02-14 10:05:09 +00:00
Craig Topper df99baa4df [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass.
Bits 7:4 control the scale part of the operation. If the scale is 0 the behavior is equivalent to VROUND.

Fixes PR36246

llvm-svn: 324985
2018-02-13 04:19:26 +00:00
Sam McCall 2d8242d60d [gtest] Support raw_ostream printing functions more comprehensively.
Summary:
These are functions like operator<<(raw_ostream&, Foo).

Previously these were only supported for messages. In the assertion
  EXPECT_EQ(A, B) << C;
the local modifications would explicitly try to use raw_ostream printing for C.
However A and B would look for a std::ostream printing function, and often fall
back to gtest's default "168 byte object <00 01 FE 42 ...>".

This patch pulls out the raw_ostream support into a new header under `custom/`.

I changed the mechanism: instead of a convertible stream, we wrap the printed
value in a proxy object to allow it to be sent to a std::ostream.
I think the new way is clearer.

I also changed the policy: we prefer raw_ostream printers over std::ostream
ones. This is because the fallback printers are defined using std::ostream,
while all the raw_ostream printers should be "good".

Reviewers: ilya-biryukov, chandlerc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D43091

llvm-svn: 324876
2018-02-12 10:20:09 +00:00
Fangrui Song 4f0f426d1f [utils] Refactor utils/update_{,llc_}test_checks.py to share more code
Summary:
This revision refactors 1. parser 2. CHECK line adder of utils/update_{,llc_}test_checks.py
so that thir functionality can be re-used by other utility scripts (e.g.  D42712)

Reviewers: asb, craig.topper, RKSimon, echristo

Subscribers: llvm-commits, spatel

Differential Revision: https://reviews.llvm.org/D42805

llvm-svn: 324803
2018-02-10 05:01:33 +00:00
Clement Courbet 873aa11dd9 [TargetSchedule] Fix r324582.
Increment was using the wrong NumUnits (the one from the ProcResGroup
and not the subunit).

llvm-svn: 324727
2018-02-09 10:28:46 +00:00
Victor Leschuk 33b9fa7caa [lit] Pass CLANG env var to testing configuration
Allow CLANG environment variable be copied into the testing configuration
and proper support testing with a custom path to the clang executable.

Signed-off-by: Vladimir Vereschaka <vvereschaka@accesssoftek.com>
llvm-svn: 324706
2018-02-09 05:28:38 +00:00
David Blaikie e6503d87da Fix missing field initializer warning in TableGen SubtargetEmitter
llvm-svn: 324643
2018-02-08 19:57:05 +00:00
Clement Courbet 39911e2ee6 [TargetSchedule] Expose sub-units of a ProcResGroup in MCProcResourceDesc.
Summary:
Right now using a ProcResource automatically counts as usage of all
super ProcResGroups. All this is done during codegen, so there is no
way for schedulers to get this information at runtime.

This adds the information of which individual ProcRes units are
contained in a ProcResGroup in MCProcResourceDesc.

Reviewers: gchatelet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D43023

llvm-svn: 324582
2018-02-08 08:46:48 +00:00
Clement Courbet eb4f5d2890 [CodeGenSchedule][NFC] Always emit ProcResourceUnits.
Summary:
Right now only the ProcResourceUnits that are directly referenced by
instructions are emitted. This change emits all of them, so that
analysis passes can use the information.
This has no functional impact. It typically adds a few entries (e.g. 4
for X86/haswell) to the generated ProcRes table.

Reviewers: gchatelet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42903

llvm-svn: 324228
2018-02-05 12:23:51 +00:00