Commit Graph

284057 Commits

Author SHA1 Message Date
Vedant Kumar 1a8456da17 Fix more spelling mistakes in comments of LLVM Analysis passes
Patch by Reshabh Sharma!

Differential Revision: https://reviews.llvm.org/D43939

llvm-svn: 326601
2018-03-02 18:57:02 +00:00
Sanjay Patel 46b083ef4a [PatternMatch, InstSimplify] fix m_NaN to work with vector constants and use it
This is NFC for the moment (and independent of any potential NaN semantic
controversy). Besides making the code in InstSimplify easier to read, the
motivation is to eventually allow undef elements in vector constants to
match too. A proposal to add the base logic for that is in D43792.

llvm-svn: 326600
2018-03-02 18:36:08 +00:00
Krzysztof Parzyszek f608812bde [Hexagon] Handle VACOPY in isel lowering
llvm-svn: 326599
2018-03-02 18:35:57 +00:00
Ilya Biryukov ddedde9aa0 [clangd] Use higher timoout values in TUSchedulerTest::Debounce
Should unbreak windows buildbots.

llvm-svn: 326598
2018-03-02 18:23:41 +00:00
Simon Pilgrim 8cbc1d232b [X86][BTVER2] Fix throughput of YMM bitwise instructions
These instructions are double-pumped, split into 2 128-bit ops and then passing through either FPU pipe.

Found while testing llvm-mca (D43951)

llvm-svn: 326597
2018-03-02 18:20:35 +00:00
Craig Topper 6b1419b547 [X86] Reject xmm16-31 in inline asm constraints when AVX512 is disabled
Fixes PR36532

Differential Revision: https://reviews.llvm.org/D43960

llvm-svn: 326596
2018-03-02 18:19:40 +00:00
Craig Topper 18799f4c07 [InstCombine] Allow fptrunc (fpext X)) to be reduced to a single fpext/ftrunc
If we are only truncating bits from the extend we should be able to just use a smaller extend.

If we are truncating more than the extend we should be able to just use a fptrunc since the presense of the fpextend shouldn't affect rounding.

Differential Revision: https://reviews.llvm.org/D43970

llvm-svn: 326595
2018-03-02 18:16:51 +00:00
Alexey Bataev 20cf67c233 [OPENMP] Scan all redeclarations looking for declare simd attribute.
Patch fixes the problem with the functions marked as `declare simd`. If
the canonical declaration does not have associated `declare simd`
construct, we may not generate required code even if other
redeclarations are marked as `declare simd`.

llvm-svn: 326594
2018-03-02 18:07:00 +00:00
Derek Schuff 57feeed307 [X86][x32] Save callee-save register used as base pointer for x32 ABI
For the x32 ABI, since the base pointer register (EBX) is a callee save register
it should be saved before use.

This fixes https://bugs.llvm.org/show_bug.cgi?id=36011

Differential Revision: https://reviews.llvm.org/D42358

Patch by Pratik Bhatu

llvm-svn: 326593
2018-03-02 17:46:39 +00:00
Benjamin Kramer 4925653555 [ARM] Fold variable into assert.
Avoids unused variable warnings in Release mode.

llvm-svn: 326592
2018-03-02 17:39:20 +00:00
Fangrui Song 0a301a194e [utils] Add utils/update_cc_test_checks.py
A utility to update LLVM IR in C/C++ FileCheck test files.

Example RUN lines in .c/.cc test files:

// RUN: %clang -S -Os -DXX %s -o - | FileCheck %s
// RUN: %clangxx -S -Os %s -o - | FileCheck -check-prefix=IR %s

Usage:

% utils/update_cc_test_checks.py --llvm-bin=release/bin test/a.cc
% utils/update_cc_test_checks.py --c-index-test=release/bin/c-index-test --clang=release/bin/clang /tmp/c/a.cc

    // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
    // RUN: %clang -emit-llvm -S -Os -DXX %s -o - | FileCheck -check-prefix=AA %s
    // RUN: %clangxx -emit-llvm -S -Os %s -o - | FileCheck -check-prefix=BB %s
    using T =
    #ifdef XX
        int __attribute__((vector_size(16)))
    #else
        short __attribute__((vector_size(16)))
    #endif
        ;

    // AA-LABEL: _Z3fooDv4_i:
    // AA:       entry:
    // AA-NEXT:    %add = shl <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
    // AA-NEXT:    ret <4 x i32> %add
    //
    // BB-LABEL: _Z3fooDv8_s:
    // BB:       entry:
    // BB-NEXT:    %add = shl <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
    // BB-NEXT:    ret <8 x i16> %add
    T foo(T a) {
      return a + a;
    }

Differential Revision: https://reviews.llvm.org/D42712

llvm-svn: 326591
2018-03-02 17:37:04 +00:00
Alexey Bataev 852525de25 [OPENMP] Treat local variables in CUDA mode as thread local.
In CUDA mode all local variables are actually thread
local|threadprivate, not private, and, thus, they cannot be shared
between threads|lanes.

llvm-svn: 326590
2018-03-02 17:17:12 +00:00
Matt Arsenault b9699c009d AMDGPU/GlobalISel: InstrMapping for G_ZEXT
llvm-svn: 326589
2018-03-02 16:55:37 +00:00
Matt Arsenault 1c1aab99ae AMDGPU/GlobalISel: InstrMapping for G_TRUNC
llvm-svn: 326588
2018-03-02 16:55:33 +00:00
Matt Arsenault ef8db767d7 AMDGPU/GlobalISel: Define InstrMappings for G_FCMP
Patch by Tom Stellard

llvm-svn: 326587
2018-03-02 16:53:15 +00:00
Matt Arsenault 2607dc60de AMDGPU/GlobalISel: Define instruction mapping for @llvm.minnum
Patch by Tom Stellard

llvm-svn: 326586
2018-03-02 16:40:17 +00:00
Yaxun Liu 3c42f1c3c9 LoopUnroll: respect pragma unroll when AllowRemainder is disabled
Currently when AllowRemainder is disabled, pragma unroll count is not
respected even though there is no remainder. This bug causes a loop
fully unrolled in many cases even though the user specifies a unroll
count. Especially it affects OpenCL/CUDA since in many cases a loop
contains convergent instructions and currently AllowRemainder is
disabled for such loops.

Differential Revision: https://reviews.llvm.org/D43826

llvm-svn: 326585
2018-03-02 16:22:32 +00:00
Momchil Velikov 505614bb4f [ARM] Fix access to stack arguments when re-aligning SP in Armv6m
When an Armv6m function dynamically re-aligns the stack, access to incoming
stack arguments (and to stack area, allocated for register varargs) is done via
SP, which is incorrect, as the SP is offset by an unknown amount relative to the
value of SP upon function entry.

This patch fixes it, by making access to "fixed" frame objects be done via FP
when the function needs stack re-alignment.  It also changes the access to
"fixed" frame objects be done via FP (instead of using R6/BP) also for the case
when the stack frame contains variable sized objects. This should allow more
objects to fit within the immediate offset of the load instruction.

All of the above via a small refactoring to reuse the existing
`ARMFrameLowering::ResolveFrameIndexReference.`

Differential Revision: https://reviews.llvm.org/D43566

llvm-svn: 326584
2018-03-02 15:47:14 +00:00
Nicholas Wilson 36f14f41e6 [WebAssembly] Rename global types to match the notation in the spec
llvm-svn: 326583
2018-03-02 14:54:34 +00:00
Clement Courbet c9119b3b6a [MergeICmps] Revert accidentally submitted failing test case.
Reverts r326574.

llvm-svn: 326582
2018-03-02 14:53:33 +00:00
Nicholas Wilson f2f6d5e03b [WebAssembly] Export non-hidden defined data symbols via wasm globals
This fixes a TODO introduced in rLLD325861.

Differential Revision: https://reviews.llvm.org/D43930

llvm-svn: 326581
2018-03-02 14:51:36 +00:00
Nicholas Wilson f6dbc2edee [WebAssembly] Pass ownership of body to SyntheticFunction. NFC
This avoids the Writer unnecessarily having a member to retain ownership
of the function body.

Differential Revision: https://reviews.llvm.org/D43933

llvm-svn: 326580
2018-03-02 14:48:50 +00:00
Nicholas Wilson cb81a0c9d9 [WebAssembly] Add validation for init function signature
Differential Revision: https://reviews.llvm.org/D43947

llvm-svn: 326579
2018-03-02 14:46:54 +00:00
Stefan Pintilie b5a9440a80 [Power9] Add missing instructions to the Power 9 scheduler
Adding more instructions using InstRW so that we can move away from ItinRW
and ultimately have a complete Power 9 scheduler.

llvm-svn: 326578
2018-03-02 14:41:38 +00:00
Nicholas Wilson 3b82510523 [WebAssembly] Check function type indexes
Also update tests containing invalid Wasm files, exposed by the check

Differential Revision: https://reviews.llvm.org/D43954

llvm-svn: 326577
2018-03-02 14:35:29 +00:00