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In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 296252
This commit is contained in:
Nirav Dave
@@ -363,6 +363,9 @@ public:
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return false;
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}
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/// Returns if it's reasonable to merge stores to MemVT size.
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virtual bool canMergeStoresTo(EVT MemVT) const { return true; }
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/// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
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virtual bool isCheapToSpeculateCttz() const {
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return false;
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File diff suppressed because it is too large
Load Diff
@@ -850,7 +850,7 @@ TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
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MinFunctionAlignment = 0;
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PrefFunctionAlignment = 0;
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PrefLoopAlignment = 0;
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GatherAllAliasesMaxDepth = 6;
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GatherAllAliasesMaxDepth = 18;
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MinStackArgumentAlignment = 1;
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// TODO: the default will be switched to 0 in the next commit, along
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// with the Target-specific changes necessary.
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@@ -9254,7 +9254,7 @@ static SDValue performSTORECombine(SDNode *N,
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return SDValue();
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}
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/// This function handles the log2-shuffle pattern produced by the
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/// This function handles the log2-shuffle pattern produced by the
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/// LoopVectorizer for the across vector reduction. It consists of
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/// log2(NumVectorElements) steps and, in each step, 2^(s) elements
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/// are reduced, where s is an induction variable from 0 to
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@@ -500,6 +500,11 @@ class InstrItineraryData;
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bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
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unsigned &Cost) const override;
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bool canMergeStoresTo(EVT MemVT) const override {
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// Do not merge to larger than i32.
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return (MemVT.getSizeInBits() <= 32);
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}
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bool isCheapToSpeculateCttz() const override;
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bool isCheapToSpeculateCtlz() const override;
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@@ -59,10 +59,10 @@ define i64 @test_hfa_ignores_gprs([7 x float], [2 x float] %in, i64, i64 %res) {
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}
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; [2 x float] should not be promoted to double by the Darwin varargs handling,
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; but should go in an 8-byte aligned slot.
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; but should go in an 8-byte aligned slot and can be merged as integer stores.
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define void @test_varargs_stackalign() {
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; CHECK-LABEL: test_varargs_stackalign:
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; CHECK-DARWINPCS: stp {{w[0-9]+}}, {{w[0-9]+}}, [sp, #16]
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; CHECK-DARWINPCS: str {{x[0-9]+}}, [sp, #16]
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call void(...) @callee([3 x float] undef, [2 x float] [float 1.0, float 2.0])
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ret void
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@@ -205,10 +205,7 @@ declare i32 @args_i32(i32, i32, i32, i32, i32, i32, i32, i32, i16 signext, i32,
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define i32 @test8(i32 %argc, i8** nocapture %argv) nounwind {
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entry:
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; CHECK-LABEL: test8
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; CHECK: strb {{w[0-9]+}}, [sp, #3]
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; CHECK: strb wzr, [sp, #2]
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; CHECK: strb {{w[0-9]+}}, [sp, #1]
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; CHECK: strb wzr, [sp]
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; CHECK: str w8, [sp]
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; CHECK: bl
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; FAST-LABEL: test8
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; FAST: strb {{w[0-9]+}}, [sp]
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@@ -13,8 +13,8 @@ define void @t2() nounwind ssp {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: strh wzr, [sp, #32]
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; CHECK: stp xzr, xzr, [sp, #16]
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; CHECK: str xzr, [sp, #8]
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; CHECK: stp xzr, xzr, [sp, #8]
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; CHECK: str xzr, [sp, #24]
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%buf = alloca [26 x i8], align 1
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%0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0
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call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false)
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@@ -99,7 +99,7 @@ define void @test_nospare([8 x i64], [8 x float], ...) {
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; __stack field should point just past them.
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define void @test_offsetstack([8 x i64], [2 x i64], [3 x float], ...) {
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; CHECK-LABEL: test_offsetstack:
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; CHECK: sub sp, sp, #80
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; CHECK: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #-80]!
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; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #96
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; CHECK: add x[[VAR:[0-9]+]], {{x[0-9]+}}, :lo12:var
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; CHECK: str [[STACK_TOP]], [x[[VAR]]]
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@@ -4,8 +4,7 @@
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@g0 = external global <3 x float>, align 16
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@g1 = external global <3 x float>, align 4
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; CHECK: ldr s[[R0:[0-9]+]], {{\[}}[[R1:x[0-9]+]]{{\]}}, #4
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; CHECK: ld1{{\.?s?}} { v[[R0]]{{\.?s?}} }[1], {{\[}}[[R1]]{{\]}}
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; CHECK: ldr q[[R0:[0-9]+]], {{\[}}[[R1:x[0-9]+]], :lo12:g0
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; CHECK: str d[[R0]]
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define void @blam() {
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@@ -1,5 +1,4 @@
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; RUN: llc --combiner-alias-analysis=false < %s | FileCheck %s
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; RUN: llc --combiner-alias-analysis=true < %s | FileCheck %s
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; RUN: llc < %s | FileCheck %s
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; This test checks that we do not merge stores together which have
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; dependencies through their non-chain operands (e.g. one store is the
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@@ -1,13 +1,21 @@
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; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-insert-nops -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-insert-nops -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK
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; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-insert-nops -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECKNOP
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; CHECK: test01.cl:2:{{[0-9]+}}
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; CHECK-NEXT: s_nop 0
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; This test expects that we have one instance for each line in some order with "s_nop 0" instances after each.
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; CHECK: test01.cl:3:{{[0-9]+}}
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; CHECK-NEXT: s_nop 0
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; Check that each line appears at least once
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; CHECK-DAG: test01.cl:2:3
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; CHECK-DAG: test01.cl:3:3
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; CHECK-DAG: test01.cl:4:3
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; CHECK: test01.cl:4:{{[0-9]+}}
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; CHECK-NEXT: s_nop 0
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; Check that each of each of the lines consists of the line output, followed by "s_nop 0"
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; CHECKNOP: test01.cl:{{[234]}}:3
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; CHECKNOP-NEXT: s_nop 0
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; CHECKNOP: test01.cl:{{[234]}}:3
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; CHECKNOP-NEXT: s_nop 0
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; CHECKNOP: test01.cl:{{[234]}}:3
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; CHECKNOP-NEXT: s_nop 0
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; CHECK: test01.cl:5:{{[0-9]+}}
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; CHECK-NEXT: s_nop 0
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@@ -21,7 +29,7 @@ entry:
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call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !17, metadata !18), !dbg !19
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%0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !20
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%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i32 0, !dbg !20
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store i32 1, i32 addrspace(1)* %arrayidx, align 4, !dbg !21
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store i32 1, i32 addrspace(1)* %arrayidx, align 4, !dbg !20
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%1 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !22
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%arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %1, i32 1, !dbg !22
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store i32 2, i32 addrspace(1)* %arrayidx1, align 4, !dbg !23
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@@ -255,11 +255,9 @@ define void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> %a
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; GCN: buffer_load_ubyte v{{[0-9]+}}, off
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; GCN: buffer_load_ubyte v{{[0-9]+}}, off
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; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:6
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; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:5
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; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4
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; GCN: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}}
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; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:5
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; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:6
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; GCN: buffer_load_ubyte
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; GCN: buffer_load_ubyte
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@@ -1,8 +1,5 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-NOAA %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-NOAA %s
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; RUN: llc -march=amdgcn -verify-machineinstrs -combiner-alias-analysis -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -combiner-alias-analysis -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s
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; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s
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; This test is mostly to test DAG store merging, so disable the vectorizer.
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; Run with devices with different unaligned load restrictions.
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@@ -150,12 +147,7 @@ define void @merge_global_store_4_constants_f32(float addrspace(1)* %out) #0 {
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}
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; GCN-LABEL: {{^}}merge_global_store_4_constants_mixed_i32_f32:
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; GCN-NOAA: buffer_store_dwordx4 v
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; GCN-AA: buffer_store_dwordx2
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; GCN-AA: buffer_store_dword v
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; GCN-AA: buffer_store_dword v
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; GCN-AA: buffer_store_dwordx4 v
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; GCN: s_endpgm
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define void @merge_global_store_4_constants_mixed_i32_f32(float addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
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@@ -474,17 +466,9 @@ define void @merge_global_store_4_adjacent_loads_i8_natural_align(i8 addrspace(1
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ret void
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}
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; This works once AA is enabled on the subtarget
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; GCN-LABEL: {{^}}merge_global_store_4_vector_elts_loads_v4i32:
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; GCN: buffer_load_dwordx4 [[LOAD:v\[[0-9]+:[0-9]+\]]]
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; GCN-NOAA: buffer_store_dword v
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; GCN-NOAA: buffer_store_dword v
|
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; GCN-NOAA: buffer_store_dword v
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; GCN-NOAA: buffer_store_dword v
|
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; GCN-AA: buffer_store_dwordx4 [[LOAD]]
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; GCN: buffer_store_dwordx4 [[LOAD]]
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; GCN: s_endpgm
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define void @merge_global_store_4_vector_elts_loads_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 {
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
|
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@@ -32,10 +32,10 @@
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; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], s9 offset:40{{$}}
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; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], s9 offset:44{{$}}
|
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|
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; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}}
|
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; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}}
|
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; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}}
|
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; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}}
|
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; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}}
|
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; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}}
|
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; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}}
|
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; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}}
|
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define void @private_elt_size_v4i32(<4 x i32> addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
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@@ -130,8 +130,8 @@ entry:
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; HSA-ELT8: private_element_size = 2
|
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; HSA-ELT4: private_element_size = 1
|
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|
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; HSA-ELTGE8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:16
|
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; HSA-ELTGE8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:24
|
||||
; HSA-ELTGE8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, {{off|v[0-9]}}, s[0:3], s9 offset:1
|
||||
; HSA-ELTGE8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, {{off|v[0-9]}}, s[0:3], s9 offset:2
|
||||
|
||||
; HSA-ELTGE8: buffer_load_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen
|
||||
|
||||
|
||||
@@ -157,9 +157,8 @@ define void @reorder_global_load_local_store_global_load(i32 addrspace(1)* %out,
|
||||
|
||||
; FUNC-LABEL: @reorder_local_offsets
|
||||
; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:100 offset1:102
|
||||
; CI: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset0:3 offset1:100
|
||||
; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:12
|
||||
; CI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:408
|
||||
; CI-DAG: ds_write2_b32 {{v[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:3 offset1:100
|
||||
; CI-DAG: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:408
|
||||
; CI: buffer_store_dword
|
||||
; CI: s_endpgm
|
||||
define void @reorder_local_offsets(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* noalias nocapture readnone %gptr, i32 addrspace(3)* noalias nocapture %ptr0) #0 {
|
||||
@@ -181,12 +180,12 @@ define void @reorder_local_offsets(i32 addrspace(1)* nocapture %out, i32 addrspa
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @reorder_global_offsets
|
||||
; CI: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400
|
||||
; CI: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408
|
||||
; CI: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:12
|
||||
; CI: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400
|
||||
; CI: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408
|
||||
; CI: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:12
|
||||
; CI-DAG: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400
|
||||
; CI-DAG: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408
|
||||
; CI-DAG: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:12
|
||||
; CI-DAG: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400
|
||||
; CI-DAG: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408
|
||||
; CI: buffer_store_dword
|
||||
; CI: s_endpgm
|
||||
define void @reorder_global_offsets(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* noalias nocapture readnone %gptr, i32 addrspace(1)* noalias nocapture %ptr0) #0 {
|
||||
%ptr1 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 3
|
||||
|
||||
@@ -12,7 +12,8 @@ define void @test_byval_8_bytes_alignment(i32 %i, ...) {
|
||||
entry:
|
||||
; CHECK: sub sp, sp, #12
|
||||
; CHECK: sub sp, sp, #4
|
||||
; CHECK: stmib sp, {r1, r2, r3}
|
||||
; CHECK: add r0, sp, #4
|
||||
; CHECK: stm sp, {r0, r1, r2, r3}
|
||||
%g = alloca i8*
|
||||
%g1 = bitcast i8** %g to i8*
|
||||
call void @llvm.va_start(i8* %g1)
|
||||
|
||||
@@ -1,5 +1,4 @@
|
||||
; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=NO-REALIGN
|
||||
; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=REALIGN
|
||||
; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s
|
||||
|
||||
; rdar://12713765
|
||||
; When realign-stack is set to false, make sure we are not creating stack
|
||||
@@ -8,29 +7,31 @@
|
||||
|
||||
define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" {
|
||||
entry:
|
||||
; NO-REALIGN-LABEL: test1
|
||||
; NO-REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
|
||||
; NO-REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
|
||||
; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
|
||||
; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48
|
||||
; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
|
||||
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48
|
||||
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
|
||||
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; NO-REALIGN: mov r[[R3:[0-9]+]], r[[R1]]
|
||||
; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R3]]:128]!
|
||||
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R3]]:128]
|
||||
|
||||
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48
|
||||
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0]], #32
|
||||
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
|
||||
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
|
||||
; CHECK-LABEL: test1
|
||||
; CHECK: ldr r[[R1:[0-9]+]], [pc, r1]
|
||||
; CHECK: add r[[R2:[0-9]+]], r1, #48
|
||||
; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; CHECK: mov r[[R2:[0-9]+]], r[[R1]]
|
||||
; CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
|
||||
; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; CHECK: add r[[R1:[0-9]+]], r[[R1]], #32
|
||||
; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; CHECK: mov r[[R1:[0-9]+]], sp
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; CHECK: add r[[R2:[0-9]+]], r[[R1]], #32
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]!
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; CHECK: add r[[R1:[0-9]+]], r0, #48
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; CHECK: add r[[R1:[0-9]+]], r0, #32
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r0:128]!
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r0:128]
|
||||
%retval = alloca <16 x float>, align 16
|
||||
%0 = load <16 x float>, <16 x float>* @T3_retval, align 16
|
||||
store <16 x float> %0, <16 x float>* %retval
|
||||
@@ -41,32 +42,33 @@ entry:
|
||||
|
||||
define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp {
|
||||
entry:
|
||||
; REALIGN-LABEL: test2
|
||||
; REALIGN: bfc sp, #0, #6
|
||||
; REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
|
||||
; REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
|
||||
; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
|
||||
; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48
|
||||
; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; CHECK: ldr r[[R1:[0-9]+]], [pc, r1]
|
||||
; CHECK: add r[[R2:[0-9]+]], r[[R1]], #48
|
||||
; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; CHECK: mov r[[R2:[0-9]+]], r[[R1]]
|
||||
; CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
|
||||
; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; CHECK: add r[[R1:[0-9]+]], r[[R1]], #32
|
||||
; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; CHECK: mov r[[R1:[0-9]+]], sp
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; CHECK: orr r[[R2:[0-9]+]], r[[R1]], #32
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]!
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; CHECK: add r[[R1:[0-9]+]], r0, #48
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; CHECK: add r[[R1:[0-9]+]], r0, #32
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r0:128]!
|
||||
; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r0:128]
|
||||
|
||||
|
||||
; REALIGN: orr r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48
|
||||
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #32
|
||||
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #16
|
||||
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
|
||||
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
|
||||
; REALIGN: add r[[R1:[0-9]+]], r[[R0:0]], #48
|
||||
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #32
|
||||
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
|
||||
; REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
|
||||
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
|
||||
%retval = alloca <16 x float>, align 16
|
||||
%retval = alloca <16 x float>, align 16
|
||||
%0 = load <16 x float>, <16 x float>* @T3_retval, align 16
|
||||
store <16 x float> %0, <16 x float>* %retval
|
||||
%1 = load <16 x float>, <16 x float>* %retval
|
||||
|
||||
@@ -16,22 +16,22 @@ define void @foo(i64* %addr) {
|
||||
; an LDMIA was created with both a FrameIndex and an offset, which
|
||||
; is not allowed.
|
||||
|
||||
; CHECK-WITH-LDRD: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]
|
||||
; CHECK-WITH-LDRD: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp]
|
||||
; CHECK-WITH-LDRD-DAG: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]
|
||||
; CHECK-WITH-LDRD-DAG: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp]
|
||||
|
||||
; CHECK-WITH-LDRD: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]
|
||||
; CHECK-WITH-LDRD: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp]
|
||||
; CHECK-WITH-LDRD-DAG: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]
|
||||
; CHECK-WITH-LDRD-DAG: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp]
|
||||
|
||||
; We also want to ensure the register scavenger is working (i.e. an
|
||||
; offset from sp can be generated), so we need two spills.
|
||||
; CHECK-WITHOUT-LDRD: add [[ADDRREG:[a-z0-9]+]], sp, #{{[0-9]+}}
|
||||
; CHECK-WITHOUT-LDRD: stm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
|
||||
; CHECK-WITHOUT-LDRD: stm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
|
||||
; CHECK-WITHOUT-LDRD-DAG: add [[ADDRREG:[a-z0-9]+]], sp, #{{[0-9]+}}
|
||||
; CHECK-WITHOUT-LDRD-DAG: stm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
|
||||
; CHECK-WITHOUT-LDRD-DAG: stm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
|
||||
|
||||
; In principle LLVM may have to recalculate the offset. At the moment
|
||||
; it reuses the original though.
|
||||
; CHECK-WITHOUT-LDRD: ldm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
|
||||
; CHECK-WITHOUT-LDRD: ldm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
|
||||
; CHECK-WITHOUT-LDRD-DAG: ldm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
|
||||
; CHECK-WITHOUT-LDRD-DAG: ldm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
|
||||
|
||||
store volatile i64 %val1, i64* %addr
|
||||
store volatile i64 %val2, i64* %addr
|
||||
|
||||
@@ -9,8 +9,6 @@ entry:
|
||||
; CHECK-LABEL: t:
|
||||
; CHECK: vpop {d8}
|
||||
; CHECK-NOT: vpopne
|
||||
; CHECK: pop {r7, pc}
|
||||
; CHECK: vpop {d8}
|
||||
; CHECK: pop {r7, pc}
|
||||
br i1 undef, label %if.else, label %if.then
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user