Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Ethernet MAC addresses are not unique enough
use unique_device_ID full range (96 bits)
call crc32_ieee() to generate last 3 bytes of mac address
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
When ENET_ENHANCEDBUFFERDESCRIPTOR_MODE enabled,
MAC will automatic capture receive nanosecond from 1588TMR
and return back to ENET_ReadFrame. It is a highest accuracy
recv timestamp_ns, we do not need manually read from 1588TMR.
By this change, receive timestamp accuracy increase
from 20us to 200ns above.
Signed-off-by: Chen Caidy <chen@caidy.cc>
Add the RCR_PRMS field to toggle the promiscuous mode in the Ethernet
controller.
Register a set_config function that can make use of the field when
CONFIG_NET_PROMISCUOUS_MODE is enabled.
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Quite a few of the drivers meant for the POSIX arch
interacted with the host directly, and will not
work when we use an embedded libC.
Until we fix them, let's add the appropriate
kconfig dependencies to avoid users trying to build them.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Adds PHY driver. Works via MDIO API and
exposed ADIN2111 MDIO Clause 45
functions.
Link status detection is triggered by
ADIN2111 driver within offloaded IRQ
handler.
Supports:
- LED0, LED1 enable/disable
- Fatal HW error detection
- AN 2.4V tx mode enable/disable
The initialization order is important.
PHY 2 must be initialized after PHY1.
Therefore, it shall be defined after the 1st one
in the devicetree.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Adds initial ADIN2111 2-Port 10BASE-T1L (SPE)
switch support. Works over SPI.
The driver creates 2 interfaces, 1 per port (PHY).
Configures multicast and broadcast filters.
The same unicast is applied to both ports.
Supports:
- Link state detection
- CRC enable/disable
- Ports config set
- Ports ETH stats
Provides functions for MDIO driver.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Make it possible to be able to change speed and duplex for the
STM32H7xx and API_V2 from the configuration settings.
This exists for the non-STM32H7x already today, so this is basically
copying the code for the other STM32's.
Please note that ST has a series incompability. For F1 and F2,
the duplex settings are named ETH_MODE_FULLDUPLEX respective
ETH_MODE_HALFDUPLEX. For F4, H7 and F7 the duplex settings are named
ETH_FULLDUPLEX_MODE respective ETG_HALFDUPLEX_MODE.
This should really be queried from the PHY (as previous programmer have
written in the code). But while waiting for a proper PHY solution,
this is intended as a stop-gap solution.
Signed-off-by: Stefan Petersen <spe@ciellt.se>
Without this change, there's a difference between what the V2 Ethernet
HAL claims to be its capabilities in eth_stm32_hal_get_capabilities()
and what is actually enabled when CONFIG_ETH_STM32_HW_CHECKSUM is
disabled. This difference somehow causes the checksum in outgoing
packets to become 0, and hence seems to break networking at least on
some PHYs.
This commit disables HW checksums by default even when V2 driver is in
use, and this hence fixes networking when CONFIG_ETH_STM32_HW_CHECKSUM
is disabled.
This fixes#57629.
Signed-off-by: Ole Morten Haaland <omh@icsys.no>
This patch enables the PLL clock output and PLL ref clock
for second ethernet module in NXP's i.MxRT106x SoCs
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Fix a compilation error for the ethernet driver smsc91x that
prevents the build with asserts enabled.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
rx_thread() is started by eth_initialize(), while dev_data->iface is
populated by eth_iface_init() (called by net_init()).
Usually eth_iface_init() has completed by the time rx_thread() hits its
idle timeout and accesses dev_data->iface, but in case of a time-intensive
SYS_INIT item between eth_initialize() and net_init(), this is not
necessarily the case, causing a NULL dereference. This can be forced by
putting a k_sleep(K_SECONDS(5)) at the top of eth_iface_init().
Start rx_thread() in eth_iface_init() instead (which runs after
eth_initialize() due to init priorities) to make sure everything is
initialized properly.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Allows Ethernet communication between "cells"
in the Jailhouse hypervisor.
The vring queue deviates from a standard virtqueue
so is implemented separately.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
In the case that there is a situation where the controller
oscillator start-up timer doesn't expire, or the SPI can't
read the CLKRDY bit the driver would hang during init.
The config option ETH_ENC28J60_CLKRDY_INIT_WAIT_MS sets
the time that the driver will wait for OST before returning
an ETIMEDOUT error.
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
Allow defining multiple instances of enc28j60.
Remove the ETH_ENC28J60_0 Kconfig option along with this.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add the `full-duplex` property for the `microchip,enc28j60` node.
Replace ETH_ENC28J60_0_FULL_DUPLEX Kconfig option with this property.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
When running cppcheck on eth_stm32_hal.c it generated a warning for
shiftTooManyBitsSigned.
The solution is to make sure that the numeric value shifted is unsigned.
Updated to use BIT() macro as suggested by GeorgeGCV.
Fixes: #57336
Signed-off-by: Stefan Petersen <spe@ciellt.se>
Some single-precision float constants were being compared against
double-precision floats. Make the constants doubles.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
According to the datasheet for Marvell PHY [1], the mode field of the
General Control Register 1 Page 18 occupies bits [2:0]. However, the macro
PHY_MRVL_MODE_CONFIG_MASK specifies the mask as 0x3, which would
correspond only to [1:0]. The code in phy_xlnx_gem_marvell_alaska_cfg()
uses the mask to set the mode field to 0 to set "RGMII (System mode) to
Copper" mode. Unfortunately, different chips have different reset values
(111 or 000) and in first case, the code would set the field to 100,
instead of 000.
Without this change, ethernet on Avnet MicroZed (Marvel Alaska 88E1512 PHY)
does not work.
Signed-off-by: Marek Vedral <vedrama5@fel.cvut.cz>
[1]: https://www.marvell.com/content/dam/marvell/en/public-collateral/phys-transceivers/marvell-ethernet-phys-alaska-88e151x-datasheet.pdf
The SAM GMAC driver is not able to use all of the receive buffers
concurrently. Frames larger than (buffer size) * (buffer count - 1) are
silently dropped. Fix it by adding one to MAIN_QUEUE_RX_DESC_COUNT.
Fixes#55701
Signed-off-by: Brandon Del Bel <delbel@umn.edu>
