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drivers: spi: Microchip XEC QMSPI-LDMA fix spi buffer usage

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Zephyr SPI driver model for full-duplex operation assumes
data will be transmitted and received during each clock period.
The QMSPI driver for the XEC family also supported dual and
quad I/O use cases which are inherently half-duplex. To
support dual/quad the driver incorrectly processed spi buffers
as all transmit buffers first then all receive buffers. This
worked if only the SPI driver was used. It did not work with
the Zephyr flash SPI NOR driver which assumes SPI drivers
follow the SPI driver model. This commit implements a QMSPI
driver that follows the Zephyr SPI driver model resulting in
a slightly smaller driver. Dual/quad SPI transactions are
supported if the experimental SPI extended mode Zephyr
configuration flag is enabled. We also remove the QMSPI full duplex
driver added previously to support the flash SPI NOR driver.
Added board to spi loop-back test and spi_flash sample.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit is contained in:
Scott Worley
2023-01-14 13:59:57 -05:00
committed by Carles Cufí
parent a6e5755da8
commit 5c00a83b99
13 changed files with 708 additions and 1715 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.dts
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@@ -212,7 +212,6 @@
clock-frequency = <4000000>;
lines = <4>;
chip-select = <0>;
port-sel = <0>; /* Shared SPI */
pinctrl-0 = < &shd_cs0_n_gpio055
&shd_clk_gpio056

1
drivers/spi/CMakeLists.txt
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@@ -28,7 +28,6 @@ zephyr_library_sources_ifdef(CONFIG_SPI_PSOC6 spi_psoc6.c)
zephyr_library_sources_ifdef(CONFIG_SPI_NPCX_FIU spi_npcx_fiu.c)
zephyr_library_sources_ifdef(CONFIG_SPI_BITBANG spi_bitbang.c)
zephyr_library_sources_ifdef(CONFIG_SPI_XEC_QMSPI_LDMA spi_xec_qmspi_ldma.c)
zephyr_library_sources_ifdef(CONFIG_SPI_XEC_QMSPI_FULL_DUPLEX spi_xec_qmspi_full_duplex.c)
zephyr_library_sources_ifdef(CONFIG_SPI_GD32 spi_gd32.c)
zephyr_library_sources_ifdef(CONFIG_SPI_MCHP_QSPI spi_mchp_mss_qspi.c)
zephyr_library_sources_ifdef(CONFIG_SPI_PL022 spi_pl022.c)

8
drivers/spi/Kconfig.xec_qmspi
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@@ -17,11 +17,3 @@ config SPI_XEC_QMSPI_LDMA
depends on DT_HAS_MICROCHIP_XEC_QMSPI_LDMA_ENABLED
help
Enable support for Microchip MEC17xx QMSPI with local DMA driver.
config SPI_XEC_QMSPI_FULL_DUPLEX
bool "Microchip XEC MEC17xx QMSPI Full Duplex driver"
default y
depends on DT_HAS_MICROCHIP_XEC_QMSPI_FULL_DUPLEX_ENABLED
help
Enable support for Microchip MEC17xx QMSPI full duplex driver
to work with Zephyr NOR driver

714
drivers/spi/spi_xec_qmspi_full_duplex.c
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File diff suppressed because it is too large Load Diff

182
drivers/spi/spi_xec_qmspi_full_duplex.h
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@@ -1,182 +0,0 @@
/*
* Copyright (c) 2022 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SPI_XEC_QMSPI_V2_H
#define _SPI_XEC_QMSPI_V2_H
#define MEC152X_QSPI_SRC_CLOCK_HZ 48000000u
#define MEC172X_QSPI_SRC_CLOCK_HZ 48000000u
#define MEC172X_QSPI_TURBO_SRC_CLOCK_HZ 96000000u
#define XEC_QSPI_TX_FIFO_SIZE 8
#define XEC_QSPI_RX_FIFO_SIZE 8
#define XEC_QSPI_DESCR_MAX 16
/* mode register */
#define XEC_QSPI_M_ACTV_POS 0
#define XEC_QSPI_M_SRST_POS 1
#define XEC_QSPI_M_RX_LDMA_EN_POS 3
#define XEC_QSPI_M_TX_LDMA_EN_POS 4
#define XEC_QSPI_M_CPOL_POS 8
#define XEC_QSPI_M_CPHA_MOSI_POS 9
#define XEC_QSPI_M_CPHA_MISO_POS 10
#define XEC_QSPI_M_CP_MSK (0x7u << XEC_QSPI_M_CPOL_POS)
#define XEC_QSPI_M_CS_SEL_POS 12
#define XEC_QSPI_M_CS_SEL_MSK (0x3u << XEC_QSPI_M_CS_SEL_POS)
#define XEC_QSPI_M_CS0_SEL 0
#define XEC_QSPI_M_CS1_SEL (1u << XEC_QSPI_M_CS_SEL_POS)
#define XEC_QSPI_M_CLK_DIV_POS 16
#ifdef CONFIG_SOC_SERIES_MEC172X
#define XEC_QSPI_M_CLK_DIV_MASK 0xffff0000u
#else
#define XEC_QSPI_M_CLK_DIV_MASK 0xff000000u
#endif
/* control register */
#define XEC_QSPI_C_IFC_POS 0
#define XEC_QSPI_C_IFC_MSK 0x3u
#define XEC_QSPI_C_IFC_1X 0
#define XEC_QSPI_C_IFC_2X 0x1u
#define XEC_QSPI_C_IFC_4X 0x2u
#define XEC_QSPI_C_TX_EN_POS 2
#define XEC_QSPI_C_TX_EN_MSK (0x3u << XEC_QSPI_C_TX_EN_POS)
#define XEC_QSPI_C_TX_EN_DATA (0x1u << XEC_QSPI_C_TX_EN_POS)
#define XEC_QSPI_C_TX_EN_ZEROS (0x2u << XEC_QSPI_C_TX_EN_POS)
#define XEC_QSPI_C_TX_EN_ONES (0x3u << XEC_QSPI_C_TX_EN_POS)
#define XEC_QSPI_C_TX_DMA_EN_POS 4
#define XEC_QSPI_C_TX_DMA_EN_MSK (0x3u << XEC_QSPI_C_TX_DMA_EN_POS)
#define XEC_QSPI_C_TX_DMA_EN_1B (0x1u << XEC_QSPI_C_TX_DMA_EN_POS)
#define XEC_QSPI_C_TX_DMA_EN_2B (0x2u << XEC_QSPI_C_TX_DMA_EN_POS)
#define XEC_QSPI_C_TX_DMA_EN_4B (0x3u << XEC_QSPI_C_TX_DMA_EN_POS)
#ifdef CONFIG_SOC_SERIES_MEC172X
#define XEC_QSPI_C_TX_DMA_EN_LDCH0 (0x1u << XEC_QSPI_C_TX_DMA_EN_POS)
#define XEC_QSPI_C_TX_DMA_EN_LDCH1 (0x2u << XEC_QSPI_C_TX_DMA_EN_POS)
#define XEC_QSPI_C_TX_DMA_EN_LDCH2 (0x3u << XEC_QSPI_C_TX_DMA_EN_POS)
#endif
#define XEC_QSPI_C_RX_EN_POS 6
#define XEC_QSPI_C_RX_DMA_EN_POS 7
#define XEC_QSPI_C_RX_DMA_EN_MSK (0x3u << XEC_QSPI_C_RX_DMA_EN_POS)
#define XEC_QSPI_C_RX_DMA_EN_1B (0x1u << XEC_QSPI_C_RX_DMA_EN_POS)
#define XEC_QSPI_C_RX_DMA_EN_2B (0x2u << XEC_QSPI_C_RX_DMA_EN_POS)
#define XEC_QSPI_C_RX_DMA_EN_4B (0x3u << XEC_QSPI_C_RX_DMA_EN_POS)
#ifdef CONFIG_SOC_SERIES_MEC172X
#define XEC_QSPI_C_RX_DMA_EN_LDCH0 (0x1u << XEC_QSPI_C_RX_DMA_EN_POS)
#define XEC_QSPI_C_RX_DMA_EN_LDCH1 (0x2u << XEC_QSPI_C_RX_DMA_EN_POS)
#define XEC_QSPI_C_RX_DMA_EN_LDCH2 (0x3u << XEC_QSPI_C_RX_DMA_EN_POS)
#endif
#define XEC_QSPI_C_CLOSE_POS 9
#define XEC_QSPI_C_Q_XFR_UNITS_POS 10
#define XEC_QSPI_C_Q_XFR_UNITS_MSK (0x3u << XEC_QSPI_C_Q_XFR_UNITS_POS)
#define XEC_QSPI_C_Q_XFR_UNITS_BITS 0
#define XEC_QSPI_C_Q_XFR_UNITS_1B (0x1u << XEC_QSPI_C_Q_XFR_UNITS_POS)
#define XEC_QSPI_C_Q_XFR_UNITS_4B (0x2u << XEC_QSPI_C_Q_XFR_UNITS_POS)
#define XEC_QSPI_C_Q_XFR_UNITS_16B (0x3u << XEC_QSPI_C_Q_XFR_UNITS_POS)
#define XEC_QSPI_C_FN_DESCR_POS 12
#define XEC_QSPI_C_FN_DESCR_MSK (0xfu << XEC_QSPI_C_FN_DESCR_POS)
#define XEC_QSPI_C_FN_DESCR(n) \
(((uint32_t)(n) & 0xfu) << XEC_QSPI_C_FN_DESCR_POS)
/* control register enable descriptor mode */
#define XEC_QSPI_C_DESCR_MODE_EN_POS 16
/* descriptor specifies last descriptor to be processed */
#define XEC_QSPI_D_DESCR_LAST_POS 16
#define XEC_QSPI_C_Q_NUNITS_POS 17
#define XEC_QSPI_C_Q_NUNITS_MAX 0x7fffu
#define XEC_QSPI_C_Q_NUNITS_MSK (0x7fffu << XEC_QSPI_C_Q_NUNITS_POS)
#define XEC_QSPI_C_NUNITS(n) \
(((uint32_t)(n) & 0x7fffu) << XEC_QSPI_C_Q_NUNITS_POS)
/* execute register (WO). Set one bit at a time! */
#define XEC_QSPI_EXE_START_POS 0
#define XEC_QSPI_EXE_STOP_POS 1
#define XEC_QSPI_EXE_CLR_FIFOS_POS 2
/* status register */
#define XEC_QSPI_STS_MSK 0x0f01ff7fu
#define XEC_QSPI_STS_MSK_RW1C 0x0000cc1fu
#define XEC_QSPI_STS_XFR_DONE_POS 0
#define XEC_QSPI_STS_DMA_DONE_POS 1
#define XEC_QSPI_STS_TXB_ERR_POS 2
#define XEC_QSPI_STS_RXB_ERR_POS 3
#define XEC_QSPI_STS_PROG_ERR_POS 4
#ifdef CONFIG_SOC_SERIES_MEC172X
#define XEC_QSPI_STS_LDMA_RX_ERR_POS 5
#define XEC_QSPI_STS_LDMA_TX_ERR_POS 6
#endif
#define XEC_QSPI_STS_TXB_FULL_POS 8
#define XEC_QSPI_STS_TXB_EMPTY_POS 9
#define XEC_QSPI_STS_TXB_REQ_POS 10
#define XEC_QSPI_STS_TXB_STALL_POS 11
#define XEC_QSPI_STS_RXB_FULL_POS 12
#define XEC_QSPI_STS_RXB_EMPTY_POS 13
#define XEC_QSPI_STS_RXB_REQ_POS 14
#define XEC_QSPI_STS_RXB_STALL_POS 15
#define XEC_QSPI_STS_XFR_ACTIVE_POS 16
#define XEC_QSPI_STS_CURR_DESCR_POS 24
#define XEC_QSPI_STS_CURR_DESCR_MSK (0xfu << XEC_QSPI_STS_CURR_DESCR_POS)
#define XEC_QSPI_STS_ALL_ERR (BIT(XEC_QSPI_STS_TXB_ERR_POS) | \
BIT(XEC_QSPI_STS_RXB_ERR_POS) | \
BIT(XEC_QSPI_STS_PROG_ERR_POS))
/* buffer count status (RO) */
#define XEC_QSPI_BCNT_STS_TX_POS 0
#define XEC_QSPI_BCNT_STS_TX_MSK 0xffffu
#define XEC_QSPI_BCNT_STS_RX_POS 16
#define XEC_QSPI_BCNT_STS_RX_MSK (0xffffu << XEC_QSPI_BCNT_STS_RX_POS)
/* interrupt enable */
#define XEC_QSPI_IEN_XFR_DONE_POS 0
#define XEC_QSPI_IEN_DMA_DONE_POS 1
#define XEC_QSPI_IEN_TXB_ERR_POS 2
#define XEC_QSPI_IEN_RXB_ERR_POS 3
#define XEC_QSPI_IEN_PROG_ERR_POS 4
#ifdef CONFIG_SOC_SERIES_MEC172X
#define XEC_QSPI_IEN_LDMA_RX_ERR_POS 5
#define XEC_QSPI_IEN_LDMA_TX_ERR_POS 6
#endif
#define XEC_QSPI_IEN_TXB_FULL_POS 8
#define XEC_QSPI_IEN_TXB_EMPTY_POS 9
#define XEC_QSPI_IEN_TXB_REQ_POS 10
#define XEC_QSPI_IEN_RXB_FULL_POS 12
#define XEC_QSPI_IEN_RXB_EMPTY_POS 13
#define XEC_QSPI_IEN_RXB_REQ_POS 14
/* chip select timing */
#define XEC_QSPI_CSTM_DLY_CS_TO_START_POS 0
#define XEC_QSPI_CSTM_DLY_CS_TO_START_MSK 0xfu
#define XEC_QSPI_CSTM_DLY_CLK_OFF_TO_CS_OFF_POS 8
#define XEC_QSPI_CSTM_DLY_CLK_OFF_TO_CS_OFF_MSK 0xf00u
#define XEC_QSPI_CSTM_DLY_LAST_DATA_HOLD_POS 16
#define XEC_QSPI_CSTM_DLY_LAST_DATA_HOLD_MSK 0xf0000u
#define XEC_QSPI_CSTM_DLY_CS_OFF_TO_CS_ON_POS 24
#define XEC_QSPI_CSTM_DLY_CS_OFF_TO_CS_ON_MSK 0xff000000u
#ifdef CONFIG_SOC_SERIES_MEC172X
#define XEC_QSPI_MALT1_EN_POS 0
#define XEC_QSPI_MALT1_CLK_DIV_POS 16
#define XEC_QSPI_MALT1_CLK_DIV_MSK 0xffff0000u
#define XEC_QSPI_LDCH_CTRL_EN_POS 0
#define XEC_QSPI_LDCH_CTRL_RESTART_EN_POS 1
#define XEC_QSPI_LDCH_CTRL_RESTART_ADDR_EN_POS 2
#define XEC_QSPI_LDCH_CTRL_OVRLEN_POS 3
#define XEC_QSPI_LDCH_CTRL_ACCSZ_POS 4
#define XEC_QSPI_LDCH_CTRL_ACCSZ_MSK 0x30u
#define XEC_QSPI_LDCH_CTRL_ACCSZ_1B 0u
#define XEC_QSPI_LDCH_CTRL_ACCSZ_2B 1u
#define XEC_QSPI_LDCH_CTRL_ACCSZ_4B 2u
#define XEC_QSPI_LDCH_CTRL_INCR_ADDR_POS 6
struct qspi_ldma_chan {
volatile uint32_t ldctrl;
volatile uint32_t mstart;
volatile uint32_t nbytes;
uint32_t rsvd[1];
};
#endif /* CONFIG_SOC_SERIES_MEC172X */
#endif /* _SPI_XEC_QMSPI_V2_H */

1237
drivers/spi/spi_xec_qmspi_ldma.c
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File diff suppressed because it is too large Load Diff

2
dts/arm/microchip/mec172xnsz.dtsi
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@@ -720,7 +720,7 @@
reg = <0x40070000 0x400>;
interrupts = <91 2>;
girqs = < MCHP_XEC_ECIA(18, 1, 10, 91) >;
pcrs = <4 8>;
clocks = <&pcr 4 8 MCHP_XEC_PCR_CLK_PERIPH>;
clock-frequency = <12000000>;
lines = <1>;
chip-select = <0>;

9
dts/bindings/spi/microchip,xec-qmspi-full-duplex.yaml
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@@ -1,9 +0,0 @@
# Copyright (c) 2018, Google LLC.
# Copyright (c) 2022, Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
description: Microchip XEC QMSPI controller with local DMA
compatible: "microchip,xec-qmspi-full-duplex"
include: [microchip-xec-qmspi-v2.yaml]

91
dts/bindings/spi/microchip,xec-qmspi-ldma.yaml
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@@ -6,4 +6,93 @@ description: Microchip XEC QMSPI controller with local DMA
compatible: "microchip,xec-qmspi-ldma"
include: [microchip-xec-qmspi-v2.yaml]
include: [spi-controller.yaml, pinctrl-device.yaml]
properties:
reg:
required: true
clocks:
required: true
interrupts:
required: true
girqs:
type: array
required: true
description: |
An array of integers encoding each interrupt signal connection.
This information includes the aggregated GIRQ number, GIRQ bit
position, aggregated GIRQ NVIC connection, and direct NVIC
connection of the GIRQ bit.
pinctrl-0:
required: true
pinctrl-names:
required: true
lines:
type: int
description: |
QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
MOSI and MISO or half-duplex on MOSI only. Lines set to 2
or 4 indicate dual or quad I/O modes.
Defaults to 1 for full duplex driver's support for full-duplex spi.
enum:
- 1
- 2
- 4
chip-select:
type: int
description: |
Use QMSPI CS0# or CS1#. Port 0 supports both chip selects.
Ports 1 and 2 implement CS0# only. Defaults to CS0#.
dcsckon:
type: int
description: |
Delay in QMSPI main clocks from CS# assertion to first clock edge.
If not present use hardware default value. Refer to chip documention
for QMSPI input clock frequency.
dckcsoff:
type: int
description: |
Delay in QMSPI main clocks from last clock edge to CS# de-assertion.
If not present use hardware default value. Refer to chip documention
for QMSPI input clock frequency.
dldh:
type: int
description: |
Delay in QMSPI main clocks from CS# de-assertion to driving HOLD#
and WP#. If not present use hardware default value. Refer to chip
documentation for QMSPI input clock frequency.
dcsda:
type: int
description: |
Delay in QMSPI main clocks from CS# de-assertion to CS# assertion.
If not present use hardware default value. Refer to chip documention
for QMSPI input clock frequency.
cs1-freq:
type: int
description: |
Allows different frequencies for CS#0 and CS1# devices. This applies
to ports implementing CS1#.
tctradj:
type: int
description: |
An optional signed 8-bit value for adjusting the QMSPI control signal
timing tap.
tsckadj:
type: int
description: |
An optional signed 8-bit value for adjusting the QMSPI clock signal
timing tap.

105
dts/bindings/spi/microchip-xec-qmspi-v2.yaml
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@@ -1,105 +0,0 @@
# Copyright (c) 2018, Google LLC.
# Copyright (c) 2022, Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
description: Microchip XEC QMSPI controller V2
include: [spi-controller.yaml, pinctrl-device.yaml]
properties:
reg:
required: true
girqs:
type: array
required: true
description: |
An array of integers encoding each interrupt signal connection.
This information includes the aggregated GIRQ number, GIRQ bit
position, aggregated GIRQ NVIC connection, and direct NVIC
connection of the GIRQ bit.
pcrs:
type: array
required: true
description: |
A two entry integer array containing the QMSPI PCR sleep register
index and bit position.
pinctrl-0:
required: true
pinctrl-names:
required: true
lines:
type: int
description: |
QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
MOSI and MISO or half-duplex on MOSI only. Lines set to 2
or 4 indicate dual or quad I/O modes.
Defaults to 1 for full duplex driver's support for full-duplex spi.
enum:
- 1
- 2
- 4
port-sel:
type: int
description: |
SPI Port 0, 1, or 2. Port 0 is the shared SPI, port 1 is
the private SPI, and port 2 is the internal SPI port for
chip configurations with an embedded SPI flash. Defaults
to port 0 (shared SPI port).
chip-select:
type: int
description: |
Use QMSPI CS0# or CS1#. Port 0 supports both chip selects.
Ports 1 and 2 implement CS0# only. Defaults to CS0#.
dcsckon:
type: int
description: |
Delay in QMSPI main clocks from CS# assertion to first clock edge.
If not present use hardware default value. Refer to chip documention
for QMSPI input clock frequency.
dckcsoff:
type: int
description: |
Delay in QMSPI main clocks from last clock edge to CS# de-assertion.
If not presetn use hardware default value. Refer to chip documention
for QMSPI input clock frequency.
dldh:
type: int
description: |
Delay in QMSPI main clocks from CS# de-assertion to driving HOLD#
and WP#. If not present use hardware default value. Refer to chip
documention for QMSPI input clock frequency.
dcsda:
type: int
description: |
Delay in QMSPI main clocks from CS# de-assertion to CS# assertion.
If not present use hardware default value. Refer to chip documention
for QMSPI input clock frequency.
cs1-freq:
type: int
description: |
Allows different frequencies for CS#0 and CS1# devices. This applies
to ports implementing CS1#.
tctradj:
type: int
description: |
An optional signed 8-bit value for adjusting the QMSPI control signal
timing tap.
tsckadj:
type: int
description: |
An optional signed 8-bit value for adjusting the QMSPI clock signal
timing tap.

7
samples/drivers/spi_flash/boards/mec172xevb_assy6906.conf Normal file
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@@ -0,0 +1,7 @@
#
# Copyright (c) 2022 Microchip Technology Inc.
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_SPI_NOR=y

42
samples/drivers/spi_flash/boards/mec172xevb_assy6906.overlay Normal file
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@@ -0,0 +1,42 @@
/*
* Copyright (c) 2022 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
aliases {
spi-flash0 = &spi1_cs0_flash;
};
};
&spi0 {
status = "okay";
compatible = "microchip,xec-qmspi-ldma";
clock-frequency = <24000000>;
lines = <4>;
chip-select = <0>;
pinctrl-0 = < &shd_cs0_n_gpio055
&shd_clk_gpio056
&shd_io0_gpio223
&shd_io1_gpio224
&shd_io2_gpio227
&shd_io3_gpio016 >;
pinctrl-names = "default";
spi1_cs0_flash: w25q128@0 {
compatible = "jedec,spi-nor";
/* 134217728 bits = 16 Mbytes */
size = <0x8000000>;
reg = <0>;
spi-max-frequency = <24000000>;
jedec-id = [ef 40 18];
status = "okay";
};
};
&shd_cs0_n_gpio055 {
drive-open-drain;
output-high;
};

24
tests/drivers/spi/spi_loopback/boards/mec172xevb_assy6906.overlay Normal file
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@@ -0,0 +1,24 @@
/*
* Copyright (c) 2022 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
&spi0 {
status = "okay";
compatible = "microchip,xec-qmspi-ldma";
clock-frequency = <12000000>;
lines = <1>;
chip-select = <0>;
slow@0 {
compatible = "test-spi-loopback-slow";
reg = <0>;
spi-max-frequency = <500000>;
};
fast@0 {
compatible = "test-spi-loopback-fast";
reg = <0>;
spi-max-frequency = <16000000>;
};
};