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<h1 id="roadmap">Roadmap</h1>
<p><a href="https://nlnet.nl/project/TwPM/index.html">TwPM project</a> is funded by the
<a href="https://nlnet.nl">NLnet Foundation</a> via the
<a href="https://www.assure.ngi.eu/">NGI ASSURE</a>.</p>
<p><a href="https://3mdeb.com/">3mdeb</a> has proposed to implement the following tasks under
the grant agreement No 957073.</p>
<h2 id="1-public-site-with-documentation">1. Public site with documentation</h2>
<p>All of the documentation produced during this project should be publicly
available to users and developers.</p>
<p>Milestones:</p>
<ul>
<li>create repositories for the project</li>
<li>prepare server and domain name</li>
<li>describe project's purpose and phases</li>
<li>create placeholders for description of deviations from TPM specification,
software stack and documentation changelog that will be updated after each of
the remaining phases</li>
</ul>
<p>State: <a href="../">Done (this website)</a></p>
<h2 id="2-gather-hardware-requirements-and-choose-target-board">2. Gather hardware requirements and choose target board</h2>
<p>TPMs are connected to the mainboard of PC. They have maximum allowed power
consumption and boot time. Based on those requirements and additional factors
like cost, availability and ease of use with open source tools we have to choose
a board for reference implementation.</p>
<p>Milestones:</p>
<ul>
<li>documentation of hardware requirements</li>
<li>analysis and comparison of available boards</li>
<li>establishment of reference board</li>
<li>review and update existing documentation, add entry to changelog</li>
</ul>
<p>State: <a href="../changelog/#2023-04-20">Done</a></p>
<h2 id="3-implement-lpc-protocol-in-fpga">3. Implement LPC protocol in FPGA</h2>
<p>While the newest computers use SPI for connecting TPM devices to the mainboard,
slightly older, but still widely used hardware uses Low Pin Count (LPC)
interface. Implementing this protocol at software level through bit-banging
would require very high speed micro-controllers, which would make the cost and
power consumption unreasonably high. To the best of our knowledge, there are no
MCUs that have LPC controller included as a hardware part of SoC, due to the
fact that LPC is specific to PC only. For these reasons hardware implementation
is required.</p>
<p>Milestones:</p>
<ul>
<li>design and implementation of LPC peripheral in Verilog</li>
<li>simulation of synthesized code</li>
<li>documentation describing connection between designed TPM and mainboard</li>
<li>review and update existing documentation, add entry to changelog</li>
</ul>
<p>State: <a href="../changelog/#2023-04-20">Done</a></p>
<h2 id="4-implement-basic-tpm-registers-in-fpga">4. Implement basic TPM registers in FPGA</h2>
<p>Most of the hardware TPM registers must return result immediately or almost
immediately. MCUs and their communication with FPGA are not fast enough to
acknowledge, parse, prepare response and send it to host in time. Hardware
implementation is required for registers that require fast response.</p>
<p>Milestones:</p>
<ul>
<li>implementation of TPM register space</li>
<li>implementation of finite state machine for changing localities</li>
<li>review and update existing documentation, add entry to changelog</li>
</ul>
<p>State: <a href="../changelog/#2023-05-24">Done</a></p>
<h2 id="5-implement-tpm-command-parsing-and-communication-between-fpga-and-mcu">5. Implement TPM command parsing and communication between FPGA and MCU</h2>
<p>Minimal parsing of commands and responses (limited to just their sizes) must be
done on FPGA side in order to properly set status bits that host can use to
check whether TPM expects more bytes of command or has more bytes of response.
Full command parsing and execution takes place on MCU, so FPGA has to implement
and expose buffer with command sent by host, along with any required metadata
like type of message in the buffer or currently active locality.</p>
<p>Milestones:</p>
<ul>
<li>implementation of FIFO on FPGA</li>
<li>implementation of command machine state</li>
<li>design, implementation and documentation of protocol of communication between
FPGA and MCU</li>
<li>application code for reading data from FIFO, passing parsed commands to the
TPM stack and writing responses back to FIFO</li>
<li>review and update existing documentation, add entry to changelog</li>
</ul>
<p>State: <a href="../changelog/#2024-01-16">Done</a></p>
<h2 id="6-base-tests">6. Base tests</h2>
<p>For testing of the implementation done so far, a subset of tpm2-tools commands
will be used. Only commands that do not depend on Protected Storage, RNG and
Primary Keys Certificates will be tested at this point.</p>
<p>Milestone:</p>
<ul>
<li>test suite: PCR operations (read, extend, reset values, locality protection)</li>
<li>test suite: object creation (primary, ordinary, derived objects of various
types)</li>
<li>test suite: cryptographic support functions (hash, HMAC, encryption, signing)</li>
<li>documentation of results</li>
<li>review and update existing documentation, add entry to changelog</li>
</ul>
<p>State: <a href="../changelog/#2024-01-16">Done</a></p>
<h2 id="7-implement-spi-tpm-protocol">7. Implement SPI TPM protocol</h2>
<p>SPI implementation on MCU may not be feasible because some of the registers must
return proper values immediately. This task consists of repeating all the tasks
that were done on FPGA side for LPC, but this time SPI is used as physical
interface.</p>
<p>Milestones:</p>
<ul>
<li>design and implementation of LPC peripheral in Verilog</li>
<li>simulation of synthesized code</li>
<li>documentation describing connection between designed TPM and mainboard</li>
<li>implementation of TPM register space</li>
<li>review and update existing documentation, add entry to changelog</li>
</ul>
<p>State: <a href="../changelog/#2024-03-14">Done</a></p>
<h2 id="8-explore-the-usage-of-using-simpler-hardware-platform">8. Explore the usage of using simpler hardware platform</h2>
<p>Additionally, we want to explore whether we can meet the TPM specification
requirements using simpler (and cheaper) microcontroller platform (with no FPGA
involved). That may not be feasible due to the hardware limitations, but it
is a great potential opportunity of increasing the adoption of the solution,
so that is why believe it makes sense to try to purse that and publish the
results.</p>
<p>Milestones:</p>
<ul>
<li>explore usage of the solution using simpler hardware platform (with no FPGA)</li>
<li>publish test results to the public documentation website</li>
<li>review and update existing documentation, add entry to changelog</li>
</ul>
<p>State: Done</p>
<h2 id="9-flash-driver-for-tpm-stack">9. Flash driver for TPM stack</h2>
<p>Nonvolatile storage is an integral part of TPM. It allows for saving user- or
vendor-defined data inside TPM, potentially with protection based on state of
TPM (PCR values, authorization sessions). With NVRAM implemented, additional
tests can be performed.</p>
<p>Milestones:</p>
<ul>
<li>flash driver for chosen board (if not available yet or has limited support)</li>
<li>integration of the TPM stack with flash driver</li>
<li>test suite: NV memory (persistent objects and data, vendor certificates)</li>
<li>test suite: attestation and authorization (quote, authorization sessions)</li>
<li>test suite: use in real-world scenario (Fobnail)</li>
<li>review and update existing documentation, add entry to changelog</li>
</ul>
<p>State: In progress</p>
<h2 id="10-unique-identification-and-randomness-source">10. Unique identification and randomness source</h2>
<p>Each TPM has to be uniquely identifiable. This uniqueness is used e.g. to create
primary seeds which are used to derive primary keys for various hierarchies.
Random number generator is also included in this task - unique registers (with
e.g. serial numbers) and RNG engines are usually specific to the given hardware.
FPGA can also be used if any of those isn't available or doesn't have enough
entropy on MCU.</p>
<p>Milestones:</p>
<ul>
<li>find and obtain enough bits of unique data identifying the platform</li>
<li>find and obtain enough bits of entropy for seeding PRNG</li>
<li>test suite: Windows HLK</li>
<li>review and update existing documentation, add entry to changelog</li>
</ul>
<p>State: In progress</p>
<h2 id="11-manufacturing-process">11. Manufacturing process</h2>
<p>Each TPM must be individually manufactured. This consists of committing vendor
certificate for TPM's primary Endorsement Key (EK) to its nonvolatile memory. As
each EK is unique, so is its certificate, and it must be sign by key which chain
of trust is rooted in publicly available vendor's root certificate.</p>
<p>Milestones:</p>
<ul>
<li>create manufacturing process</li>
<li>post the process on the documentation site</li>
<li>create script for automation of manufacturing process</li>
<li>review and update existing documentation, add entry to changelog</li>
</ul>
<p>State: Backlog</p>
<h2 id="12-customizable-configuration">12. Customizable configuration</h2>
<p>Platforms other than the reference one may support different functionalities, or
may have limited performance. To make transition to different hardware easier,
some options should be made configurable. This may include available hash
algorithms in TPM stack, physical interface used (LPC or SPI), presence of
hardware RNG engine, amount of nonvolatile memory.</p>
<p>Milestones:</p>
<ul>
<li>create easy to use build system integrating whole stack</li>
<li>prepare configuration file for whole project</li>
<li>review and update existing documentation, add entry to changelog</li>
</ul>
<p>State: In progress</p>
</article>
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