Files
slimbootloader/Silicon
Stanley Chang 9e18d1a9e4 fix: correct offset and value for disabling SPI prefetching and caching
This commit corrects the SaveAndDisableSpiPrefetchCache by applying the
correct offset (3:2) and value (b'01) to disable Prefetching and Caching.

Additionally, the following improvements were made:

1. Aligned V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS with EDS.

2. Enhanced performance and reliability by switching from MmioAndThenOr32 to
   MmioAndThenOr8.

3. Introduced N_SPI_BCR_SRC (the offset)

4. Removed unused constants: V_SPI_BCR_SRC_PREF_EN_CACHE_EN,
   V_SPI_BCR_SRC_PREF_DIS_CACHE_EN, N_SPI_BCR_SYNC_SS, and B_SPI_BCR_SYNC_SS

Verified with TGL RVP, EHL CRB, and TWL CRB

Discussion: https://groups.io/g/slimbootloader/topic/spi_write_and_read_cycle/113260279
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
2025-06-03 10:41:36 -07:00
..
2025-04-23 12:31:14 +08:00