Commit Graph
1024 Commits
Author SHA1 Message Date
Guo Dong 7e53dc3e70 [TGL] Use MR2 FSP and Microcode for TGL-U (#1186)
MR2 FSP is available so update SBL to use MR2 FSP.
and also use new Microcode required by new FSP
Update platform code on FSP UPDs, especially enable TCC feature.
Update TGL platform version to 1.2 since MR2 released.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2021-06-09 15:51:00 -07:00
Guo Dong 29073e4782 Get RTCM from OS boot media instead IFWI (#1179)
RTCM will sit in OS boot media instead of IFWI image
So update SBL logic to load RTCM from OS boot media.

If the RTCM could not be found, SBL should continue
boot normal OS.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2021-06-09 08:05:56 -07:00
Ong Kok Tong 60f5423552 [EHL] Gpio common lib integration
Integrated EHL GPIO lib into common GPIO lib.

Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
2021-06-04 11:16:39 -07:00
Guo Dong 8658d66c2b [TGL] Set PayloadId to "AUTO" by default
Update PayloadId to "AUTO" to align with other platforms to
have consistent behavior.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2021-06-04 11:14:34 -07:00
leanshen 474666bc6f [EHL] Update the EHL BoardPkg version to 1.1
Update EHL BoardPkg version to 1.1 to allign with current
software package version:
PROJ_MAJOR_VER -> 1 (Production Release candidate)
PROJ_MINOR_VER -> 1 (2nd revision of PV release)

Signed-off-by: LeanSheng <lean.sheng.tan@intel.com>
2021-06-02 20:33:49 -07:00
Tan Lean Sheng 218cdbcd2c [EHL] Remove FSP UPD files from EHL Silicon package (#1181)
Remove the old FSP UPD files from EHL folder, let SBL
fetch from FSP github during build time.

Signed-off-by: LeanSheng <lean.sheng.tan@intel.com>
2021-06-02 20:33:10 -07:00
Guo Dong 99c9617db0 [TGL] Update PayloadId settings in dlt files
Update the comments and actual setting in dlt files to
make them in alignment.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2021-06-02 15:32:34 -07:00
Guo Dong a8bd06f8f2 [TGL] reset when TPM startup failure on S3
As per PC Client spec, SRTM should perform a host platform reset
when TPM startup failure on S3

Signed-off-by: Guo Dong <guo.dong@intel.com>
2021-06-02 15:32:34 -07:00
Guo Dong f7401ea952 [TGL] Minor code clean up
Remove TGL-H GPIO definition and program.
Use R_ACPI_IO_SMI_STS instead of "R_ACPI_IO_SMI_EN + 4"
Set PCIE region len to 0x10000000 instead of 0x20000000
Remove data dumping for PSD
Fix other typo

Signed-off-by: Guo Dong <guo.dong@intel.com>
2021-06-02 15:32:34 -07:00
Sindhura Grandhi 66a5487148 Add TccErrorLog feature in Tcc mode
Make Error logging capability configurable under
Tcc mode. This will be consumed later.

Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
2021-06-02 11:37:50 -07:00
jinjhuli 46e90b83fd [EHL] Clone FSP and Microcode from open source repo
1. Clone FSP from
https://github.com/intel/FSP/tree/master/ElkhartLakeFspBinPkg
2. Clone microcode from
https://github.com/tianocore/edk2-non-osi/tree/master/Silicon/Intel/ElkhartlakeSiliconBinPkg

Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
2021-05-28 15:13:54 -07:00
Ong Kok Tong 41a7ab5aee [EHL] BiProchot changes for Fusa
Change BiProcHot value to 0 for Fusa sku as per
requested from PMC team to fulfill Fusa requirement

Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
2021-05-28 15:13:18 -07:00
Maurice Ma 97124b133f Patch FSP-T UPD microcode base
When redundant partition is enabled, the FSP-T microcode base UPD
always points to the microcode region in 1st partition. Instead,
it should points to the microcode rgion in its own partition. This
patch fixed this issue.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-05-28 15:07:15 -07:00
Maurice Ma c44a7f3146 [TGL] Skip PCH UART init in later stages
When PCH UART is used as debug UART, the later stage code should
not do re-initializaiton. This patch will skip PCH UART GPIO
reprogramming and FSP-S UART re-initialization.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-05-28 11:57:43 -07:00
Talamudupula 36ff6c2b6e Disable debug prints before serial init
Set debug print error level to 0 by default.
This will prevent code to print debug messages via
UART, if it is not yet initielized.

After PostTempRamInit, when platforms did UartInit,
we can set it back to default PCD value.

Signed-off-by: Talamudupula <stalamudupula@gmail.com>
2021-05-27 18:24:27 -07:00
Maurice Ma 9480958ee8 [TGL] Fix TGL PCH Debug UART issue
On TGL platform, if change current DEBUG UART to PCH UART, there
is no output from SBL at all.

This patch fixed this issue by:
  - Skip UART init in FSP-T and let SBL do UART init itself.
  - Disable any debug output before UART init is done.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-05-27 14:51:01 -07:00
Guo Dong 383a5b4e23 [TGL] Fix PlatformId override issue
If the PlatformId is already set by stitch data, the platform code
should skip platform settings to avoid PlatformID override.
This patch adds the PlatformId check in platform code.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2021-05-27 09:33:04 -07:00
James Gutbub 2471cdddeb [CFL] Resolve StitchIfwi.py issue
Recent addition of '-op' argument may have
unintentionally created an issue by using an
unassigned variable 'work_dir' where the
intended variable to be used may have been
'stitch_dir'. This patch resolves the issue
and able to successfully stitch an IFWI once
again.

Signed-off-by: James Gutbub <james.gutbub@intel.com>
2021-05-26 14:00:22 -07:00
Vincent Chen 8bb52daaca [QEMU] Fix compiler error for NOOPT build in Windows
- fix __aullshr link error due to compiler intrinsics functions
  for NOOPT build in Windows
- adjust Stage1A/TopSwap/OsLoader FD size for NOOPT target
- adjust Stage2 size for NOOPT target when DEBUG FSP is used

Signed-off-by: Vincent Chen <vincent.chen@intel.com>
2021-05-25 21:20:38 -07:00
Vincent Chen 6275eb6eb7 Fix PCI address check in CsmeFwUpdate (#1165)
The PCI address consumed by CSME FW update library is in
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS format.
- when register offset is  < 0x100, it is :    bbddffrr
- when register offset is >= 0x100, it is : rrrbbddff00
Consider the two different cases in CsmePciReadBuffer()

Signed-off-by: Vincent Chen <vincent.chen@intel.com>
2021-05-25 13:40:57 -07:00
Aiden Park 6d1734a6ec [FWU] Fix a pointer misusing in capsule name
This will fix an invalid pointer operation while copying capsule filename
from capsule info config data to a unicode buffer.

Signed-off-by: Aiden Park <aiden.park@intel.com>
2021-05-25 11:14:06 -07:00
Aiden Park 236a800284 Support ELF32/64 format payloads regardless of operation mode
This allows to load and execute ELF32 or ELF64 format payloads
regardless of Ia32 or X64 SBL operation modes.

Signed-off-by: Aiden Park <aiden.park@intel.com>
2021-05-24 09:04:14 -07:00
Stanley Chang 3a02cd0f45 Add EXT FS check in initialization
This patch runs basic check during EXT FS initialization
by opening root directory to ensure superblock been
validated.

Signed-off-by: Stanley Chang <stanley.chang@intel.com>
2021-05-21 20:11:53 -07:00
stalamudupula 1320881dd9 [CFL][CML][CML-V][EHL][TGL] Use common PchSbiAccessLib (#1161)
Use the newly added PchSbiAccessLib in common package,
for all the current platfroms. Platform specific PchSbi Lib
is removed.

Signed-off-by: Talamudupula <stalamudupula@gmail.com>
2021-05-20 11:24:26 -07:00
Subash Lakkimsetti dfd4444a33 Generate signed slimboot binary to output path
Currently final IFWI gets generated output path.
Copy the signed slimboot binary to out path.
Added option for outpath.

Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
2021-05-20 11:13:36 -07:00