Explicit cast added to resolve a build error with VS2022 caused by
bitwise ORing different enum types.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
BTL-S Hybrid shares its CPUID with ADL-S, but 12P parts introduce a
new CPUID. Added support to GetCpuSkuInfo() to detect this new ID.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
When changing a boot option from a non-RAW type to RAW, the boot command
does not set the valid field of the LbaImage.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Set SMI lock bit at ReadyToBoot for Osloader.
Test info: Confirmed SMI_LOCK setting in OSLoader Ubuntu with
devmem2 MMIO read.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
edk2-stable202411 based UEFI payload requires Smm Rebase without setting
SMRR. Set this new auto mode for compatibility with this and newer uefi
payload.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
CfgDataTool de-dupes config data in some circumstances when using the
"merge" command. In such a case, the CDATA_FLAG_TYPE_REFER flag is set
in the header, and a special REFERENCE_CFG_DATA struct is added after the
conditions that points to the reference Config Data. ConfigDataLib's
BuildConfigData() triggers a config data corruption when handling these
that needed to be fixed. Instead, the setup payload will expand these
de-duped configs using the reference data so they can be modified
independently. This will cause an increase in Config Data size when
saving data from setup in these cases.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Mismatch between YAML config type and value was causing setup to crash.
Handle it gracefully and print an error instead.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Fix loading and saving issues with SblSetup payload when Config Data
layout differs from ConfigDataDef.json file. ConfigDataDef.json used
by setup payload has config data order based on defaults, while actual
binary config values retrieved from ConfigLib can have order changes
triggered by board deltas.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
FSP 2.4 introduces the possibility of FSP built for x64 architecture.
This adds support for x64 FSP calling conventions based on the header x64
support attribute. Support for x64 FSP-T requires entering long mode
prior to FSP-T execution.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
FSP 2.4 with MultiPhase support expects FSP UPD buffer to stay accessible
after CallFspMemoryInit() returns, so FSP must be allocated from the heap
instead of stack.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Prevent GenContainer.py from creating monolithic signed containers with
no component authorization data. Prevent ContainerLib from
authenticating such containers when verified boot is enabled.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
FSP no longer supports value of 4 (Auto) for DmiAspm. Setting this breaks
Package C10 and S0ix. Fallback to YAML config value (currently 2 for "L1").
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Latest ipp-crytpo code is FIPS compliant. Need to add it as a submodule
to maintain FIPS compliance. This requires adding each ASM optimized
implementation as a separate .inf file and selecting at the platform
level. Old IppCryptoLib instance needs to be kept for backwards
compatibility.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Some silicon requires longer than provided for all APs to enter the wakeup
routine. This change makes this platform configurable. The default wait
time is none and can be increased for platforms with higher core count Si.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Adding a 3ms delay before any EC Read from ACPI resolves the windows boot
delay. Still following up on root cause.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Update the GfxInfo HOB FrameBufferBase after the IGD BAR is reallocated
during PCI enumeration. This resolves an issue where video output doesn't
work for the UEFI payload with newer FSP versions.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
DebugAgentLib was using its own IDT Entry structure definition that
didn't adjust for x64. Removed this definition and switched to built
in definition from ProcessorBind.h which does adjust for architecture
correctly.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
When no auth parameter is specified on the command line, gen_layout
chooses auth type based on provided key, but this does not get correctly
applied to the monolithic signing component because of an order of
operations issue.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
If ResetVector GDT is different from that loaded in Stage1A SecStartup()
then segment selectors need to be reloaded after GDT is updated.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Python imp module is removed in 3.12+ and will cause a build error.
Replace with importlib.machinery.SourceFileLoader.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Adding new Board Config item REMAP_STAGE1B to control remapping Stage1B
into permanent memory after FSP-M. Decouple this from ENABLE_FAST_BOOT
and STAGE1B_XIP. This makes it simpler to enable this remap when the
slight performance boost may be needed, and leave it disabled by default.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
The SBL logo is verified as part of Stage2 verification, so untrusted
logos won't be parsed, but it's still good to prevent dereferencing BMP
header pointers that may fall outside of BMP file.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
As part of ITE8659 SIO init, HwMon device is enabled, but eSPI decode was
not enabled for the IO address range.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
When 64bit MMIO above 4GB is enabled, ACPI resource descriptor needs
to be filled in to describe it.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
GetContainerHeaderSize() parses header component entries to find the
offset of the end of the last component entry and checks this against
ContainerHdr->DataOffset. However, there is a valid case where this can
exactly equal to ContainerHdr->DataOffset, when the component alignment is
small enough and there is no component auth data (AuthType is none). This
check is changed to fail on greater than instead of greater or equal to
cover this case.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
When PcdFlashSize is > 16MB, the corresponding memory map entry will be
incorrect since on ADL/RPL only the top 16MB of flash is mapped into memory
by the PCH.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
FuSa Configuration YAML file introduced some description typos and display
issues in the Configuration Editor.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
FuSa feature delta file will be part of RaptorlakeBoardPkg for RPL-P when
it is upstreamed to avoid confusion.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
- MC and CMF Parity combined into one FSP UPD.
- Added SBL Config items for IehMode, TCSS D3Hot and D3Cold, CPU PCIe
Power gating, VccSt, TCSS Cstate limit. These are all needed for the FuSa
specific dlt file. ADL-S dlt files updated so D3Hot and VccSt defaults are
unchanged, since these defaults were previously set by PCH sku.
- FuSa diagnostic mode PCD to track Diagnostic mode across stages. Crash
Log Data PCD will not be used and has been removed.
- GSPI example driver header file added.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Added Null template for FusaConfigLib. Platforms supporting FuSa should
follow this template for enabling FuSa configuration prior to FSP-M and
FSP-S.
Added ADL/RPL CfgData fields for FuSa according to SBL FuSa software
requirements, and dlt file for enabling FuSa and related configuration.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
New CrashLog support design is for FSP to collect CrashLog info and report
in HOB. Bootloader responsibility is just to populate ACPI BERT with FSP
collected CrashLog Data now. That way bootloader has no Silicon code.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
The PCH decodes MMIO accesses to the top of 4GB to SPI flash for a maximum
window size of 16MB. For SBL images larger than 16MB, this PostTempRamInit
hook was causing the MTRR to overlap with NEM stack set up by FSP-T,
causing a hang.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
On platforms where only serial console input is enabled, enabling
source debug will lead to an infinite loop in ConsoleRead(). Newer
compilers detect this and generate a build error.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Re-scanning PCI devices to find NVME controllers was adding an additional
~20ms to the end of Stage 2. Moving this to the existing PCI scan that
is part of PCI enumeration saves this time. However, this
EfiPciBeforeResourceCollection phase was not actually getting called and
needed to be added.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
When PcdVtdEnabled or MemCfgData->VtdDisable were disabled,
Fspmcfg->VtdDisable was being left at default value.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
RPL-S FSP UPD was updated so PchTsnEnable is now a 2-byte array with a
separate byte for each port. This is now different from the ADL platforms
and needs to be included selectively at build time.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
PatchCheck.py currently checks for files without terminating newlines
but takes no action. This change will report this as a code format error.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
The RPL CrashLog platform implementation has changed to use a PCD to store
the crashlog data address so this definition is no longer needed. The
PCD definition for the buffer address is added instead.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
This fix should apply to ADL-P also. For now we will avoid using #if's here
and address any ADL-P issues that come up.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
PR #1760 mistakenly included a debug change to increase the default debug
print level. Reverting that one change.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
FSP UPD FuSa toggles will be set based on new config data fields where
applicable or to predefined values when called for by the FuSa spec.
This requires setting PcdFusaSupport at build time in case platform FSP
doesn't support FuSa.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
FspsUpdUpdateLIb was not enabling FspsUpd->FspsConfig.L2QosEnumerationEn
based on PLATFORM_ADLS, which is no longer used. L2QosEnumerationEn is
present in ADL-P,S,PS, and RPL-S,P FSP UPD, just not ADL-N, so need to
prevent compiling this code for that platform only.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
RPL-P and ADL-P RVPs are essentially identical except for BoardID FRU.
Both need to work with SBL with RPL-P Silicon. To avoid duplicating
config data, this change will treat both as the same board.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
FSP-S UPD format for THC port assignment was updated, but PEP logic
was using the old format, and causing the PEP constraint to always be
enabled. This issue didn't seem to be causing a problem, but resulted
in noncompliant low power idle constraints.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Previous setting of SW-first CM mode was causing a hang during S3/S4 entry. Likely this setting requires additional ACPI/driver support which is missing.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Remove OS version check in PEPD _STA method. This is a change to the intelpep.sys ASL device (PEPD) for low power idle support. Previously, _STA would always return present/enabled for Win10 even if S0ix config flag was disabled. Changed version always returns status based on S0ix flag. Without this workaround, S4 resume was failing on ADL-N/P/PS.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Bejean Mosher