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1107 Commits

Author SHA1 Message Date
Michał Żygowski
5bf8ea2d46 Platform/AlderlakeBoardPkg/BoardConfigOdroidH4.py: Use PKCS v1.5 signatures for build reproducibility 
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2025-08-05 12:31:08 +02:00
Michał Żygowski
efc9e0cdd9 Platform/CommonBoardPkg/Logo/Logo.bmp: Change logo to Dasharo 
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2025-08-04 16:20:19 +02:00
Michał Żygowski
bf982854da Platform/AlderlakeBoardPkg/BoardConfigOdroidH4.py: Set project version to 0.9.0 
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2025-08-04 16:07:39 +02:00
Michał Żygowski
44387c3cc4 Platform/AlderlakeBoardPkg/Library/Stage2BoardInitLib/SmbiosInit.c: Customize SMBIOS 
Customize SMBIOS to match the Dasharo and original FW SMBIOS.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2025-08-04 16:07:39 +02:00
Michał Żygowski
f496db457c Platform/CommonBoardPkg/CfgData/CfgData_Platform.yaml: Increase PlatfornName length to 16 
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2025-08-04 16:07:39 +02:00
Michał Żygowski
5cf158b7e8 Add ODROID H4 support 
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2025-08-04 16:07:38 +02:00
Guo Dong
c7f0e5e1a1 Enhance GPIO data convert Tool 
GpioV2DataConvert.py tool assumes the data value defined in .h file
using decimal format. This enhancement adds hex format support.

Signed-off-by: Guo Dong <guo.dong@intel.com>
 2025-07-16 20:03:53 -07:00
Bejean Mosher
d888673acd fix: [ADL/RPL/BTL] Build error with VS2022 
Explicit cast added to resolve a build error with VS2022 caused by
bitwise ORing different enum types.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
 2025-07-11 12:08:54 -05:00
Bejean Mosher
be0cf0bf32 fix: [BTLS] 12P CPUID detection support 
BTL-S Hybrid shares its CPUID with ADL-S, but 12P parts introduce a
new CPUID. Added support to GetCpuSkuInfo() to detect this new ID.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
 2025-07-02 14:24:38 -07:00
Randy
52edc3c42a feat: [ARL] MR1 release 
ARLUH FSP:0D00E610
 ARLS  FSP:0D00E520
 Microcode:ArrowLake/m_80_b0650_0000000a.pdb
 Microcode:ArrowLake/m_82_c0662_00000118.pdb
 VBT update to 1062.
 Update SBL version to 1.1

Signed-off-by: Randy <randy.lin@intel.com>
 2025-07-02 10:00:35 -07:00
Randy
6e4a8ff8b4 feat: [RPL] Enable HdaAudio pci device 
Found the audio PCI 1F03 device is missing.

Signed-off-by: Randy <randy.lin@intel.com>
 2025-06-30 06:27:59 -07:00
Vincent Chen
2ac63f0f35 [MTL] Update for MR3 
- FSP: Edge Platforms MTL-UH_MTL-PS MR3 (0D.00.E6.10)
- Microcode: m_e6_a06a4_00000025
- VBT: 261
- platform version: SB_MTLP-1.3

Signed-off-by: Vincent Chen <vincent.chen@intel.com>
 2025-06-24 08:28:30 -07:00
Randy
15eda7dfb0 feat: ADL-N/ASL IPU 2025.3 community update 
Fsp sync  to BIOS version 6114_00
Add STAGE2_SIZE.

Signed-off-by: Randy <randy.lin@intel.com>
 2025-06-23 21:38:29 -07:00
ramesh chandra perni
8f66758c32 feat: [AZB] Updated Hash for Microcode/FSP and SBL Version AZB IPU 25.4 
Updated FSP and Microcode Hash. Update the AZB SBL version to 1.6 for
IPU 25.4

Signed-off-by: ramesh chandra perni <ramesh.chandra.perni@intel.com>
 2025-06-20 10:53:44 +08:00
samihahkasim
d14c8c1ff1 [RPLPS] Update MR2 Release 
BIOS version is IoT RPL-PS MR1 (5276_01) FSP
FSP version is 0C01EC40
platform version is 1.1
Microcode Files are: ['m_e0_b06a2_00004129.pdb', 'm_80_906a3_00000435.pdb']

Signed-off-by: samihahkasim <samihah.kasim@intel.com>
 2025-06-19 08:58:03 +08:00
Stanley Chang
052426e9c9 fix: [ARL] Remove dependency on SblOpen folder for stitching 
This commit addresses the issue of hard dependency on the SblOpen folder,
allowing stitching to proceed without it.

Signed-off-by: Stanley Chang <stanley.chang@intel.com>
 2025-06-16 09:56:21 +08:00
Stanley Chang
8907d70d80 fix: [ARL] Correct PchPcieClkSrcUsage for S02 Board 
This commit enables the S02 board to successfully detect the M.2 disk on PCH SSD2.

Signed-off-by: Stanley Chang <stanley.chang@intel.com>
 2025-06-11 14:39:12 +08:00
Sachin Kamat
089072b47b fix: [IDV] Update GPIO config script 
When GPIO skip is enabled, hide the other properties in ConfigEditor
tool.

Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
 2025-06-09 20:08:45 -07:00
Perni
d81d535c59 ICXD:Set SMI lock bit at ReadyToBoot for Osloader. 
Test info: Confirmed SMI_LOCK setting in OSLoader shell

Signed-off-by: Perni <ramesh.chandra.perni@intel.com>
 2025-05-28 08:23:21 -07:00
samihahkasim
751f695d5b fix: [TGL] Set SMI lock bit for Osloader 
Set SMI lock bit at ReadyToBoot for Osloader

Signed-off-by: samihahkasim <samihah.kasim@intel.com>
 2025-05-22 19:29:33 +08:00
Vincent Chen
05e821e518 fix: [ARL][MTL] Fix Coverity issues 
ARL
- Execute32BitCode: CWE-476 Deference null return value

MTL
- EarlyPlatformDataCheck: CWE-569 Operands don't affect result
- InitializeSmbiosInfo: CWE-476 Dereference null return value
- PlatformUpdateAcpiGnvs: CWE-563 Unused value

Signed-off-by: Vincent Chen <vincent.chen@intel.com>
 2025-05-21 10:12:07 -07:00
Vincent Chen
2db02643c3 fix: [MTL] Set SMI Lock bit for OsLoader 
Set SMI Lock bit at ReadyToBoot for OsLoader before jumping to OS

Signed-off-by: Vincent Chen <vincent.chen@intel.com>
 2025-05-21 09:56:36 -07:00
Randy
10a487573c fix: [EHL] Set SMI Lock bit for OsLoader 
Set SMI Lock bit at ReadyToBoot for OsLoader before jumping to OS

verified on EHL CRB.

Signed-off-by: Randy <randy.lin@intel.com>
 2025-05-21 09:56:15 -07:00
Kevin Tsai
c2ebb3cbb1 fix: [ARL] Set SMI lock bit for Osloader 
Set SMI lock bit at ReadyToBoot for Osloader

Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
 2025-05-20 08:04:54 -07:00
Bejean Mosher
b72f0d3c80 [ADL/RPL/BTL/TWL] Set SMI lock bit for Osloader 
Set SMI lock bit at ReadyToBoot for Osloader.

Test info: Confirmed SMI_LOCK setting in OSLoader Ubuntu with
devmem2 MMIO read.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
 2025-05-19 15:50:40 -04:00