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Add ODROID H4 support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Michał Żygowski
177
Platform/AlderlakeBoardPkg/BoardConfigOdroidH4.py
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177
Platform/AlderlakeBoardPkg/BoardConfigOdroidH4.py
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# @file
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# This file is used to provide board specific image information.
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#
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# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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# Import Modules
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#
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import os
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import sys
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tool_dir = os.path.realpath(os.path.join(os.path.dirname (os.path.realpath(__file__)), '..', 'AlderlakeBoardPkg'))
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sys.path.append (tool_dir)
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import BoardConfig as AlderlakeBoardConfig
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class Board(AlderlakeBoardConfig.Board):
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def __init__(self, *args, **kwargs):
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super(Board, self).__init__(*args, **kwargs)
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self.VERINFO_IMAGE_ID = 'SB_ADLN'
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self.BOARD_NAME = 'odroid_h4'
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self._EXTRA_INC_PATH = ['Silicon/AlderlakePkg/Adln/Include']
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self._FSP_PATH_NAME = 'Silicon/AlderlakePkg/Adln/FspBin'
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self.FSP_IMAGE_ID = '$TWLFSP$'
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self.MICROCODE_INF_FILE = 'Silicon/AlderlakePkg/Microcode/Microcode.inf'
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self.ACPI_TABLE_INF_FILE = 'Platform/AlderlakeBoardPkg/AcpiTables/AcpiTablesN.inf'
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self._LP_SUPPORT = True
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self._N_SUPPORT = True
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self.PCI_EXPRESS_BASE = 0xC0000000
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self.PCI_IO_BASE = 0x00002000
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self.PCI_MEM32_BASE = 0x80000000
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self.ACPI_PM_TIMER_BASE = 0x1808
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self.FLASH_LAYOUT_START = 0x100000000 # 4GB Top
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self.FLASH_BASE_SIZE = 0x01000000 # 16MB
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self.FLASH_BASE_ADDRESS = (self.FLASH_LAYOUT_START - self.FLASH_BASE_SIZE)
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self.LOADER_ACPI_RECLAIM_MEM_SIZE = 0x000090000
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self.HAVE_FIT_TABLE = 1
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self.HAVE_VBT_BIN = 1
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self.HAVE_VERIFIED_BOOT = 1
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self.HAVE_MEASURED_BOOT = 1
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self.HAVE_FLASH_MAP = 1
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self.HAVE_ACPI_TABLE = 1
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self.HAVE_PSD_TABLE = 1
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self.ENABLE_SPLASH = 1
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self.ENABLE_FRAMEBUFFER_INIT = 1
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self.ENABLE_VTD = 1
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# To enable source debug, set 1 to self.ENABLE_SOURCE_DEBUG
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self.ENABLE_SOURCE_DEBUG = 0
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# If ENABLE_SOURCE_DEBUG is disabled, SKIP_STAGE1A_SOURCE_DEBUG will be ignored
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self.SKIP_STAGE1A_SOURCE_DEBUG = 1
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self.ENABLE_PCIE_PM = 1
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# 0: Disable 1: Enable 2: Auto (disable for UEFI payload, enable for others)
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self.ENABLE_SMM_REBASE = 2
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# 0 - PCH UART0, 1 - PCH UART1, 2 - PCH UART2, 0xFF - EC UART 0x3F8
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self.DEBUG_PORT_NUMBER = 0xFF
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self.BUILD_CSME_UPDATE_DRIVER = 0
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self.STAGE1A_XIP = 1
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self.STAGE1B_XIP = 1
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self.STAGE2_XIP = 0
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self.STAGE1A_SIZE = 0x0001B000
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self.STAGE1_STACK_SIZE = 0x00002000
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self.STAGE1_DATA_SIZE = 0x00014000
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self.FSP_M_STACK_TOP = 0xFEF7FF00
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self.STAGE1B_SIZE = 0x00100000
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self.STAGE2_SIZE = 0x000C2000
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self.STAGE2_FD_BASE = 0x01000000
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self.STAGE2_FD_SIZE = 0x001F0000
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self.PAYLOAD_SIZE = 0x00030000
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self.EPAYLOAD_SIZE = 0x00230000
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self.OS_LOADER_FD_SIZE = 0x0005B000
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self.OS_LOADER_FD_NUMBLK = self.OS_LOADER_FD_SIZE // self.FLASH_BLOCK_SIZE
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self.ENABLE_FAST_BOOT = 0
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if self.ENABLE_FAST_BOOT:
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self.ENABLE_SPLASH = 0
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self.ENABLE_FRAMEBUFFER_INIT = 0
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self.RELEASE_MODE = 1
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self.HAVE_VERIFIED_BOOT = 0
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self.HAVE_MEASURED_BOOT = 0
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self.VERIFIED_BOOT_HASH_MASK = 0
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if self.RELEASE_MODE and self.ENABLE_FAST_BOOT:
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self.STAGE1A_SIZE = 0x00016000
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self.STAGE1B_SIZE = 0x000E0000
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self.STAGE2_SIZE = 0x000C0000
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self.STAGE2_FD_SIZE = 0x000F0000
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self.PAYLOAD_SIZE = 0x00024000
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self.PLD_HEAP_SIZE = 0x09000000
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self.UEFI_VARIABLE_SIZE = 0x1000
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if len(self._PAYLOAD_NAME.split(';')) > 1:
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self.UEFI_VARIABLE_SIZE = 0x00040000
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self.UCODE_SIZE = 0x000EC000
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self.MRCDATA_SIZE = 0x00010000
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self.CFGDATA_SIZE = 0x00004000
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self.KEYHASH_SIZE = 0x00001000
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self.VARIABLE_SIZE = 0x00002000
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self.SBLRSVD_SIZE = 0x00001000
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self.FWUPDATE_SIZE = 0x00020000 if self.ENABLE_FWU else 0
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self.SIIPFW_SIZE = 0x1000
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# Declaring UCODE_SLOT_SIZE populates the uCode region with as many
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# uCode slots as possible, even if there aren't enough uCode patches
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# to fill each slot. This can have a slight performance impact on SBL,
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# as it tries to load dummy uCode patches.
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self.UCODE_SLOT_SIZE = 0x3B000
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# If ENABLE_SBL_RESILIENCY is 1, BiosRedAssistance FIT strap setting
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# needs to be manually changed to Enabled and TopSwapOverride
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# flash setting needs to be manually changed to 4MB in stitch config
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self.ENABLE_SBL_RESILIENCY = 0
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self.BUILD_IDENTICAL_TS = 0
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if self.ENABLE_SBL_RESILIENCY:
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self.BUILD_IDENTICAL_TS = 1
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if self.BUILD_IDENTICAL_TS:
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self.TOP_SWAP_SIZE = 0x400000
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self.REDUNDANT_SIZE = self.STAGE2_SIZE + self.FWUPDATE_SIZE + self.CFGDATA_SIZE + \
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self.KEYHASH_SIZE
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else:
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self.TOP_SWAP_SIZE = 0x80000
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self.REDUNDANT_SIZE = self.UCODE_SIZE + self.STAGE2_SIZE + self.STAGE1B_SIZE + \
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self.FWUPDATE_SIZE + self.CFGDATA_SIZE + self.KEYHASH_SIZE
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self.ENABLE_TCC = 0
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self.ENABLE_TSN = 0
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if self.ENABLE_TSN:
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self.TMAC_SIZE = 0x00001000
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self.SIIPFW_SIZE += self.TMAC_SIZE
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self.NON_REDUNDANT_SIZE = 0x33F000 + self.SIIPFW_SIZE
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self.NON_VOLATILE_SIZE = 0x001000
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self.SLIMBOOTLOADER_SIZE = 0xA00000
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self.PLD_HEAP_SIZE = 0x09000000
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self.PLD_STACK_SIZE = 0x00020000
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self.PLD_RSVD_MEM_SIZE = 0x00500000
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self.KM_SIZE = 0x00000400
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self.BPM_SIZE = 0x00000600
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self.ACM_SIZE = 0x00040000 + self.KM_SIZE + self.BPM_SIZE
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# adjust ACM_SIZE to meet 256KB alignment (to align 256KB ACM size)
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if self.ACM_SIZE > 0:
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acm_top = self.FLASH_LAYOUT_START - self.STAGE1A_SIZE
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acm_btm = acm_top - self.ACM_SIZE
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acm_btm = (acm_btm & 0xFFFC0000)
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self.ACM_SIZE = acm_top - acm_btm
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self.LOADER_RSVD_MEM_SIZE = 0xC00000
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# If mulitple VBT table support is required, list them as:
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# {VbtImageId1 : VbtFileName1, VbtImageId2 : VbtFileName2, ...}
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# VbtImageId is ID to identify a VBT image. It is a UINT32 number to match
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# the ImageId field in the VBT container.
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# VbtFileName is the VBT file name. It needs to be located under platform
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# VbtBin folder.
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self._MULTI_VBT_FILE = {3:'VbtAdlnOdroidH4.dat'}
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self.CFG_DATABASE_SIZE = self.CFGDATA_SIZE
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self._generated_cfg_file_prefix = 'Autogen_'
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self._CFGDATA_DEF_FILE = 'CfgDataDefAdln.yaml'
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self._CFGDATA_INT_FILE = []
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self._CFGDATA_EXT_FILE = [self._generated_cfg_file_prefix + 'CfgDataExt_Odroid_H4.dlt']
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386
Platform/AlderlakeBoardPkg/CfgData/CfgDataExt_Odroid_H4.dlt
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386
Platform/AlderlakeBoardPkg/CfgData/CfgDataExt_Odroid_H4.dlt
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#/** @file
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#
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# Platform Configuration Delta File.
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#
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# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#
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#**/
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PLATFORMID_CFG_DATA.PlatformId | 0x000C
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PLAT_NAME_CFG_DATA.PlatformName | 'ODROIDH4'
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GEN_CFG_DATA.PayloadId | 'UEFI'
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# FIPS mode enablement feature
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FEATURES_CFG_DATA.Features.MeFipsMode | 0x0
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# S0ix feature
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FEATURES_CFG_DATA.Features.S0ix | 0x0
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# DTT feature
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FEATURES_CFG_DATA.Features.DTT | 0x0
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#
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#Delta configuration for DDR
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#
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MEMORY_CFG_DATA.SpdAddressTable | { 0xA4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
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MEMORY_CFG_DATA.SpdDataSel000 | 0
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MEMORY_CFG_DATA.SpdDataSel010 | 0
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MEMORY_CFG_DATA.SpdDataSel020 | 0
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MEMORY_CFG_DATA.SpdDataSel030 | 0
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MEMORY_CFG_DATA.SpdDataSel100 | 0
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MEMORY_CFG_DATA.SpdDataSel101 | 0
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MEMORY_CFG_DATA.SpdDataSel110 | 0
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MEMORY_CFG_DATA.SpdDataSel120 | 0
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MEMORY_CFG_DATA.SpdDataSel130 | 0
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MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch0 | { 0, 0}
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MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch1 | { 0, 0}
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MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch2 | { 0, 0}
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MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch3 | { 0, 0}
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MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch0 | { 0, 0}
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MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch1 | { 0, 0}
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MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch2 | { 0, 0}
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MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch3 | { 0, 0}
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MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch0 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
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MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch1 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
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MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch2 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
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MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch3 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
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MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch0 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
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MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch1 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
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MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch2 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
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MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch3 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
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MEMORY_CFG_DATA.DqPinsInterleaved | 0x0
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MEMORY_CFG_DATA.ECT | 0x1
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MEMORY_CFG_DATA.TsegSize | 0x1000000
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MEMORY_CFG_DATA.UserBd | 0x0
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MEMORY_CFG_DATA.IpuLaneUsed | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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MEMORY_CFG_DATA.CsiSpeed | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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MEMORY_CFG_DATA.CpuPcieRpClockReqMsgEnable | {0x0, 0x0, 0x0}
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MEMORY_CFG_DATA.CpuPcieRpPcieSpeed | {0x00, 0x00, 0x00, 0x00}
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MEMORY_CFG_DATA.EnableC6Dram | 0x1
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MEMORY_CFG_DATA.BootFrequency | 0x2
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MEMORY_CFG_DATA.CpuPcieRpEnableMask | 0x0
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MEMORY_CFG_DATA.FClkFrequency | 0x0
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MEMORY_CFG_DATA.PcieClkSrcUsage | { 0x08, 0x02, 0x03, 0x06, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
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MEMORY_CFG_DATA.PcieClkSrcClkReq | { 0x00, 0x01, 0x02, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
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MEMORY_CFG_DATA.PcieRpEnableMask | 0x14C
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MEMORY_CFG_DATA.PchHdaAudioLinkDmicEnable | {0x0, 0x0}
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MEMORY_CFG_DATA.PchHdaAudioLinkSndwEnable | {0x00, 0x00, 0x00, 0x00}
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MEMORY_CFG_DATA.TcssItbtPcie0En | 0x0
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MEMORY_CFG_DATA.TcssItbtPcie1En | 0x0
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MEMORY_CFG_DATA.TcssItbtPcie2En | 0x0
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MEMORY_CFG_DATA.TcssItbtPcie3En | 0x0
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MEMORY_CFG_DATA.TcssXhciEn | 0x0
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MEMORY_CFG_DATA.TcssDma0En | 0x0
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MEMORY_CFG_DATA.TcssDma1En | 0x0
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MEMORY_CFG_DATA.UsbTcPortEnPreMem | 0x0
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MEMORY_CFG_DATA.CpuDmiHwEqGen3CoeffListCm | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
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MEMORY_CFG_DATA.BdatEnable | 0x0
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MEMORY_CFG_DATA.Ibecc | 0x1
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MEMORY_CFG_DATA.PchHdaAudioLinkHdaEnable | 0x1
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MEMORY_CFG_DATA.PchHdaEnable | 0x1
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MEMORY_CFG_DATA.PchHdaDspEnable | 0x0
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MEMORY_CFG_DATA.CpuDmiHwEqGen3CoeffListCp | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
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MEMORY_CFG_DATA.CpuDmiHwEqGen4CoeffListCm | { 0x00, 0x0E, 0x0A, 0x07, 0x07, 0x07, 0x07, 0x07 }
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MEMORY_CFG_DATA.CpuDmiHwEqGen4CoeffListCp | { 0x00, 0x07, 0x06, 0x07, 0x07, 0x07, 0x07, 0x07 }
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MEMORY_CFG_DATA.WdtDisableAndLock | 0
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MEMORY_CFG_DATA.FirstDimmBitMaskEcc | 0x0
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MEMORY_CFG_DATA.Lp5BankMode | 0x0
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MEMORY_CFG_DATA.PrmrrSize | 0x200000
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# This setting is used for debug purposes
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#MEMORY_CFG_DATA.PlatformDebugConsent | 0x0
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GRAPHICS_CFG_DATA.InternalGfx | 0x2
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GEN_CFG_DATA.VbtImageId | 3
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#Delta configuration for Silicon settings
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SILICON_CFG_DATA.SataPortsDevSlp | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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SILICON_CFG_DATA.PortUsb20Enable | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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SILICON_CFG_DATA.PortUsb30Enable | {0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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SILICON_CFG_DATA.SerialIoUartMode | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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SILICON_CFG_DATA.SerialIoUartAutoFlow | {0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00}
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SILICON_CFG_DATA.SerialIoI2cMode | {0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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SILICON_CFG_DATA.Usb2PhyPetxiset | {0x02, 0x02, 0x06, 0x06, 0x02, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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SILICON_CFG_DATA.Usb2PhyPredeemp | {0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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SILICON_CFG_DATA.SataLedEnable | 0x1
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SILICON_CFG_DATA.CpuUsb3OverCurrentPin | {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}
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SILICON_CFG_DATA.PchIshGpEnable | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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SILICON_CFG_DATA.PcieRpAspm | {0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04}
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SILICON_CFG_DATA.Usb2OverCurrentPin | {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
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SILICON_CFG_DATA.Usb3OverCurrentPin | {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
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SILICON_CFG_DATA.PchDmiAspmCtrl | 0x4
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SILICON_CFG_DATA.CpuPcieRpAspm | {0x3, 0x3, 0x3, 0x0}
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SILICON_CFG_DATA.CpuPcieRpL1Substates | {0x2, 0x2, 0x2, 0x2}
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SILICON_CFG_DATA.CpuPcieRpMultiVcEnabled | { 0x0, 0x0, 0x0, 0x0 }
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SILICON_CFG_DATA.PtmEnabled | { 0x1, 0x1, 0x1, 0x1}
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SILICON_CFG_DATA.EnableTimedGpio0 | 0x0
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SILICON_CFG_DATA.EnableTimedGpio1 | 0x0
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SILICON_CFG_DATA.EcAvailable | 0x0
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SILICON_CFG_DATA.PchIshI2cEnable | {0x00, 0x00, 0x00}
|
||||
SILICON_CFG_DATA.PchPmSlpAMinAssert | 0x4
|
||||
|
||||
POWER_CFG_DATA.TccActivationOffset | 0xA
|
||||
POWER_CFG_DATA.TurboRatioLimitRatio | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
|
||||
POWER_CFG_DATA.TurboRatioLimitNumCore | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
|
||||
POWER_CFG_DATA.AtomTurboRatioLimitRatio | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
|
||||
POWER_CFG_DATA.AtomTurboRatioLimitNumCore | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
|
||||
POWER_CFG_DATA.Eist | 0x1
|
||||
POWER_CFG_DATA.TdcEnable | {0x1, 0x1, 0x0, 0x0, 0x0}
|
||||
POWER_CFG_DATA.ImonSlope | {0x00, 0x00, 0x67, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
|
||||
POWER_CFG_DATA.EnableItbm | 0x1
|
||||
|
||||
PEP_CFG_DATA.PepAudio | 0x1
|
||||
PEP_CFG_DATA.PepVmd | 0x0
|
||||
PEP_CFG_DATA.PepHeci3 | 0x0
|
||||
PEP_CFG_DATA.PepPcieLan | 0x1
|
||||
PEP_CFG_DATA.PepPcieWlan | 0x1
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A00.GPIOSkip_GPP_A00 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A01.GPIOSkip_GPP_A01 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A02.GPIOSkip_GPP_A02 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A03.GPIOSkip_GPP_A03 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A04.GPIOSkip_GPP_A04 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A05.GPIOSkip_GPP_A05 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A06.GPIOSkip_GPP_A06 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A07.GPIOSkip_GPP_A07 | 1
|
||||
|
||||
# LAN_DISABLE#
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_A08 | 0x0350A3A1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A08 | 0x02082E01
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A09.GPIOSkip_GPP_A09 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A10.GPIOSkip_GPP_A10 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A11.GPIOSkip_GPP_A11 | 1
|
||||
|
||||
# SATAXPCIE1
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_A12 | 0x0310A4A3
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A12 | 0x020C2E01
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A13.GPIOSkip_GPP_A13 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A14.GPIOSkip_GPP_A14 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A15.GPIOSkip_GPP_A15 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A16.GPIOSkip_GPP_A16 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A17.GPIOSkip_GPP_A17 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A18.GPIOSkip_GPP_A18 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A19.GPIOSkip_GPP_A19 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A20.GPIOSkip_GPP_A20 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A21.GPIOSkip_GPP_A21 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A22.GPIOSkip_GPP_A22 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_A23.GPIOSkip_GPP_A23 | 1
|
||||
|
||||
# CORE_VID0
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_B00 | 0x0310A4A3
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B00 | 0x00002E01
|
||||
|
||||
# CORE_VID1
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_B01 | 0x0310A4A3
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B01 | 0x00012E01
|
||||
|
||||
# VRALERT#
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_B02 | 0x0310A4A3
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B02 | 0x00022E01
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B03.GPIOSkip_GPP_B03 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B04.GPIOSkip_GPP_B04 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B05.GPIOSkip_GPP_B05 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B06.GPIOSkip_GPP_B06 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B07.GPIOSkip_GPP_B07 | 1
|
||||
|
||||
# EMMC_DET#
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_B08 | 0x0510A5A1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B08 | 0x00082E19
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B09.GPIOSkip_GPP_B09 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B10.GPIOSkip_GPP_B10 | 1
|
||||
|
||||
# PMC_ALERT#
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_B11 | 0x0310A4A3
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B11 | 0x000B2E01
|
||||
|
||||
# SLP_S0#
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_B12 | 0x0310A4A3
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B12 | 0x000C2E01
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B13.GPIOSkip_GPP_B13 | 1
|
||||
|
||||
# SATA_LED#
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_B14 | 0x0310A4A1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B14 | 0x000E2E01
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B15.GPIOSkip_GPP_B15 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B16.GPIOSkip_GPP_B16 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B17.GPIOSkip_GPP_B17 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B18.GPIOSkip_GPP_B18 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B19.GPIOSkip_GPP_B19 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B20.GPIOSkip_GPP_B20 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B21.GPIOSkip_GPP_B21 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B22.GPIOSkip_GPP_B22 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_B23.GPIOSkip_GPP_B23 | 1
|
||||
|
||||
# SMBUS
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_C00 | 0x0310A4A3
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_C00 | 0x0B002E01
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_C01 | 0x0310A4A3
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_C01 | 0x0B012E01
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_C02.GPIOSkip_GPP_C02 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_C03.GPIOSkip_GPP_C03 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_C04.GPIOSkip_GPP_C04 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_C05.GPIOSkip_GPP_C05 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_C06.GPIOSkip_GPP_C06 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_C07.GPIOSkip_GPP_C07 | 1
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D00.GPIOSkip_GPP_D00 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D01.GPIOSkip_GPP_D01 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D02.GPIOSkip_GPP_D02 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D03.GPIOSkip_GPP_D03 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D04.GPIOSkip_GPP_D04 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D05.GPIOSkip_GPP_D05 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D06.GPIOSkip_GPP_D06 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D07.GPIOSkip_GPP_D07 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D08.GPIOSkip_GPP_D08 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D09.GPIOSkip_GPP_D09 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D10.GPIOSkip_GPP_D10 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D11.GPIOSkip_GPP_D11 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D12.GPIOSkip_GPP_D12 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D13.GPIOSkip_GPP_D13 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D14.GPIOSkip_GPP_D14 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D15.GPIOSkip_GPP_D15 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D16.GPIOSkip_GPP_D16 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D17.GPIOSkip_GPP_D17 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D18.GPIOSkip_GPP_D18 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_D19.GPIOSkip_GPP_D19 | 1
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E00.GPIOSkip_GPP_E00 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E01.GPIOSkip_GPP_E01 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E02.GPIOSkip_GPP_E02 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E03.GPIOSkip_GPP_E03 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E04.GPIOSkip_GPP_E04 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E05.GPIOSkip_GPP_E05 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E06.GPIOSkip_GPP_E06 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E07.GPIOSkip_GPP_E07 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E08.GPIOSkip_GPP_E08 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E09.GPIOSkip_GPP_E09 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E10.GPIOSkip_GPP_E10 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E11.GPIOSkip_GPP_E11 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E12.GPIOSkip_GPP_E12 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E13.GPIOSkip_GPP_E13 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E14.GPIOSkip_GPP_E14 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E15.GPIOSkip_GPP_E15 | 1
|
||||
|
||||
# to NVMe slot pad 67
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_E16 | 0x0310A5A1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E16 | 0x0E102E01
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E17.GPIOSkip_GPP_E17 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E18.GPIOSkip_GPP_E18 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E19.GPIOSkip_GPP_E19 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E20.GPIOSkip_GPP_E20 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E21.GPIOSkip_GPP_E21 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E22.GPIOSkip_GPP_E22 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_E23.GPIOSkip_GPP_E23 | 1
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F00.GPIOSkip_GPP_F00 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F01.GPIOSkip_GPP_F01 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F02.GPIOSkip_GPP_F02 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F03.GPIOSkip_GPP_F03 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F04.GPIOSkip_GPP_F04 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F05.GPIOSkip_GPP_F05 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F06.GPIOSkip_GPP_F06 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F07.GPIOSkip_GPP_F07 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F08.GPIOSkip_GPP_F08 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F09.GPIOSkip_GPP_F09 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F10.GPIOSkip_GPP_F10 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F11.GPIOSkip_GPP_F11 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F12.GPIOSkip_GPP_F12 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F13.GPIOSkip_GPP_F13 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F14.GPIOSkip_GPP_F14 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F15.GPIOSkip_GPP_F15 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F16.GPIOSkip_GPP_F16 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F17.GPIOSkip_GPP_F17 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F18.GPIOSkip_GPP_F18 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F19.GPIOSkip_GPP_F19 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F20.GPIOSkip_GPP_F20 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F21.GPIOSkip_GPP_F21 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F22.GPIOSkip_GPP_F22 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_F23.GPIOSkip_GPP_F23 | 1
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H00.GPIOSkip_GPP_H00 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H01.GPIOSkip_GPP_H01 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H02.GPIOSkip_GPP_H02 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H03.GPIOSkip_GPP_H03 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H04.GPIOSkip_GPP_H04 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H05.GPIOSkip_GPP_H05 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H06.GPIOSkip_GPP_H06 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H07.GPIOSkip_GPP_H07 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H08.GPIOSkip_GPP_H08 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H09.GPIOSkip_GPP_H09 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H10.GPIOSkip_GPP_H10 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H11.GPIOSkip_GPP_H11 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H12.GPIOSkip_GPP_H12 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H13.GPIOSkip_GPP_H13 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H14.GPIOSkip_GPP_H14 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H15.GPIOSkip_GPP_H15 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H16.GPIOSkip_GPP_H16 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H17.GPIOSkip_GPP_H17 | 1
|
||||
|
||||
# PROC_C10_GATE#
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPP_H18 | 0x0310A4A3
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H18 | 0x07122E01
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H19.GPIOSkip_GPP_H19 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H20.GPIOSkip_GPP_H20 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H21.GPIOSkip_GPP_H21 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H22.GPIOSkip_GPP_H22 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_H23.GPIOSkip_GPP_H23 | 1
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_I05.GPIOSkip_GPP_I05 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_I07.GPIOSkip_GPP_I07 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_I08.GPIOSkip_GPP_I08 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_I09.GPIOSkip_GPP_I09 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_I10.GPIOSkip_GPP_I10 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_I11.GPIOSkip_GPP_I11 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_I12.GPIOSkip_GPP_I12 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_I13.GPIOSkip_GPP_I13 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_I14.GPIOSkip_GPP_I14 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_I15.GPIOSkip_GPP_I15 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_I16.GPIOSkip_GPP_I16 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_I17.GPIOSkip_GPP_I17 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_I18.GPIOSkip_GPP_I18 | 1
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_R00.GPIOSkip_GPP_R00 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_R01.GPIOSkip_GPP_R01 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_R02.GPIOSkip_GPP_R02 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_R03.GPIOSkip_GPP_R03 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_R04.GPIOSkip_GPP_R04 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_R05.GPIOSkip_GPP_R05 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_R06.GPIOSkip_GPP_R06 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_R07.GPIOSkip_GPP_R07 | 1
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_S00.GPIOSkip_GPP_S00 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_S01.GPIOSkip_GPP_S01 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_S02.GPIOSkip_GPP_S02 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_S03.GPIOSkip_GPP_S03 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_S04.GPIOSkip_GPP_S04 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_S05.GPIOSkip_GPP_S05 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_S06.GPIOSkip_GPP_S06 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPP_S07.GPIOSkip_GPP_S07 | 1
|
||||
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPD00.GPIOSkip_GPD00 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPD01.GPIOSkip_GPD01 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPD02 | 0x0350A3A1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPD02 | 0x05022E01
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPD03.GPIOSkip_GPD03 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPD04.GPIOSkip_GPD04 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPD05.GPIOSkip_GPD05 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPD06.GPIOSkip_GPD06 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPD07 | 0x0350A3A1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPD07 | 0x05072E01
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPD08.GPIOSkip_GPD08 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPD09.GPIOSkip_GPD09 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPD10.GPIOSkip_GPD10 | 1
|
||||
GPIO_CFG_DATA.GpioPinConfig0_GPD11 | 0x0350A3A1
|
||||
GPIO_CFG_DATA.GpioPinConfig1_GPD11 | 0x050B2E01
|
||||
@@ -24,6 +24,9 @@ Defines Platform BoardIds
|
||||
#define BoardIdAdlNLp5Rvp 0x07
|
||||
#define PLATFORM_ID_ADL_N_LPDDR5_RVP 0x07
|
||||
|
||||
#define BoardIdAdlNOdroidH4 0x0C
|
||||
#define PLATFORM_ID_ADL_N_ODROID_H4 0x0C
|
||||
|
||||
// Added for ADL-PS Board IDs
|
||||
#define BoardIdAdlPSDdr5Rvp 0x0B
|
||||
#define PLATFORM_ID_ADL_PS_DDR5_RVP 0x0B
|
||||
|
||||
@@ -163,6 +163,28 @@ GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mAdlNLpddr5RowDisplayDdiConfig[16] = {
|
||||
DdiDisable // DDI Port 4 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
|
||||
};
|
||||
|
||||
//
|
||||
// Display DDI settings for ODROID H4: DDIA-HDMI, DDIB-DP, TCP0-DP
|
||||
//
|
||||
GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mOdroidH4DisplayDdiConfig[16] = {
|
||||
DdiPortEdp, // DDI Port A Config : DdiPortDisabled = No LFP is Connected, DdiPortEdp = eDP, DdiPortMipiDsi = MIPI DSI
|
||||
DdiPortEdp, // DDI Port B Config : DdiPortDisabled = No LFP is Connected, DdiPortEdp = eDP, DdiPortMipiDsi = MIPI DSI
|
||||
DdiHpdEnable, // DDI Port A HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
|
||||
DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
|
||||
DdiHpdDisable, // DDI Port C HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
|
||||
DdiHpdEnable, // DDI Port 1 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
|
||||
DdiHpdDisable, // DDI Port 2 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
|
||||
DdiHpdDisable, // DDI Port 3 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
|
||||
DdiHpdDisable, // DDI Port 4 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
|
||||
DdiDdcEnable, // DDI Port A DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
|
||||
DdiDdcEnable, // DDI Port B DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
|
||||
DdiDisable, // DDI Port C DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
|
||||
DdiDdcEnable, // DDI Port 1 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
|
||||
DdiDisable, // DDI Port 2 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
|
||||
DdiDisable, // DDI Port 3 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
|
||||
DdiDisable // DDI Port 4 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
|
||||
};
|
||||
|
||||
//
|
||||
// Display DDI settings for RPL-P COM-HPC CRB DDR5 DDIA-DP, DDIB-DP ,TCP0-DP and TCP1-DP
|
||||
//
|
||||
|
||||
@@ -512,6 +512,10 @@ UpdateFspConfig (
|
||||
// DP + DP
|
||||
CopyMem(SaDisplayConfigTable, (VOID *)(UINTN)mAdlNLpddr5RowDisplayDdiConfig, sizeof(mAdlNLpddr5RowDisplayDdiConfig));
|
||||
break;
|
||||
case PLATFORM_ID_ADL_N_ODROID_H4:
|
||||
// HDMI + DP + DP
|
||||
CopyMem(SaDisplayConfigTable, (VOID *)(UINTN)mOdroidH4DisplayDdiConfig, sizeof(mOdroidH4DisplayDdiConfig));
|
||||
break;
|
||||
case PLATFORM_ID_RPL_P_DDR5_CRB:
|
||||
DEBUG((DEBUG_INFO, "PLATFORM_ID_RPL_P_DDR5_CRB board Id %x .....\n", PlatformId));
|
||||
CopyMem(SaDisplayConfigTable, (VOID *)(UINTN)mRplPDdr5SODimmCrbDisplayDdiConfig, sizeof(mRplPDdr5SODimmCrbDisplayDdiConfig));
|
||||
@@ -628,6 +632,9 @@ UpdateFspConfig (
|
||||
Fspmcfg->PcieClkReqGpioMux[9] = 0x796e9000;
|
||||
Fspmcfg->TcssXdciEn = 0x1;
|
||||
Fspmcfg->Lp5CccConfig = 0xff;
|
||||
case PLATFORM_ID_ADL_N_ODROID_H4:
|
||||
Fspmcfg->SkipCpuReplacementCheck = 0x1;
|
||||
Fspmcfg->LpDdrDqDqsReTraining = 0x1;
|
||||
break;
|
||||
default:
|
||||
DEBUG ((DEBUG_INFO, "Unknown board for FSP-M UPD settings.\n"));
|
||||
|
||||
@@ -669,7 +669,7 @@ UpdateFspConfig (
|
||||
FspsConfig->CpuPciePowerGating[1] = SiCfgData->CpuPciePowerGating;
|
||||
FspsConfig->CpuPciePowerGating[2] = SiCfgData->CpuPciePowerGating;
|
||||
FspsConfig->CpuPciePowerGating[3] = SiCfgData->CpuPciePowerGating;
|
||||
#if !defined(PLATFORM_ADLN) && !defined(PLATFORM_ADLN50)
|
||||
#if !defined(PLATFORM_ADLN) && !defined(PLATFORM_ADLN50) && !defined(PLATFORM_ODROID_H4)
|
||||
FspsConfig->L2QosEnumerationEn = SiCfgData->L2QosEnumerationEn;
|
||||
#endif
|
||||
}
|
||||
@@ -1117,6 +1117,54 @@ UpdateFspConfig (
|
||||
FspsConfig->CpuPcieRpGen5Uptp[1] = 0x7;
|
||||
FspsConfig->CpuPcieRpGen5Uptp[2] = 0x7;
|
||||
break;
|
||||
case PLATFORM_ID_ADL_N_ODROID_H4:
|
||||
FspsConfig->Usb4CmMode = 0x0;
|
||||
FspsConfig->EnergyEfficientTurbo = 0x1;
|
||||
FspsConfig->PkgCStateLimit = 0x6;
|
||||
FspsConfig->PsysPmax = 0x0;
|
||||
FspsConfig->PchUnlockGpioPads = 0x1;
|
||||
FspsConfig->PchLanEnable = 0x0;
|
||||
FspsConfig->PchPmVrAlert = 0x1;
|
||||
FspsConfig->IomStayInTCColdSeconds = 0x0;
|
||||
FspsConfig->IomBeforeEnteringTCColdSeconds = 0x0;
|
||||
FspsConfig->UsbTcPortEn = 0x0;
|
||||
FspsConfig->ITbtPcieRootPortEn[0] = 0x0;
|
||||
FspsConfig->ITbtPcieRootPortEn[1] = 0x0;
|
||||
FspsConfig->ITbtPcieRootPortEn[2] = 0x0;
|
||||
FspsConfig->ITbtPcieRootPortEn[3] = 0x0;
|
||||
FspsConfig->PortResetMessageEnable[0] = 0x0;
|
||||
FspsConfig->PortResetMessageEnable[1] = 0x0;
|
||||
FspsConfig->PortResetMessageEnable[2] = 0x0;
|
||||
FspsConfig->PortResetMessageEnable[3] = 0x0;
|
||||
FspsConfig->PortResetMessageEnable[4] = 0x0;
|
||||
FspsConfig->PortResetMessageEnable[5] = 0x0;
|
||||
FspsConfig->PortResetMessageEnable[6] = 0x0;
|
||||
FspsConfig->IomTypeCPortPadCfg[0] = 0x0;
|
||||
FspsConfig->IomTypeCPortPadCfg[1] = 0x0;
|
||||
FspsConfig->IomTypeCPortPadCfg[2] = 0x0;
|
||||
FspsConfig->IomTypeCPortPadCfg[3] = 0x0;
|
||||
FspsConfig->MeUnconfigOnRtcClear = 0x2;
|
||||
FspsConfig->CpuPcieRpPmSci[0] = 0x0;
|
||||
FspsConfig->CpuPcieRpPmSci[1] = 0x0;
|
||||
FspsConfig->CpuPcieRpPmSci[2] = 0x0;
|
||||
FspsConfig->CpuPcieRpMaxPayload[0] = 0x0;
|
||||
FspsConfig->CpuPcieRpMaxPayload[1] = 0x0;
|
||||
FspsConfig->CpuPcieRpMaxPayload[2] = 0x0;
|
||||
FspsConfig->CpuPcieRpLtrEnable[0] = 0x0;
|
||||
FspsConfig->CpuPcieRpLtrEnable[1] = 0x0;
|
||||
FspsConfig->CpuPcieRpLtrEnable[2] = 0x0;
|
||||
FspsConfig->IshGpGpioPinMuxing[4] = 0x0;
|
||||
FspsConfig->IshGpGpioPinMuxing[5] = 0x0;
|
||||
FspsConfig->IshGpGpioPinMuxing[6] = 0x0;
|
||||
FspsConfig->IshGpGpioPinMuxing[7] = 0x0;
|
||||
FspsConfig->SataPortDevSlpPinMux[0] = 0x0;
|
||||
FspsConfig->SataPortDevSlpPinMux[1] = 0x0;
|
||||
FspsConfig->TdcTimeWindow[1] = 0x3e8;
|
||||
FspsConfig->UsbPdoProgramming = 0x1;
|
||||
FspsConfig->PmcUsb2PhySusPgEnable = 0x0;
|
||||
FspsConfig->PmcModPhySusPgEnable = 0x0;
|
||||
FspsConfig->PchUsbOverCurrentEnable = 0x0;
|
||||
FspsConfig->PchXhciUaolEnable = 0x0;
|
||||
case PLATFORM_ID_ADL_PS_DDR5_RVP:
|
||||
FspsConfig->AmtEnabled = 0x0;
|
||||
FspsConfig->FwProgress = 0x0;
|
||||
|
||||
@@ -799,6 +799,9 @@ DEBUG_CODE_END();
|
||||
case PLATFORM_ID_ADL_N_UP7EN50:
|
||||
ConfigureGpio (CDATA_NO_TAG, sizeof (mGpioTablePreMemAdlNLpddr5Rvp) / sizeof (mGpioTablePreMemAdlNLpddr5Rvp[0]), (UINT8*)mGpioTablePreMemAdlNLpddr5Rvp);
|
||||
break;
|
||||
case PLATFORM_ID_ADL_N_ODROID_H4:
|
||||
// Do nothing
|
||||
break;
|
||||
case PLATFORM_ID_AZB_LP5_CRB2A:
|
||||
#if FixedPcdGetBool(PcdAzbWwanSupport)
|
||||
ConfigureGpio (CDATA_NO_TAG, sizeof (mGpioTablePreMemAzbLp5) / sizeof (mGpioTablePreMemAzbLp5[0]), (UINT8*)mGpioTablePreMemAzbLp5);
|
||||
|
||||
@@ -1226,6 +1226,59 @@ PlatformUpdateAcpiGnvs (
|
||||
PlatformNvs->WlanWakeGpio = GPIO_VER2_LP_GPP_D13;
|
||||
PlatformNvs->WlanRootPortNumber = 4;
|
||||
break;
|
||||
|
||||
case PLATFORM_ID_ADL_N_ODROID_H4:
|
||||
PlatformNvs->PcieSlot1WakeGpio = 0;
|
||||
PlatformNvs->PcieSlot1RpNumber = 0;
|
||||
PlatformNvs->PcieSlot1PowerEnableGpioPolarity = 0;
|
||||
PlatformNvs->PcieSlot1RstGpio = 0;
|
||||
PlatformNvs->PcieSlot1RstGpioPolarity = 0;
|
||||
|
||||
PlatformNvs->PcieSlot2WakeGpio = 0;
|
||||
PlatformNvs->PcieSlot2RpNumber = 0;
|
||||
PlatformNvs->PcieSlot2PowerEnableGpio = 0;
|
||||
PlatformNvs->PcieSlot2PowerEnableGpioPolarity = 0;
|
||||
PlatformNvs->PcieSlot2RstGpio = 0;
|
||||
PlatformNvs->PcieSlot2RstGpioPolarity = 0;
|
||||
|
||||
PlatformNvs->PcieSlot3WakeGpio = 0;
|
||||
PlatformNvs->PcieSlot3RpNumber = 0;
|
||||
PlatformNvs->PcieSlot3PowerEnableGpio = 0;
|
||||
PlatformNvs->PcieSlot3PowerEnableGpioPolarity = 0;
|
||||
PlatformNvs->PcieSlot3RstGpio = 0;
|
||||
PlatformNvs->PcieSlot3RstGpioPolarity = 0;
|
||||
|
||||
PlatformNvs->WlanWakeGpio = 0;
|
||||
PlatformNvs->WlanRootPortNumber = 0;
|
||||
|
||||
PlatformNvs->PegSlot1PwrEnableGpioNo = 0;
|
||||
PlatformNvs->PegSlot1PwrEnableGpioPolarity = 0;
|
||||
PlatformNvs->PegSlot1RstGpioNo = 0;
|
||||
PlatformNvs->PegSlot1RstGpioPolarity = 0;
|
||||
PlatformNvs->PegSlot1WakeGpioPin = 0;
|
||||
|
||||
PlatformNvs->M2Ssd2PowerEnableGpio = 0;
|
||||
PlatformNvs->M2Ssd2PowerEnableGpioPolarity = 0;
|
||||
PlatformNvs->M2Ssd2RstGpio = 0;
|
||||
PlatformNvs->M2Ssd2RstGpioPolarity = 0;
|
||||
|
||||
PlatformNvs->PchM2SsdPowerEnableGpioPolarity = 0;
|
||||
PlatformNvs->PchM2SsdRstGpio = 0;
|
||||
PlatformNvs->PchM2SsdRstGpioPolarity = 0;
|
||||
|
||||
PlatformNvs->PchM2Ssd2PowerEnableGpio = 0;
|
||||
PlatformNvs->PchM2Ssd2PowerEnableGpioPolarity = 0;
|
||||
PlatformNvs->PchM2Ssd2RstGpio = 0;
|
||||
PlatformNvs->PchM2Ssd2RstGpioPolarity = 0;
|
||||
|
||||
PlatformNvs->PchM2Ssd3PowerEnableGpio = 0;
|
||||
PlatformNvs->PchM2Ssd3PowerEnableGpioPolarity = 0;
|
||||
PlatformNvs->PchM2Ssd3RstGpio = 0;
|
||||
PlatformNvs->PchM2Ssd3RstGpioPolarity = 0;
|
||||
|
||||
PlatformNvs->SataPortPowerEnableGpio = 0;
|
||||
PlatformNvs->SataPortPowerEnableGpioPolarity = 0;
|
||||
|
||||
case PLATFORM_ID_AZB_LP5_CRB2A:
|
||||
break;
|
||||
default:
|
||||
@@ -1313,6 +1366,15 @@ PlatformUpdateAcpiGnvs (
|
||||
SaNvs->UFSIrq = 18;
|
||||
}
|
||||
|
||||
if (GetPlatformId () == PLATFORM_ID_ADL_N_ODROID_H4) {
|
||||
PlatformNvs->Rtd3Support = 0x0;
|
||||
SaNvs->CpuPcieRtd3 = 0;
|
||||
SaNvs->CpuPcieRp0Enable = 0;
|
||||
SaNvs->CpuPcieRp1Enable = 0;
|
||||
SaNvs->CpuPcieRp2Enable = 0;
|
||||
SaNvs->CpuPcieRp3Enable = 0;
|
||||
}
|
||||
|
||||
PlatformNvs->PpmFlags = CpuNvs->PpmFlags;
|
||||
SocUpdateAcpiGnvs ((VOID *)GnvsIn);
|
||||
|
||||
|
||||
BIN
Platform/AlderlakeBoardPkg/VbtBin/VbtAdlnOdroidH4.dat
Normal file
BIN
Platform/AlderlakeBoardPkg/VbtBin/VbtAdlnOdroidH4.dat
Normal file
Binary file not shown.
@@ -20,6 +20,7 @@
|
||||
#define B_LPC_CFG_IOE_ME1 BIT11 ///< Microcontroller Enable #1, Enables decoding of I/O locations 62h and 66h to LPC.
|
||||
#define B_LPC_CFG_IOE_CBE BIT1 ///< Com Port B Enable, Enables decoding of the COMB range to LPC. Range is selected LIOD.CB.
|
||||
#define B_LPC_CFG_IOE_CAE BIT0 ///< Com Port A Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA.
|
||||
#define B_LPC_CFG_IOE_SIO_2E_2F BIT12
|
||||
#define B_LPC_CFG_IOE_ME2 BIT13
|
||||
|
||||
#define R_ESPI_CFG_ESPI_LGIR1 0x84 ///< LPC Generic IO Range 1
|
||||
|
||||
@@ -18,6 +18,7 @@
|
||||
#include <PchAccess.h>
|
||||
#include <IndustryStandard/Pci.h>
|
||||
#include <Register/SerialIoUartRegs.h>
|
||||
#include <PlatformBoardId.h>
|
||||
|
||||
#define MM_PCI_OFFSET(Bus, Device, Function) \
|
||||
( (UINTN)(Bus << 20) + \
|
||||
@@ -88,6 +89,117 @@ GetSerialPortBase (
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
PnpWriteReg (
|
||||
UINT8 Reg,
|
||||
UINT8 Value
|
||||
)
|
||||
{
|
||||
IoWrite8(0x2E, Reg);
|
||||
IoWrite8(0x2F, Value);
|
||||
}
|
||||
|
||||
UINT8
|
||||
EFIAPI
|
||||
PnpReadReg (
|
||||
UINT8 Reg
|
||||
)
|
||||
{
|
||||
IoWrite8(0x2E, Reg);
|
||||
return IoRead8(0x2F);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
PnpSelectLdn (
|
||||
UINT8 Ldn
|
||||
)
|
||||
{
|
||||
PnpWriteReg(0x7, Ldn);
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
It8613EnterConfig (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
IoWrite8(0x2e, 0x87);
|
||||
IoWrite8(0x2e, 0x01);
|
||||
IoWrite8(0x2e, 0x55);
|
||||
IoWrite8(0x2e, 0x55);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
It8613ExitConfig (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
PnpWriteReg(0x2e, 0x01);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
InitIt8613Serial (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
It8613EnterConfig ();
|
||||
PnpSelectLdn (7);
|
||||
|
||||
/* Internal VCC_OK */
|
||||
PnpWriteReg (0x23, 0x40);
|
||||
/* Pin7 as GP23 - USB2_EN, Pin9 as GP21 - USB3_EN */
|
||||
PnpWriteReg (0x26, 0xfb);
|
||||
/* Pin24 as GPO50 (value of 0 on bit0 is reserved, JP1 strapping)*/
|
||||
PnpWriteReg (0x29, 0x01);
|
||||
/* K8 power sequence sofyware disabled */
|
||||
PnpWriteReg (0x2c, 0x41);
|
||||
/* PCICLK 25MHz */
|
||||
PnpWriteReg (0x2d, 0x02);
|
||||
|
||||
PnpWriteReg (0xbc, 0xc0);
|
||||
PnpWriteReg (0xbd, 0x03);
|
||||
PnpWriteReg (0xc1, 0x0a);
|
||||
PnpWriteReg (0xc8, 0x00);
|
||||
PnpWriteReg (0xc9, 0x0a);
|
||||
PnpWriteReg (0xda, 0xb0);
|
||||
PnpWriteReg (0xdb, 0x44);
|
||||
|
||||
/* Kill watchdog */
|
||||
PnpWriteReg (0x72, 0x00);
|
||||
PnpWriteReg (0x73, 0x00);
|
||||
PnpWriteReg (0x74, 0x00);
|
||||
|
||||
/* Configure GPIO I/O BASE */
|
||||
PnpWriteReg (0x62, 0x0a);
|
||||
PnpWriteReg (0x63, 0x00);
|
||||
|
||||
/* Enable Simple I/O on GP21 and GP23 */
|
||||
PnpWriteReg (0xc1, PnpReadReg(0xc1) | 0x0a);
|
||||
/* Configure GP21 and GP23 as output */
|
||||
PnpWriteReg (0xc9, PnpReadReg(0xc9) | 0x0a);
|
||||
|
||||
/* Drive GP21 and GP23 low to enable VBUS on USB ports */
|
||||
IoWrite8(0xa01, IoRead8(0xa01) & ~0x0a);
|
||||
|
||||
/* Init UART */
|
||||
PnpSelectLdn (1);
|
||||
PnpWriteReg (0x30, 0x0);
|
||||
PnpWriteReg (0x60, 0x3);
|
||||
PnpWriteReg (0x61, 0xf8);
|
||||
PnpWriteReg (0x70, 0x4);
|
||||
PnpWriteReg (0xf0, 0x1);
|
||||
PnpWriteReg (0xf1, 0x52);
|
||||
PnpWriteReg (0x30, 0x1);
|
||||
|
||||
It8613ExitConfig ();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Performs platform specific initialization required for the CPU to access
|
||||
the hardware associated with a SerialPortLib instance. This function does
|
||||
@@ -123,9 +235,18 @@ LegacySerialPortInitialize (
|
||||
Data16 = PciRead16 (eSPIBaseAddr + R_LPC_CFG_IOE);
|
||||
Data16 |= B_LPC_CFG_IOE_CBE;
|
||||
Data16 |= B_LPC_CFG_IOE_CAE;
|
||||
Data16 |= B_LPC_CFG_IOE_SIO_2E_2F;
|
||||
MmioWrite16 (PCH_PCR_ADDRESS (PID_DMI, R_PCH_DMI_PCR_LPCIOE), Data16);
|
||||
PciWrite16 (eSPIBaseAddr + R_LPC_CFG_IOE, Data16);
|
||||
|
||||
if (GetPlatformId() == PLATFORM_ID_ADL_N_ODROID_H4) {
|
||||
/* Enable I/O range 0xa00 decoding for IT8613E GPIO */
|
||||
MmioWrite32 (PCH_PCR_ADDRESS (PID_DMI, R_PCH_DMI_PCR_LPCLGIR1), 0x007c0a01);
|
||||
PciWrite32 (eSPIBaseAddr + R_ESPI_CFG_ESPI_LGIR1, 0x007c0a01);
|
||||
|
||||
InitIt8613Serial ();
|
||||
}
|
||||
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
@@ -29,6 +29,7 @@
|
||||
BootloaderCorePkg/BootloaderCorePkg.dec
|
||||
Silicon/AlderlakePkg/AlderlakePkg.dec
|
||||
Silicon/CommonSocPkg/CommonSocPkg.dec
|
||||
Platform/AlderlakeBoardPkg/AlderlakeBoardPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
|
||||
Reference in New Issue
Block a user