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[IntelFsp2Pkg] Update to latest EDK2 stable tag 202111

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This patch updated SBL IntelFsp2Pkg to be in sync with EDK2 stable tag
202111.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This commit is contained in:
Maurice Ma
2021-12-13 14:08:25 -08:00
parent c7e1623c29
commit dda4d34fb3
4 changed files with 87 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files
IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
+32 -1
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@@ -2,7 +2,7 @@
Intel FSP Header File definition from Intel Firmware Support Package External
Architecture Specification v2.0 and above.
Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -44,14 +44,28 @@ typedef struct {
UINT8 Reserved1[2];
///
/// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.
/// For revision v2.3 the value will be 0x23.
///
UINT8 SpecVersion;
///
/// Byte 0x0B: Revision of the FSP Information Header.
/// The Current value for this field is 0x6.
///
UINT8 HeaderRevision;
///
/// Byte 0x0C: Revision of the FSP binary.
/// Major.Minor.Revision.Build
/// If FSP HeaderRevision is <= 5, the ImageRevision can be decoded as follows:
/// 7 : 0 - Build Number
/// 15 : 8 - Revision
/// 23 : 16 - Minor Version
/// 31 : 24 - Major Version
/// If FSP HeaderRevision is >= 6, ImageRevision specifies the low-order bytes of the build number and revision
/// while ExtendedImageRevision specifies the high-order bytes of the build number and revision.
/// 7 : 0 - Low Byte of Build Number
/// 15 : 8 - Low Byte of Revision
/// 23 : 16 - Minor Version
/// 31 : 24 - Major Version
///
UINT32 ImageRevision;
///
@@ -116,6 +130,23 @@ typedef struct {
/// If the value is set to 0x00000000, then this API is not available in this component.
///
UINT32 FspMultiPhaseSiInitEntryOffset;
///
/// Byte 0x4C: Extended revision of the FSP binary.
/// This value is only valid if FSP HeaderRevision is >= 6.
/// ExtendedImageRevision specifies the high-order byte of the revision and build number in the FSP binary revision.
/// 7 : 0 - High Byte of Build Number
/// 15 : 8 - High Byte of Revision
/// The FSP binary build number can be decoded as follows:
/// Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0]
/// Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8]
/// Minor Version = ImageRevision[23:16]
/// Major Version = ImageRevision[31:24]
///
UINT16 ExtendedImageRevision;
///
/// Byte 0x4E: Reserved4.
///
UINT16 Reserved4;
} FSP_INFO_HEADER;
///
IntelFsp2Pkg/IntelFsp2Pkg.dec
+7 -1
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@@ -1,7 +1,7 @@
## @file
# Provides driver and definitions to build fsp in EDKII bios.
#
# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -68,6 +68,7 @@
# Guid define in FSP EAS
gFspHeaderFileGuid = { 0x912740BE, 0x2284, 0x4734, { 0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C } }
gFspReservedMemoryResourceHobGuid = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }
gFspNonVolatileStorageHob2Guid = { 0x4866788f, 0x6ba8, 0x47d8, { 0x83, 0x06, 0xac, 0xf7, 0x7f, 0x55, 0x10, 0x46 } }
gFspNonVolatileStorageHobGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }
gFspBootLoaderTolumHobGuid = { 0x73ff4f56, 0xaa8e, 0x4451, { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } } # FSP EAS v1.1
@@ -98,6 +99,11 @@
# Maximal Interrupt supported in IDT table.
#
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported | 34| UINT8|0x10000005
#
# Allows FSP-M to reserve a section of Temporary RAM for implementation specific use.
# Reduces the amount of memory available for the PeiCore heap.
#
gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize |0x00000000|UINT32|0x10000006
[PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]
gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT32|0x46530000
IntelFsp2Pkg/IntelFsp2Pkg.dsc
+3 -1
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@@ -1,7 +1,7 @@
## @file
# Provides driver and definitions to build fsp.
#
# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -16,6 +16,8 @@
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
!include MdePkg/MdeLibs.dsc.inc
[LibraryClasses]
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
IntelFsp2Pkg/Tools/SplitFspBin.py
+45 -23
View File
@@ -1,6 +1,6 @@
## @ FspTool.py
## @ SplitFspBin.py
#
# Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -103,26 +103,29 @@ class FSP_COMMON_HEADER(Structure):
class FSP_INFORMATION_HEADER(Structure):
_fields_ = [
('Signature', ARRAY(c_char, 4)),
('HeaderLength', c_uint32),
('Reserved1', c_uint16),
('SpecVersion', c_uint8),
('HeaderRevision', c_uint8),
('ImageRevision', c_uint32),
('ImageId', ARRAY(c_char, 8)),
('ImageSize', c_uint32),
('ImageBase', c_uint32),
('ImageAttribute', c_uint16),
('ComponentAttribute', c_uint16),
('CfgRegionOffset', c_uint32),
('CfgRegionSize', c_uint32),
('Reserved2', c_uint32),
('TempRamInitEntryOffset', c_uint32),
('Reserved3', c_uint32),
('NotifyPhaseEntryOffset', c_uint32),
('FspMemoryInitEntryOffset', c_uint32),
('TempRamExitEntryOffset', c_uint32),
('FspSiliconInitEntryOffset', c_uint32)
('Signature', ARRAY(c_char, 4)),
('HeaderLength', c_uint32),
('Reserved1', c_uint16),
('SpecVersion', c_uint8),
('HeaderRevision', c_uint8),
('ImageRevision', c_uint32),
('ImageId', ARRAY(c_char, 8)),
('ImageSize', c_uint32),
('ImageBase', c_uint32),
('ImageAttribute', c_uint16),
('ComponentAttribute', c_uint16),
('CfgRegionOffset', c_uint32),
('CfgRegionSize', c_uint32),
('Reserved2', c_uint32),
('TempRamInitEntryOffset', c_uint32),
('Reserved3', c_uint32),
('NotifyPhaseEntryOffset', c_uint32),
('FspMemoryInitEntryOffset', c_uint32),
('TempRamExitEntryOffset', c_uint32),
('FspSiliconInitEntryOffset', c_uint32),
('FspMultiPhaseSiInitEntryOffset', c_uint32),
('ExtendedImageRevision', c_uint16),
('Reserved4', c_uint16)
]
class FSP_PATCH_TABLE(Structure):
@@ -390,7 +393,26 @@ def OutputStruct (obj, indent = 0, plen = 0):
if IsStrType (val):
rep = HandleNameStr (val)
elif IsIntegerType (val):
rep = '0x%X' % val
if (key == 'ImageRevision'):
FspImageRevisionMajor = ((val >> 24) & 0xFF)
FspImageRevisionMinor = ((val >> 16) & 0xFF)
FspImageRevisionRevision = ((val >> 8) & 0xFF)
FspImageRevisionBuildNumber = (val & 0xFF)
rep = '0x%08X' % val
elif (key == 'ExtendedImageRevision'):
FspImageRevisionRevision |= (val & 0xFF00)
FspImageRevisionBuildNumber |= ((val << 8) & 0xFF00)
rep = "0x%04X ('%02X.%02X.%04X.%04X')" % (val, FspImageRevisionMajor, FspImageRevisionMinor, FspImageRevisionRevision, FspImageRevisionBuildNumber)
elif field[1] == c_uint64:
rep = '0x%016X' % val
elif field[1] == c_uint32:
rep = '0x%08X' % val
elif field[1] == c_uint16:
rep = '0x%04X' % val
elif field[1] == c_uint8:
rep = '0x%02X' % val
else:
rep = '0x%X' % val
elif isinstance(val, c_uint24):
rep = '0x%X' % val.get_value()
elif 'c_ubyte_Array' in str(type(val)):