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feat: [MTL] Upstream MTL to open source (#2147)

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Upstream remaining internal MTL code to SBL open source.
Remove TCC specific code in Stage2BoardInitLib as feature is not supported

Signed-off-by: kokweich <kok.wei.chan@intel.com>
This commit is contained in:
kokweich
2024-03-07 21:34:13 +08:00
committed by GitHub
parent 617a889beb
commit 70af3d9614
13 changed files with 1058 additions and 79 deletions
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25
Platform/MeteorlakeBoardPkg/BoardConfigMtlPs.py Normal file
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## @file
# This file is used to provide board specific image information.
#
# Copyright (c) 2023 - 2024, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
# Import Modules
#
import os
import sys
tool_dir = os.path.realpath(os.path.join(os.path.dirname (os.path.realpath(__file__)), '..', 'MeteorlakeBoardPkg'))
sys.path.append (tool_dir)
import BoardConfigMtlp as MeteorlakeBoardConfig
class Board(MeteorlakeBoardConfig.Board):
def __init__(self, *args, **kwargs):
super(Board, self).__init__(*args, **kwargs)
self.VERINFO_IMAGE_ID = 'SB_MTLPS'
self.BOARD_NAME = 'mtlps'
self._PS_SUPPORT = True
self.ACPI_TABLE_INF_FILE = 'Platform/MeteorlakeBoardPkg/AcpiTables/AcpiTablesPs.inf'

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Platform/MeteorlakeBoardPkg/BoardConfigMtlp.py Normal file
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## @file
# This file is used to provide board specific image information.
#
# Copyright (c) 2020 - 2024, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
# Import Modules
#
import os
import sys
import time
sys.dont_write_bytecode = True
sys.path.append (os.path.join('..', '..'))
from BuildLoader import *
class Board(BaseBoard):
def __init__(self, *args, **kwargs):
super(Board, self).__init__(*args, **kwargs)
self.VERINFO_IMAGE_ID = 'SB_MTLP'
self.VERINFO_PROJ_MAJOR_VER = 0
self.VERINFO_PROJ_MINOR_VER = 0
self.VERINFO_SVN = 1
self.VERINFO_BUILD_DATE = time.strftime("%m/%d/%Y")
self.BOARD_NAME = 'mtl'
self.BOARD_PKG_NAME = 'MeteorlakeBoardPkg'
self.SILICON_PKG_NAME = 'MeteorlakePkg'
self.FSP_IMAGE_ID = '$MTLFSP$'
self._EXTRA_INC_PATH = ['Silicon/MeteorlakePkg/FspBin']
self._FSP_PATH_NAME = 'Silicon/MeteorlakePkg/FspBin'
self.FSP_INF_FILE = 'Silicon/MeteorlakePkg/FspBin/FspBin.inf'
self.MICROCODE_INF_FILE = 'Silicon/MeteorlakePkg/Microcode/Microcode.inf'
self._LP_SUPPORT = False
self._N_SUPPORT = False
self._PS_SUPPORT = False
self.PCI_EXPRESS_BASE = 0xC0000000
self.PCI_IO_BASE = 0x00002000
self.PCI_MEM32_BASE = 0x80000000
self.ACPI_PM_TIMER_BASE = 0x1808
self.FLASH_LAYOUT_START = 0x100000000 # 4GB Top
self.FLASH_BASE_SIZE = 0x02000000 # 32MB
self.FLASH_BASE_ADDRESS = (self.FLASH_LAYOUT_START - self.FLASH_BASE_SIZE)
self.LOADER_ACPI_RECLAIM_MEM_SIZE = 0x000090000
self.HAVE_FIT_TABLE = 1
self.HAVE_VBT_BIN = 1 # TBD
self.HAVE_VERIFIED_BOOT = 1
self.HAVE_MEASURED_BOOT = 1
self.HAVE_FLASH_MAP = 1
self.HAVE_ACPI_TABLE = 1
self.HAVE_PSD_TABLE = 1
self.ENABLE_SPLASH = 1
self.ENABLE_FRAMEBUFFER_INIT = 1
self.ENABLE_VTD = 1
# To enable source debug, set 1 to self.ENABLE_SOURCE_DEBUG
self.ENABLE_SOURCE_DEBUG = 0
# If ENABLE_SOURCE_DEBUG is disabled, SKIP_STAGE1A_SOURCE_DEBUG will be ignored
self.SKIP_STAGE1A_SOURCE_DEBUG = 1
# 0: Disable 1: Enable 2: Auto (disable for UEFI payload, enable for others)
self.ENABLE_SMM_REBASE = 2
# 0 - PCH UART0, 1 - PCH UART1, 2 - PCH UART2, 0xFF - EC UART 0x3F8
self.DEBUG_PORT_NUMBER = 0x0
self.ENABLE_MULTI_USB_BOOT_DEV = 1
self.CPU_MAX_LOGICAL_PROCESSOR_NUMBER = 32
self.SUPPORT_X2APIC = 0
self.ENABLE_GRUB_CONFIG = 1
if self.HAVE_FIT_TABLE:
self.FIT_ENTRY_MAX_NUM = 17
# RSA2048 or RSA3072
self._RSA_SIGN_TYPE = 'RSA3072'
# 'SHA2_256' or 'SHA2_384'
self._SIGN_HASH = 'SHA2_384'
# 0x01 for SHA2_256 or 0x02 for SHA2_384
self.SIGN_HASH_TYPE = HASH_TYPE_VALUE[self._SIGN_HASH]
# 0x0010 for SM3_256 | 0x0008 for SHA2_512 | 0x0004 for SHA2_384 | 0x0002 for SHA2_256 | 0x0001 for SHA1
self.IPP_HASH_LIB_SUPPORTED_MASK = IPP_CRYPTO_ALG_MASK['SHA2_384'] | IPP_CRYPTO_ALG_MASK['SHA2_256']
# G9 for 384 | W7 Opt for SHA384| Ni Opt for SHA256| V8 Opt for SHA256
self.ENABLE_CRYPTO_SHA_OPT = IPP_CRYPTO_OPTIMIZATION_MASK['SHA256_NI'] | IPP_CRYPTO_OPTIMIZATION_MASK['SHA384_W7']
# Key configuration
self._MASTER_PRIVATE_KEY = 'KEY_ID_MASTER' + '_' + self._RSA_SIGN_TYPE
self._CFGDATA_PRIVATE_KEY = 'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
self._CONTAINER_PRIVATE_KEY = 'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
self.ENABLE_SMP_INIT = 1 # SMP is N/A on SIMICS
self.ENABLE_FWU = 1
self.ENABLE_SMBIOS = 1
self.ENABLE_CSME_UPDATE = 1
# CSME update library is required to enable this option and will be available as part of CSME kit
self.BUILD_CSME_UPDATE_DRIVER = 0
self.STAGE1A_XIP = 1
self.STAGE1B_XIP = 1
self.STAGE2_XIP = 0
self.STAGE1A_SIZE = 0x00020000
self.STAGE1_STACK_SIZE = 0x00002000
self.STAGE1_DATA_SIZE = 0x00014000
self.FSP_M_STACK_TOP = 0xFEF7FF00
self.STAGE1B_SIZE = 0x00200000
self.STAGE2_SIZE = 0x000C1000
self.STAGE2_FD_BASE = 0x01000000
self.STAGE2_FD_SIZE = 0x001F0000
self.PAYLOAD_SIZE = 0x0002C000
self.EPAYLOAD_SIZE = 0x00187000
self.ENABLE_FAST_BOOT = 0
if self.ENABLE_FAST_BOOT:
self.ENABLE_SPLASH = 0
self.ENABLE_FRAMEBUFFER_INIT = 0
self.RELEASE_MODE = 1
self.HAVE_VERIFIED_BOOT = 0
self.HAVE_MEASURED_BOOT = 0
self.VERIFIED_BOOT_HASH_MASK = 0
if self.RELEASE_MODE and self.ENABLE_FAST_BOOT:
self.STAGE1A_SIZE = 0x00016000
self.STAGE1B_SIZE = 0x000E0000
self.STAGE2_SIZE = 0x000C0000
self.STAGE2_FD_SIZE = 0x000F0000
self.PAYLOAD_SIZE = 0x00024000
if self.ENABLE_SOURCE_DEBUG:
self.STAGE1B_SIZE += 0x4000
if self.SKIP_STAGE1A_SOURCE_DEBUG == 0:
self.STAGE1A_SIZE += 0x4000
self.UEFI_VARIABLE_SIZE = 0x1000
if len(self._PAYLOAD_NAME.split(';')) > 1:
self.UEFI_VARIABLE_SIZE = 0x00040000
self.UCODE_SIZE = 0x000B7000
self.UCODE_SLOT_SIZE = 0x00037000
self.MRCDATA_SIZE = 0x00010000
self.CFGDATA_SIZE = 0x00004000
self.KEYHASH_SIZE = 0x00001000
self.VARIABLE_SIZE = 0x00002000
self.SBLRSVD_SIZE = 0x00001000
self.FWUPDATE_SIZE = 0x00020000 if self.ENABLE_FWU else 0
# Need a little bit more for full paging table
self.OS_LOADER_FD_SIZE = 0x00058000
self.OS_LOADER_FD_NUMBLK = self.OS_LOADER_FD_SIZE // self.FLASH_BLOCK_SIZE
# If BUILD_IDENTICAL_TS is 0, the flash map sizings and layout
# will need to be adjusted so that uCode and Stage 1B are in
# redudant partition
self.BUILD_IDENTICAL_TS = 1
# If ENABLE_SBL_RESILIENCY is 1, BiosRedAssistance FIT strap setting
# needs to be manually changed to Enabled
self.ENABLE_SBL_RESILIENCY = 0
self.TOP_SWAP_SIZE = 0x00400000
self.REDUNDANT_SIZE = self.STAGE2_SIZE + self.FWUPDATE_SIZE + \
self.CFGDATA_SIZE + self.KEYHASH_SIZE
self.SIIPFW_SIZE = 0x1000
self.ENABLE_TCC = 0
if self.ENABLE_TCC:
self.TCC_CCFG_SIZE = 0x00001000
self.TCC_CRL_SIZE = 0x00008000
self.TCC_STREAM_SIZE = 0x00005000
self.SIIPFW_SIZE += self.TCC_CCFG_SIZE + self.TCC_CRL_SIZE + self.TCC_STREAM_SIZE
self.ENABLE_TSN = 0
if self.ENABLE_TSN:
self.TMAC_SIZE = 0x00001000
self.SIIPFW_SIZE += self.TMAC_SIZE
self.NON_REDUNDANT_SIZE = 0x3BF000 + self.SIIPFW_SIZE
self.NON_VOLATILE_SIZE = 0x001000
self.SLIMBOOTLOADER_SIZE = (self.TOP_SWAP_SIZE + self.REDUNDANT_SIZE) * 2 + \
self.NON_REDUNDANT_SIZE + self.NON_VOLATILE_SIZE
self.SLIMBOOTLOADER_SIZE = ((self.SLIMBOOTLOADER_SIZE + 0xFFFFF) & ~0xFFFFF)
self.PLD_HEAP_SIZE = 0x09000000
# self.PLD_HEAP_SIZE = 0x04000000
self.PLD_STACK_SIZE = 0x00020000
self.PLD_RSVD_MEM_SIZE = 0x00500000
self.KM_SIZE = 0x00000400
self.BPM_SIZE = 0x00000600
self.ACM_SIZE = 0x00040000 + self.KM_SIZE + self.BPM_SIZE
# adjust ACM_SIZE to meet 256KB alignment (to align 256KB ACM size)
if self.ACM_SIZE > 0:
acm_top = self.FLASH_LAYOUT_START - self.STAGE1A_SIZE
acm_btm = acm_top - self.ACM_SIZE
acm_btm = (acm_btm & 0xFFFC0000)
self.ACM_SIZE = acm_top - acm_btm
self.LOADER_RSVD_MEM_SIZE = 0x500000
# If mulitple VBT table support is required, list them as:
# {VbtImageId1 : VbtFileName1, VbtImageId2 : VbtFileName2, ...}
# VbtImageId is ID to identify a VBT image. It is a UINT32 number to match
# the ImageId field in the VBT container.
# VbtFileName is the VBT file name. It needs to be located under platform
# VbtBin folder.
self._MULTI_VBT_FILE = {1:'VbtMtlpCrb.dat', 2:'VbtMtlpLp5.dat', 3:'VbtMtlpRvp.dat', 4:'VbtMtlpsCrb.dat', 5:'VbtMtlpsRvp.dat'}
self.CFG_DATABASE_SIZE = self.CFGDATA_SIZE
self._generated_cfg_file_prefix = 'Autogen_'
self._CFGDATA_INT_FILE = []
self._CFGDATA_EXT_FILE = [self._generated_cfg_file_prefix + 'CfgData_Int_Mtlp_DDR5_Rvp.dlt', self._generated_cfg_file_prefix + 'CfgData_Int_Mtlps_DDR5_RVP.dlt', self._generated_cfg_file_prefix + 'CfgData_Int_Mtlps_DDR5_CRB.dlt', self._generated_cfg_file_prefix + 'CfgData_Int_Mtlp_LPDDR5_Rvp.dlt', self._generated_cfg_file_prefix + 'CfgData_Int_Mtlp_DDR5_CRB.dlt']
def PlatformBuildHook (self, build, phase):
if phase == 'pre-build:before':
# create build folder if not exist
if not os.path.exists(build._fv_dir):
os.makedirs(build._fv_dir)
# Generate the dlt files based on feature
brd_cfg_src_dir = os.path.join(os.environ['PLT_SOURCE'], 'Platform', self.BOARD_PKG_NAME, 'CfgData')
brd_cfg2_src_dir = '.'
if hasattr(self, 'BOARD_PKG_NAME_OVERRIDE'):
brd_cfg2_src_dir = os.path.join(os.environ['PLT_SOURCE'], 'Platform', self.BOARD_PKG_NAME_OVERRIDE, 'CfgData')
for dlt_file in self._CFGDATA_EXT_FILE:
cfg_dlt_file = os.path.join(brd_cfg_src_dir, dlt_file[len (self._generated_cfg_file_prefix):])
if not os.path.exists(cfg_dlt_file):
cfg_dlt_file = os.path.join(brd_cfg2_src_dir, dlt_file[len (self._generated_cfg_file_prefix):])
lines = open (cfg_dlt_file).read()
# Enable TCC in dlt file
if self.ENABLE_TCC:
if os.path.exists(os.path.join(brd_cfg_src_dir, 'CfgData_Tcc_Feature.dlt')):
lines += open (os.path.join(brd_cfg_src_dir, 'CfgData_Tcc_Feature.dlt')).read()
else:
lines += open (os.path.join(brd_cfg2_src_dir, 'CfgData_Tcc_Feature.dlt')).read()
# Enable TSN in dlt file
if self.ENABLE_TSN:
if os.path.exists(os.path.join(brd_cfg_src_dir, 'CfgData_Tsn_Feature.dlt')):
lines += open (os.path.join(brd_cfg_src_dir, 'CfgData_Tsn_Feature.dlt')).read()
else:
lines += open (os.path.join(brd_cfg2_src_dir, 'CfgData_Tsn_Feature.dlt')).read()
# Write to generated final dlt file
output_cfg_dlt_file = os.path.join(build._fv_dir, dlt_file)
open(output_cfg_dlt_file, 'w').write(lines)
def GetPlatformDsc (self, BuildPkgName = "BootLoaderCorePkg"):
dsc = {}
# These libraries will be added into the DSC files
dsc['LibraryClasses.%s' % self.BUILD_ARCH] = [
'LoaderLib|Platform/CommonBoardPkg/Library/LoaderLib/LoaderLib.inf',
'SerialPortLib|BootloaderCommonPkg/Library/SerialPortLib/SerialPortLib.inf',
'PlatformHookLib|Silicon/$(SILICON_PKG_NAME)/Library/PlatformHookLib/PlatformHookLib.inf',
'ResetSystemLib|Platform/$(BOARD_PKG_NAME)/Library/ResetSystemLib/ResetSystemLib.inf',
'GpioLib|Silicon/CommonSocPkg/Library/GpioLib/GpioLib.inf',
'GpioV2Lib|Silicon/$(SILICON_PKG_NAME)/Library/GpioV2Lib/GpioV2Lib.inf',
'PchP2sbLib|Silicon/$(SILICON_PKG_NAME)/Library/PchP2sbLib/PchP2sbLib.inf',
'GpioSiLib|Silicon/$(SILICON_PKG_NAME)/Library/GpioSiLib/GpioSiLib.inf',
'PchSbiAccessLib|Silicon/CommonSocPkg/Library/PchSbiAccessLib/PchSbiAccessLib.inf',
'TccLib|Silicon/CommonSocPkg/Library/TccLib/TccLib.inf',
'ShellExtensionLib|Platform/$(BOARD_PKG_NAME)/Library/ShellExtensionLib/ShellExtensionLib.inf',
'FspmUpdUpdateLib|Platform/$(BOARD_PKG_NAME)/Library/FspmUpdUpdateLib/FspmUpdUpdateLib.inf',
'FspsUpdUpdateLib|Platform/$(BOARD_PKG_NAME)/Library/FspsUpdUpdateLib/FspsUpdUpdateLib.inf',
'PchInfoLib|Silicon/$(SILICON_PKG_NAME)/Library/PchInfoLib/PchInfoLib.inf',
'PchPciBdfLib|Silicon/$(SILICON_PKG_NAME)/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf',
'PchSpiLib|Silicon/CommonSocPkg/Library/PchSpiLib/PchSpiLib.inf',
'SpiFlashLib|Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.inf',
'BootGuardLib|Silicon/$(SILICON_PKG_NAME)/Library/BootGuardLibCBnT/BootGuardLibCBnT.inf',
'BdatLib|Silicon/CommonSocPkg/Library/BdatLib/BdatLib.inf',
'SmbusLib|Silicon/CommonSocPkg/Library/SmbusLib/SmbusLib.inf',
'IgdOpRegionLib30|Silicon/CommonSocPkg/Library/IgdOpRegionLib/IgdOpRegionLib30/IgdOpRegionLib30.inf',
'HeciLib|Silicon/CommonSocPkg/Library/HeciLib/HeciLib.inf',
'MeChipsetLib|Silicon/CommonSocPkg/Library/MeChipsetLib/MeChipsetLib.inf',
'VtdLib|Silicon/$(SILICON_PKG_NAME)/Library/VTdLib/VTdLib.inf',
'PsdLib|Silicon/$(SILICON_PKG_NAME)/Library/PsdLib/PsdLib.inf',
'HeciMeExtLib|Silicon/$(SILICON_PKG_NAME)/Library/HeciMeExtLib/HeciMeExtLib.inf',
'MeExtMeasurementLib|Silicon/$(SILICON_PKG_NAME)/Library/MeExtMeasurementLib/MeExtMeasurementLib.inf',
'CpuPcieHsPhyInitLib|Silicon/$(SILICON_PKG_NAME)/Library/CpuPcieHsPhyInitLib/CpuPcieHsPhyInitLib.inf',
'WatchDogTimerLib|Silicon/CommonSocPkg/Library/WatchDogTimerLib/WatchDogTimerLib.inf',
'TcoTimerLib|Silicon/CommonSocPkg/Library/TcoTimerLib/TcoTimerLib.inf',
'TopSwapLib|Silicon/$(SILICON_PKG_NAME)/Library/TopSwapLib/TopSwapLib.inf'
]
if self.BUILD_CSME_UPDATE_DRIVER:
dsc['LibraryClasses.%s' % self.BUILD_ARCH].append ('MeFwUpdateLib|Silicon/$(SILICON_PKG_NAME)/Library/MeFwUpdateLib/MeFwUpdateLib.inf')
dsc['PcdsFixedAtBuild'] = ['gPlatformModuleTokenSpaceGuid.PcdAcpiTablesMaxEntry | 40']
if self._PS_SUPPORT:
dsc['PcdsFixedAtBuild'].append('gPlatformMeteorLakeTokenSpaceGuid.PcdMtlPSSupport | TRUE')
return dsc
def GetKeyHashList (self):
# Define a set of new key used for different purposes
# The key is either key id or public key PEM format or private key PEM format
pub_key_list = [
(
# Key for verifying Config data blob
HASH_USAGE['PUBKEY_CFG_DATA'],
'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
),
(
# Key for verifying firmware update
HASH_USAGE['PUBKEY_FWU'],
'KEY_ID_FIRMWAREUPDATE' + '_' + self._RSA_SIGN_TYPE
),
(
# Key for verifying container header
HASH_USAGE['PUBKEY_CONT_DEF'],
'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
),
(
# Use RSA2048 key for verifying OS image signed with RSA2048
HASH_USAGE['PUBKEY_OS'],
'KEY_ID_OS1_PUBLIC_RSA2048'
),
(
# Use RSA3072 key for verifying OS image signed with RSA3072
HASH_USAGE['PUBKEY_OS'],
'KEY_ID_OS1_PUBLIC_RSA3072'
),
]
return pub_key_list
def GetContainerList (self):
container_list = []
container_list_auth_type = self._RSA_SIGN_TYPE + '_'+ self._SIGNING_SCHEME[4:] + '_' + self._SIGN_HASH
container_list.append (
# Name | Image File | CompressAlg | AuthType | Key File | Region Align | Region Size | Svn Info
# ========================================================================================================================================================
('IPFW', 'SIIPFW.bin', '', container_list_auth_type, 'KEY_ID_CONTAINER'+'_'+self._RSA_SIGN_TYPE, 0, 0 , 0), # Container Header
)
bins = os.path.join(os.path.dirname(os.path.realpath(__file__)), 'Binaries')
if self.ENABLE_TCC:
container_list.append (
('TCCC', 'TccCacheCfg.bin' if os.path.exists(os.path.join(bins, 'TccCacheCfg.bin')) else '', 'Lz4', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, self.TCC_CCFG_SIZE, 0), # TCC Cache Config
)
container_list.append (
('TCCM', 'TccCrlBinary.bin' if os.path.exists(os.path.join(bins, 'TccCrlBinary.bin')) else '', 'Lz4', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, self.TCC_CRL_SIZE, 0), # TCC Crl
)
container_list.append (
('TCCT', 'TccStreamCfg.bin' if os.path.exists(os.path.join(bins, 'TccStreamCfg.bin')) else '', 'Lz4', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, self.TCC_STREAM_SIZE, 0), # TCC Stream Config
)
if self.ENABLE_TSN:
container_list.append (
('TMAC','TsnSubRegion.bin' if os.path.exists(os.path.join(bins, 'TsnSubRegion.bin')) else '', 'Lz4', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, self.TMAC_SIZE, 0), # TSN MAC Address
)
return [container_list]
def GetOutputImages (self):
# define extra images that will be copied to output folder
img_list = ['SlimBootloader.txt',
'FlashMap.txt',
'CfgDataStitch.py',
'CfgDataDef.yaml']
return img_list
def GetImageLayout (self):
img_list = []
acm_flag = 0 if self.ACM_SIZE > 0 else STITCH_OPS.MODE_FILE_IGNOR
fwu_flag = 0 if self.ENABLE_FWU else STITCH_OPS.MODE_FILE_IGNOR
cfg_flag = 0 if len(self._CFGDATA_EXT_FILE) > 0 and self.CFGDATA_REGION_TYPE == FLASH_REGION_TYPE.BIOS else STITCH_OPS.MODE_FILE_IGNOR
if len(self._CFGDATA_EXT_FILE) > 0 and self.CFGDATA_REGION_TYPE == FLASH_REGION_TYPE.PLATFORMDATA:
img_list.extend ([
('CFGDATA_PDR.bin', [
('CFGDATA.bin', '', self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
]
),
])
img_list.extend ([
('NON_VOLATILE.bin', [
('SBLRSVD.bin', '' , self.SBLRSVD_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
]
),
('NON_REDUNDANT.bin', [
('SIIPFW.bin' , '' , self.SIIPFW_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
('VARIABLE.bin' , '' , self.VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
('MRCDATA.bin' , '' , self.MRCDATA_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
('EPAYLOAD.bin', '' , self.EPAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
('UEFIVARIABLE.bin', '' , self.UEFI_VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
('PAYLOAD.bin' , 'Lz4' , self.PAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
]
),
('REDUNDANT_A.bin', [
('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
]
),
('REDUNDANT_B.bin', [
('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
]
),
('TOP_SWAP_A.bin', [
('STAGE1B_A.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
('STAGE1A_A.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
]
),
('TOP_SWAP_B.bin', [
('STAGE1B_B.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
('STAGE1A_B.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
]
),
])
img_list.extend ([
('SlimBootloader.bin', [
('NON_VOLATILE.bin' , '' , self.NON_VOLATILE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
('NON_REDUNDANT.bin' , '' , self.NON_REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
('REDUNDANT_B.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
('REDUNDANT_A.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
('TOP_SWAP_B.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
('TOP_SWAP_A.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
]
),
])
return img_list

4
Platform/MeteorlakeBoardPkg/CfgData/CfgDataDef.yaml
View File

@@ -2,7 +2,7 @@
#
# Slim Bootloader CFGDATA Default File.
#
# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020 - 2024, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -41,8 +41,6 @@ configs:
- !include Platform/CommonBoardPkg/CfgData/CfgData_Common.yaml
- !include Platform/CommonBoardPkg/CfgData/CfgData_Tcc.yaml
- !include Platform/CommonBoardPkg/CfgData/CfgData_PayloadSelection.yaml
- !include CfgData_BootOption.yaml

102
Platform/MeteorlakeBoardPkg/CfgData/CfgData_Int_Mtlp_DDR5_CRB.dlt Normal file
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@@ -0,0 +1,102 @@
#/** @file
#
# Platform Configuration Delta File.
#
# Copyright (c) 2021 - 2024, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#**/
#
# Delta configuration values for platform ID 0x1A
#
PLATFORMID_CFG_DATA.PlatformId | 0x1A
PLAT_NAME_CFG_DATA.PlatformName | 'MtlpCRB'
GEN_CFG_DATA.PayloadId | ''
GEN_CFG_DATA.VbtImageId | 1
#FSPM UPD
MEMORY_CFG_DATA.SpdDataSel000 | 0
MEMORY_CFG_DATA.SpdDataSel010 | 0
MEMORY_CFG_DATA.SpdDataSel020 | 0
MEMORY_CFG_DATA.SpdDataSel030 | 0
MEMORY_CFG_DATA.SpdDataSel100 | 0
MEMORY_CFG_DATA.SpdDataSel101 | 0
MEMORY_CFG_DATA.SpdDataSel110 | 0
MEMORY_CFG_DATA.SpdDataSel120 | 0
MEMORY_CFG_DATA.SpdDataSel130 | 0
MEMORY_CFG_DATA.MrcFastBoot | 1
MEMORY_CFG_DATA.DqPinsInterleaved | 0
MEMORY_CFG_DATA.PchHdaEnable | 1
MEMORY_CFG_DATA.PchHdaDspEnable | 1
MEMORY_CFG_DATA.PchHdaAudioLinkHdaEnable | 1
MEMORY_CFG_DATA.DmiGen3DsPortRxPreset | {0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x02}
MEMORY_CFG_DATA.UserBd | 5
MEMORY_CFG_DATA.ActiveCoreCount | 0xFF
MEMORY_CFG_DATA.ActiveSmallCoreCount | 0xFF
MEMORY_CFG_DATA.PcieClkSrcUsage | { 0x80, 0x8, 0x70, 0xff, 0xff, 0xff, 0xB, 0xff, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x1 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch0 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch1 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch2 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch3 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch0 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch1 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch2 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch3 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.SaGv | 1
MEMORY_CFG_DATA.PchHdaAudioLinkDmicEnable | {0x1,0x1}
MEMORY_CFG_DATA.PchHdaAudioLinkSndwEnable | {0x1,0,0,0}
MEMORY_CFG_DATA.UsbTcPortEnPreMem | 0xF
MEMORY_CFG_DATA.PcieClkSrcClkReq | { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0, 0x1 }
MEMORY_CFG_DATA.TcssItbtPcie0En | 0x1
MEMORY_CFG_DATA.TcssItbtPcie1En | 0x1
MEMORY_CFG_DATA.TcssItbtPcie2En | 0x1
MEMORY_CFG_DATA.TcssItbtPcie3En | 0x1
MEMORY_CFG_DATA.TcssXhciEn | 0x1
MEMORY_CFG_DATA.TcssDma0En | 0x1
MEMORY_CFG_DATA.TcssDma1En | 0x1
MEMORY_CFG_DATA.I2cPostCodeEnable | 0x1
#FSPS UPD
SILICON_CFG_DATA.PcieRpL1Substates | {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3}
SILICON_CFG_DATA.PcieRpLtrEnable | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PcieRpClkReqDetect | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PcieRpAspm | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1}
SILICON_CFG_DATA.PcieRpMaxPayload | {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1}
SILICON_CFG_DATA.PcieRpAdvancedErrorReporting | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PtmEnabled | { 0x1, 0x1, 0x1, 0x1}
SILICON_CFG_DATA.SataPortsDevSlp | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PortUsb30Enable | {0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.CpuUsb3OverCurrentPin | {0xFF, 0xFF, 0x3, 0x3, 0xFF, 0xFF, 0xFF, 0xFF}
SILICON_CFG_DATA.PchIshI2cEnable | {0x01, 0x00, 0x00}
SILICON_CFG_DATA.PchIshGpEnable | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
SILICON_CFG_DATA.Usb2OverCurrentPin | {0x03, 0x03, 0x00, 0x00, 0x02, 0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07}
SILICON_CFG_DATA.Usb3OverCurrentPin | {0x00, 0x00, 0xFF, 0xFF, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04}
SILICON_CFG_DATA.SerialIoUartPowerGating | {0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}
SILICON_CFG_DATA.SerialIoUartDmaEnable | {0x01, 0x01, 0x01, 0x1, 0x1, 0x00, 0x00}
SILICON_CFG_DATA.SerialIoUartAutoFlow | {0x0, 0x0, 0x01, 0x01, 0x01, 0x00, 0x00}
SILICON_CFG_DATA.Usb2PhyPetxiset | {0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.Usb2PhyPredeemp | {0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PchSerialIoI2cPadsTermination | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
SILICON_CFG_DATA.SataLedEnable | 0
SILICON_CFG_DATA.EcAvailable | 0
SILICON_CFG_DATA.TurboRatioLimitRatio | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.AtomTurboRatioLimitRatio | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PchPmSlpSusMinAssert | 0x0
SILICON_CFG_DATA.PchPmSlpS3MinAssert | 0x0
SILICON_CFG_DATA.PchIshI3cEnable | 1
POWER_CFG_DATA.TurboMode | 0
POWER_CFG_DATA.EnergyEfficientTurbo | 1
POWER_CFG_DATA.ThermalMonitor | 0
POWER_CFG_DATA.MaxRatio | 4
POWER_CFG_DATA.EnableItbm | 0
POWER_CFG_DATA.Cx | 0x0
POWER_CFG_DATA.C1e | 0x0
POWER_CFG_DATA.TimedMwait | 1
POWER_CFG_DATA.PkgCStateLimit | 0
POWER_CFG_DATA.Eist | 0
POWER_CFG_DATA.Hwp | 1
POWER_CFG_DATA.EnableHwpAutoEppGrouping | 1

110
Platform/MeteorlakeBoardPkg/CfgData/CfgData_Int_Mtlp_DDR5_Rvp.dlt Normal file
View File

@@ -0,0 +1,110 @@
#/** @file
#
# Platform Configuration Delta File.
#
# Copyright (c) 2021 - 2024, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#**/
#
# Delta configuration values for platform ID 0x1
#
PLATFORMID_CFG_DATA.PlatformId | 0x1
PLAT_NAME_CFG_DATA.PlatformName | 'MtlpDDR5'
GEN_CFG_DATA.PayloadId | ''
GEN_CFG_DATA.VbtImageId | 3
# FIPS mode enablement feature
FEATURES_CFG_DATA.Features.MeFipsMode | 0
FEATURES_CFG_DATA.Features.S0ix | 0x0
#FSPM UPD
MEMORY_CFG_DATA.SpdDataSel000 | 0
MEMORY_CFG_DATA.SpdDataSel010 | 0
MEMORY_CFG_DATA.SpdDataSel020 | 0
MEMORY_CFG_DATA.SpdDataSel030 | 0
MEMORY_CFG_DATA.SpdDataSel100 | 0
MEMORY_CFG_DATA.SpdDataSel101 | 0
MEMORY_CFG_DATA.SpdDataSel110 | 0
MEMORY_CFG_DATA.SpdDataSel120 | 0
MEMORY_CFG_DATA.SpdDataSel130 | 0
MEMORY_CFG_DATA.MrcFastBoot | 1
MEMORY_CFG_DATA.DqPinsInterleaved | 0
MEMORY_CFG_DATA.PchHdaEnable | 1
MEMORY_CFG_DATA.PchHdaDspEnable | 1
MEMORY_CFG_DATA.PchHdaAudioLinkHdaEnable | 1
MEMORY_CFG_DATA.DmiGen3DsPortRxPreset | {0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07}
MEMORY_CFG_DATA.UserBd | 5
MEMORY_CFG_DATA.ActiveCoreCount | 0xFF
MEMORY_CFG_DATA.ActiveSmallCoreCount | 0xFF
MEMORY_CFG_DATA.PcieClkSrcUsage | { 0, 0x6, 0x70, 0x5, 0x8, 0x7, 0xB, 0xA, 0x9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch0 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch1 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch2 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch3 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch0 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch1 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch2 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch3 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch0 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch1 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch2 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch3 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch0 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch1 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch2 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch3 | { 0, 0}
MEMORY_CFG_DATA.TcssXhciEn | 0x1
MEMORY_CFG_DATA.Gen3LtcoEnable | 0x0
MEMORY_CFG_DATA.SaGv | 1
MEMORY_CFG_DATA.PchHdaAudioLinkDmicEnable | {0x1,0x1}
MEMORY_CFG_DATA.PchHdaAudioLinkSndwEnable | {0x1,0,0,0}
MEMORY_CFG_DATA.UsbTcPortEnPreMem | 0xF
MEMORY_CFG_DATA.PcieClkSrcClkReq | { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0, 0x1 }
MEMORY_CFG_DATA.I2cPostCodeEnable | 0x0
#FSPS UPD
SILICON_CFG_DATA.PcieRpL1Substates | {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3}
SILICON_CFG_DATA.PcieRpLtrEnable | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PcieRpClkReqDetect | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PcieRpAspm | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4}
SILICON_CFG_DATA.PcieRpMaxPayload | {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1}
SILICON_CFG_DATA.PcieRpAdvancedErrorReporting | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PtmEnabled | { 0x1, 0x1, 0x1, 0x1}
SILICON_CFG_DATA.SataPortsDevSlp | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PortUsb30Enable | {0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.CpuUsb3OverCurrentPin | {0xFF, 0xFF, 0x3, 0x3, 0xFF, 0xFF, 0xFF, 0xFF}
SILICON_CFG_DATA.PchIshI2cEnable | {0x01, 0x00, 0x00}
SILICON_CFG_DATA.PchIshGpEnable | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
SILICON_CFG_DATA.Usb2OverCurrentPin | {0x3, 0x3, 0x0, 0x0, 0x01, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07}
SILICON_CFG_DATA.Usb3OverCurrentPin | {0x00, 0x00, 0x01, 0x1, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04}
SILICON_CFG_DATA.SerialIoUartPowerGating | {0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}
SILICON_CFG_DATA.SerialIoUartDmaEnable | {0x01, 0x01, 0x01, 0x1, 0x1, 0x00, 0x00}
SILICON_CFG_DATA.SerialIoUartAutoFlow | {0x0, 0x0, 0x01, 0x01, 0x01, 0x00, 0x00}
SILICON_CFG_DATA.Usb2PhyPetxiset | {0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.Usb2PhyPredeemp | {0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PchSerialIoI2cPadsTermination | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
SILICON_CFG_DATA.SataLedEnable | 0
SILICON_CFG_DATA.TurboRatioLimitRatio | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.AtomTurboRatioLimitRatio | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PchPmSlpSusMinAssert | 0x0
SILICON_CFG_DATA.PchPmSlpS3MinAssert | 0x0
SILICON_CFG_DATA.PchIshI3cEnable | 1
SILICON_CFG_DATA.EnableTcssCovTypeA | {0x0, 0x0, 0x0, 0x0}
POWER_CFG_DATA.TurboMode | 0
POWER_CFG_DATA.EnergyEfficientTurbo | 1
POWER_CFG_DATA.ThermalMonitor | 0
POWER_CFG_DATA.MaxRatio | 4
POWER_CFG_DATA.EnableItbm | 0
POWER_CFG_DATA.Cx | 0x1
POWER_CFG_DATA.C1e | 0x1
POWER_CFG_DATA.TimedMwait | 1
POWER_CFG_DATA.PkgCStateLimit | 0xff
POWER_CFG_DATA.Eist | 0
POWER_CFG_DATA.Hwp | 1
POWER_CFG_DATA.EnableHwpAutoEppGrouping | 1

95
Platform/MeteorlakeBoardPkg/CfgData/CfgData_Int_Mtlp_LPDDR5_Rvp.dlt Normal file
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@@ -0,0 +1,95 @@
#/** @file
#
# Platform Configuration Delta File.
#
# Copyright (c) 2023 - 2024, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#**/
#
# Delta configuration values for platform ID 0x2
#
PLATFORMID_CFG_DATA.PlatformId | 0x2
PLAT_NAME_CFG_DATA.PlatformName | 'MtlpLp5'
GEN_CFG_DATA.PayloadId | ''
GEN_CFG_DATA.VbtImageId | 2
# FIPS mode enablement feature
FEATURES_CFG_DATA.Features.MeFipsMode | 0
#FSPM UPD
MEMORY_CFG_DATA.SpdDataSel000 | 1
MEMORY_CFG_DATA.SpdDataSel010 | 1
MEMORY_CFG_DATA.SpdDataSel020 | 1
MEMORY_CFG_DATA.SpdDataSel030 | 1
MEMORY_CFG_DATA.SpdDataSel100 | 1
MEMORY_CFG_DATA.SpdDataSel101 | 0
MEMORY_CFG_DATA.SpdDataSel110 | 1
MEMORY_CFG_DATA.SpdDataSel120 | 1
MEMORY_CFG_DATA.SpdDataSel130 | 1
MEMORY_CFG_DATA.MrcFastBoot | 1
MEMORY_CFG_DATA.DqPinsInterleaved | 0
MEMORY_CFG_DATA.PchHdaEnable | 1
MEMORY_CFG_DATA.PchHdaDspEnable | 1
MEMORY_CFG_DATA.PchHdaAudioLinkHdaEnable | 1
MEMORY_CFG_DATA.DmiGen3DsPortRxPreset | {0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x02}
MEMORY_CFG_DATA.UserBd | 5
MEMORY_CFG_DATA.ActiveCoreCount | 0xFF
MEMORY_CFG_DATA.ActiveSmallCoreCount | 0xFF
MEMORY_CFG_DATA.PcieClkSrcUsage | { 0, 0x6, 0x70, 0x5, 0x8, 0x7, 0xB, 0xA, 0x9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x1 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch0 | { 0x0, 0x3, 0x1, 0x2, 0x4, 0x5, 0x6, 0x7, 0x0C, 0x0D, 0x0E, 0x0F, 0x0B, 0x9, 0x0A, 0x8}
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch1 | { 0x3, 0x0, 0x1, 0x2, 0x5, 0x7, 0x6, 0x4, 0x0D, 0x0A, 0x0C, 0x0F, 0x9, 0x0B, 0x8, 0x0E}
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch2 | { 0x2, 0x1, 0x3, 0x0, 0x7, 0x5, 0x6, 0x4, 0x0C, 0x8, 0x0D, 0x0F, 0x0B, 0x0A, 0x9, 0x0E}
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch3 | { 0x4, 0x3, 0x0, 0x1, 0x5, 0x2, 0x6, 0x7, 0x8, 0x0F, 0x0C, 0x0E, 0x0A, 0x0D, 0x9, 0x0B}
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch0 | { 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, 0x0, 0x0E, 0x0D, 0x0C, 0x0F, 0x0B, 0x0A, 0x8, 0x9}
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch1 | { 0x0, 0x7, 0x3, 0x6, 0x2, 0x5, 0x1, 0x4, 0x9, 0x0A, 0x0B, 0x8, 0x0D, 0x0E, 0x0F, 0x0C}
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch2 | { 0x3, 0x0, 0x2, 0x1, 0x6, 0x5, 0x4, 0x7, 0x0F, 0x0D, 0x0C, 0x0E, 0x8, 0x0B, 0x0A, 0x9}
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch3 | { 0x2, 0x1, 0x3, 0x0, 0x6, 0x4, 0x7, 0x5, 0x0E, 0x0C, 0x0D, 0x0F, 0x9, 0x0A, 0x0B, 0x8}
MEMORY_CFG_DATA.SaGv | 1
MEMORY_CFG_DATA.PchHdaAudioLinkDmicEnable | {0x1,0x1}
MEMORY_CFG_DATA.PchHdaAudioLinkSndwEnable | {0x1,0,0,0}
MEMORY_CFG_DATA.UsbTcPortEnPreMem | 0xF
MEMORY_CFG_DATA.PcieClkSrcClkReq | { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0, 0x1 }
#FSPS UPD
SILICON_CFG_DATA.PcieRpL1Substates | {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3}
SILICON_CFG_DATA.PcieRpLtrEnable | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PcieRpClkReqDetect | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PcieRpAspm | {0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x0, 0x0, 0x0, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4}
SILICON_CFG_DATA.PcieRpMaxPayload | {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1}
SILICON_CFG_DATA.PcieRpAdvancedErrorReporting | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PtmEnabled | { 0x1, 0x1, 0x1, 0x1}
SILICON_CFG_DATA.SataPortsDevSlp | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PortUsb30Enable | {0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.CpuUsb3OverCurrentPin | {0x0, 0x1, 0x2, 0x3, 0xFF, 0xFF, 0xFF, 0xFF}
SILICON_CFG_DATA.PchIshI2cEnable | {0x01, 0x00, 0x00}
SILICON_CFG_DATA.PchIshGpEnable | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
SILICON_CFG_DATA.Usb2OverCurrentPin | {0x04, 0x05, 0x06, 0x07, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07}
SILICON_CFG_DATA.Usb3OverCurrentPin | {0x00, 0x00, 0x01, 0x1, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04}
SILICON_CFG_DATA.SerialIoUartPowerGating | {0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}
SILICON_CFG_DATA.SerialIoUartDmaEnable | {0x01, 0x01, 0x01, 0x1, 0x1, 0x00, 0x00}
SILICON_CFG_DATA.SerialIoUartAutoFlow | {0x0, 0x0, 0x01, 0x01, 0x01, 0x00, 0x00}
SILICON_CFG_DATA.Usb2PhyPetxiset | {0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.Usb2PhyPredeemp | {0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PchSerialIoI2cPadsTermination | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
SILICON_CFG_DATA.SataLedEnable | 0
SILICON_CFG_DATA.TurboRatioLimitRatio | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.AtomTurboRatioLimitRatio | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PchPmSlpSusMinAssert | 0x0
SILICON_CFG_DATA.PchPmSlpS3MinAssert | 0x0
SILICON_CFG_DATA.PchIshI3cEnable | 1
POWER_CFG_DATA.TurboMode | 0
POWER_CFG_DATA.EnergyEfficientTurbo | 1
POWER_CFG_DATA.ThermalMonitor | 0
POWER_CFG_DATA.MaxRatio | 4
POWER_CFG_DATA.EnableItbm | 0
POWER_CFG_DATA.Cx | 0
POWER_CFG_DATA.C1e | 0
POWER_CFG_DATA.TimedMwait | 1
POWER_CFG_DATA.PkgCStateLimit | 0
POWER_CFG_DATA.Eist | 0
POWER_CFG_DATA.Hwp | 1
POWER_CFG_DATA.EnableHwpAutoEppGrouping | 1

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#/** @file
#
# Platform Configuration Delta File.
#
# Copyright (c) 2021 - 2024, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#**/
#
# Delta configuration values for platform ID 0x15
#
PLATFORMID_CFG_DATA.PlatformId | 0x15
PLAT_NAME_CFG_DATA.PlatformName | 'MtlpsCRB'
GEN_CFG_DATA.PayloadId | ''
GEN_CFG_DATA.VbtImageId | 4
# FIPS mode enablement feature
FEATURES_CFG_DATA.Features.MeFipsMode | 0
FEATURES_CFG_DATA.Features.S0ix | 0x0
#FSPM UPD
MEMORY_CFG_DATA.SpdDataSel000 | 0
MEMORY_CFG_DATA.SpdDataSel010 | 0
MEMORY_CFG_DATA.SpdDataSel020 | 0
MEMORY_CFG_DATA.SpdDataSel030 | 0
MEMORY_CFG_DATA.SpdDataSel100 | 0
MEMORY_CFG_DATA.SpdDataSel101 | 0
MEMORY_CFG_DATA.SpdDataSel110 | 0
MEMORY_CFG_DATA.SpdDataSel120 | 0
MEMORY_CFG_DATA.SpdDataSel130 | 0
MEMORY_CFG_DATA.MrcFastBoot | 1
MEMORY_CFG_DATA.DqPinsInterleaved | 0
MEMORY_CFG_DATA.PchHdaEnable | 1
MEMORY_CFG_DATA.PchHdaDspEnable | 1
MEMORY_CFG_DATA.PchHdaAudioLinkHdaEnable | 1
MEMORY_CFG_DATA.DmiGen3DsPortRxPreset | {0x7,0x7,0x7,0x7,0x7,0x7,0x7,0x7}
MEMORY_CFG_DATA.UserBd | 5
MEMORY_CFG_DATA.ActiveCoreCount | 0xFF
MEMORY_CFG_DATA.ActiveSmallCoreCount | 0xFF
MEMORY_CFG_DATA.PcieClkSrcUsage | { 0, 0x6, 0x70, 0xFF, 0x8, 0x7, 0xFF, 0xFF, 0x9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch0 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch1 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch2 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch3 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch0 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch1 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch2 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch3 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch0 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch1 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch2 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch3 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch0 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch1 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch2 | { 0, 0}
MEMORY_CFG_DATA.DqsMapCpu2DramMc1Ch3 | { 0, 0}
MEMORY_CFG_DATA.SaGv | 1
MEMORY_CFG_DATA.PchHdaAudioLinkDmicEnable | {0x1,0x1}
MEMORY_CFG_DATA.PchHdaAudioLinkSndwEnable | {0x1,0,0,0}
MEMORY_CFG_DATA.UsbTcPortEnPreMem | 0xF
MEMORY_CFG_DATA.PcieClkSrcClkReq | { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0, 0x1 }
MEMORY_CFG_DATA.TcssItbtPcie0En | 0x1
MEMORY_CFG_DATA.TcssItbtPcie1En | 0x1
MEMORY_CFG_DATA.TcssItbtPcie2En | 0x1
MEMORY_CFG_DATA.TcssItbtPcie3En | 0x1
MEMORY_CFG_DATA.TcssXhciEn | 0x1
MEMORY_CFG_DATA.TcssDma0En | 0x1
MEMORY_CFG_DATA.TcssDma1En | 0x1
MEMORY_CFG_DATA.Gen3LtcoEnable | 0x0
MEMORY_CFG_DATA.I2cPostCodeEnable | 0x1
#FSPS UPD
SILICON_CFG_DATA.PcieRpL1Substates | {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3}
SILICON_CFG_DATA.PcieRpLtrEnable | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PcieRpClkReqDetect | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PcieRpAspm | {0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x2, 0x2, 0x2, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4}
SILICON_CFG_DATA.PcieRpMaxPayload | {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1}
SILICON_CFG_DATA.PcieRpAdvancedErrorReporting | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PtmEnabled | { 0x1, 0x1, 0x1, 0x1}
SILICON_CFG_DATA.SataPortsDevSlp | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PortUsb30Enable | {0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.CpuUsb3OverCurrentPin | {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}
SILICON_CFG_DATA.PchIshI2cEnable | {0x00, 0x01, 0x00}
SILICON_CFG_DATA.PchIshGpEnable | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}
SILICON_CFG_DATA.Usb2OverCurrentPin | {0x03, 0x03, 0x03, 0x00, 0x3, 0x3, 0x3, 0x3, 0x0, 0xff, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07}
SILICON_CFG_DATA.Usb3OverCurrentPin | {0x03, 0x03, 0x01, 0x1, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04}
SILICON_CFG_DATA.SerialIoUartPowerGating | {0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}
SILICON_CFG_DATA.SerialIoUartDmaEnable | {0x01, 0x01, 0x01, 0x1, 0x1, 0x00, 0x00}
SILICON_CFG_DATA.SerialIoUartAutoFlow | {0x0, 0x0, 0x01, 0x01, 0x01, 0x00, 0x00}
SILICON_CFG_DATA.Usb2PhyPetxiset | {0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.Usb2PhyPredeemp | {0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PchSerialIoI2cPadsTermination | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
SILICON_CFG_DATA.SataLedEnable | 0
SILICON_CFG_DATA.EcAvailable | 0
SILICON_CFG_DATA.EnableTcssCovTypeA | {0x0, 0x82, 0x0, 0x0}
SILICON_CFG_DATA.TurboRatioLimitRatio | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.AtomTurboRatioLimitRatio | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PchPmSlpSusMinAssert | 0x4
SILICON_CFG_DATA.PchPmSlpS3MinAssert | 0x3
SILICON_CFG_DATA.PchIshI3cEnable | 0
POWER_CFG_DATA.TurboMode | 0
POWER_CFG_DATA.EnergyEfficientTurbo | 1
POWER_CFG_DATA.ThermalMonitor | 0
POWER_CFG_DATA.MaxRatio | 4
POWER_CFG_DATA.EnableItbm | 0
POWER_CFG_DATA.Cx | 0x1
POWER_CFG_DATA.C1e | 0x1
POWER_CFG_DATA.TimedMwait | 1
POWER_CFG_DATA.PkgCStateLimit | 0xff
POWER_CFG_DATA.Eist | 0
POWER_CFG_DATA.Hwp | 1
POWER_CFG_DATA.EnableHwpAutoEppGrouping | 1

102
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#/** @file
#
# Platform Configuration Delta File.
#
# Copyright (c) 2021 - 2024, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#**/
#
# Delta configuration values for platform ID 0x14
#
PLATFORMID_CFG_DATA.PlatformId | 0x14
PLAT_NAME_CFG_DATA.PlatformName | 'MtlpsRVP'
GEN_CFG_DATA.PayloadId | ''
GEN_CFG_DATA.VbtImageId | 5
#FSPM UPD
MEMORY_CFG_DATA.SpdDataSel000 | 0
MEMORY_CFG_DATA.SpdDataSel010 | 0
MEMORY_CFG_DATA.SpdDataSel020 | 0
MEMORY_CFG_DATA.SpdDataSel030 | 0
MEMORY_CFG_DATA.SpdDataSel100 | 0
MEMORY_CFG_DATA.SpdDataSel101 | 0
MEMORY_CFG_DATA.SpdDataSel110 | 0
MEMORY_CFG_DATA.SpdDataSel120 | 0
MEMORY_CFG_DATA.SpdDataSel130 | 0
MEMORY_CFG_DATA.MrcFastBoot | 1
MEMORY_CFG_DATA.DqPinsInterleaved | 0
MEMORY_CFG_DATA.PchHdaEnable | 1
MEMORY_CFG_DATA.PchHdaDspEnable | 1
MEMORY_CFG_DATA.PchHdaAudioLinkHdaEnable | 1
MEMORY_CFG_DATA.DmiGen3DsPortRxPreset | {0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x02}
MEMORY_CFG_DATA.UserBd | 5
MEMORY_CFG_DATA.ActiveCoreCount | 0xFF
MEMORY_CFG_DATA.ActiveSmallCoreCount | 0xFF
MEMORY_CFG_DATA.PcieClkSrcUsage | { 0, 0x6, 0x70, 0x5, 0x8, 0x7, 0xB, 0xA, 0x9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch0 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch1 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch2 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc0Ch3 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch0 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch1 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch2 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.DqMapCpu2DramMc1Ch3 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
MEMORY_CFG_DATA.SaGv | 1
MEMORY_CFG_DATA.PchHdaAudioLinkDmicEnable | {0x1,0x1}
MEMORY_CFG_DATA.PchHdaAudioLinkSndwEnable | {0x1,0,0,0}
MEMORY_CFG_DATA.UsbTcPortEnPreMem | 0xF
MEMORY_CFG_DATA.PcieClkSrcClkReq | { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0, 0x1 }
MEMORY_CFG_DATA.TcssItbtPcie0En | 0x1
MEMORY_CFG_DATA.TcssItbtPcie1En | 0x1
MEMORY_CFG_DATA.TcssItbtPcie2En | 0x1
MEMORY_CFG_DATA.TcssItbtPcie3En | 0x1
MEMORY_CFG_DATA.TcssXhciEn | 0x1
MEMORY_CFG_DATA.TcssDma0En | 0x1
MEMORY_CFG_DATA.TcssDma1En | 0x1
MEMORY_CFG_DATA.I2cPostCodeEnable | 0x0
#FSPS UPD
SILICON_CFG_DATA.PcieRpL1Substates | {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3}
SILICON_CFG_DATA.PcieRpLtrEnable | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PcieRpClkReqDetect | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PcieRpAspm | {0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x0, 0x0, 0x0, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4}
SILICON_CFG_DATA.PcieRpMaxPayload | {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1}
SILICON_CFG_DATA.PcieRpAdvancedErrorReporting | {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
SILICON_CFG_DATA.PtmEnabled | { 0x1, 0x1, 0x1, 0x1}
SILICON_CFG_DATA.SataPortsDevSlp | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PortUsb30Enable | {0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.CpuUsb3OverCurrentPin | {0x0, 0x1, 0x2, 0x3, 0xFF, 0xFF, 0xFF, 0xFF}
SILICON_CFG_DATA.PchIshI2cEnable | {0x01, 0x00, 0x00}
SILICON_CFG_DATA.PchIshGpEnable | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
SILICON_CFG_DATA.Usb2OverCurrentPin | {0x04, 0x05, 0x06, 0x07, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07}
SILICON_CFG_DATA.Usb3OverCurrentPin | {0x00, 0x00, 0x01, 0x1, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04}
SILICON_CFG_DATA.SerialIoUartPowerGating | {0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}
SILICON_CFG_DATA.SerialIoUartDmaEnable | {0x01, 0x01, 0x01, 0x1, 0x1, 0x00, 0x00}
SILICON_CFG_DATA.SerialIoUartAutoFlow | {0x0, 0x0, 0x01, 0x01, 0x01, 0x00, 0x00}
SILICON_CFG_DATA.Usb2PhyPetxiset | {0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.Usb2PhyPredeemp | {0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
SILICON_CFG_DATA.PchSerialIoI2cPadsTermination | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
SILICON_CFG_DATA.SataLedEnable | 0
SILICON_CFG_DATA.EcAvailable | 0
SILICON_CFG_DATA.TurboRatioLimitRatio | {0x2A, 0x2A, 0x28, 0x28, 0x26, 0x26, 0x26, 0x26}
SILICON_CFG_DATA.AtomTurboRatioLimitRatio | {0x1F, 0x1F, 0x1F, 0x1F, 0x1C, 0x1C, 0x1C, 0x1C}
SILICON_CFG_DATA.PchPmSlpSusMinAssert | 0x4
SILICON_CFG_DATA.PchPmSlpS3MinAssert | 0x3
SILICON_CFG_DATA.PchIshI3cEnable | 0
POWER_CFG_DATA.TurboMode | 0
POWER_CFG_DATA.EnergyEfficientTurbo | 1
POWER_CFG_DATA.ThermalMonitor | 0
POWER_CFG_DATA.MaxRatio | 4
POWER_CFG_DATA.EnableItbm | 0
POWER_CFG_DATA.Cx | 0x0
POWER_CFG_DATA.C1e | 0x0
POWER_CFG_DATA.TimedMwait | 1
POWER_CFG_DATA.PkgCStateLimit | 0
POWER_CFG_DATA.Eist | 0
POWER_CFG_DATA.Hwp | 1
POWER_CFG_DATA.EnableHwpAutoEppGrouping | 1

33
Platform/MeteorlakeBoardPkg/CfgData/CfgData_Tcc_Feature.dlt
View File

@@ -1,33 +0,0 @@
## @file
#
# TCC feature Configuration Delta File.
#
# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
#
# Note: This file will come into effect only when ENABLE_TCC = 1 in BoardConfig file
# Enable TCC config data
TCC_CFG_DATA.TccEnable | 1
TCC_CFG_DATA.TccTuning | 1
TCC_CFG_DATA.TccSoftSram | 1
TCC_CFG_DATA.TccErrorLog | 1
# Enable Timed GPIO
SILICON_CFG_DATA.EnableTimedGpio0 | 1
SILICON_CFG_DATA.EnableTimedGpio1 | 1
# Enable RTCM from the boot option
BOOT_OPTION_CFG_DATA_0.BootFlags_0 | 24
BOOT_OPTION_CFG_DATA_1.ImageType_1 | 0x1E
BOOT_OPTION_CFG_DATA_2.BootFlags_2 | 24
BOOT_OPTION_CFG_DATA_3.ImageType_3 | 0x1E
BOOT_OPTION_CFG_DATA_4.BootFlags_4 | 24
BOOT_OPTION_CFG_DATA_5.ImageType_5 | 0x1E
BOOT_OPTION_CFG_DATA_6.BootFlags_6 | 24
BOOT_OPTION_CFG_DATA_7.ImageType_7 | 0x1E

14
Platform/MeteorlakeBoardPkg/CfgData/CfgData_Tsn_Feature.dlt
View File

@@ -1,14 +0,0 @@
## @file
#
# TSN feature Configuration Delta File.
#
# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
#
SILICON_CFG_DATA.PchTsnEnable | 1
# TSN Multi-VC is not enabled by default
SILICON_CFG_DATA.PchTsnMultiVcEnable | 0

29
Platform/MeteorlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
View File

@@ -982,7 +982,6 @@ PlatformUpdateAcpiTable (
VOID *FspHobList;
PLATFORM_DATA *PlatformData;
FEATURES_CFG_DATA *FeaturesCfgData;
TCC_CFG_DATA *TccCfgData;
EFI_STATUS Status;
EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *FadtPointer;
@@ -1049,14 +1048,6 @@ PlatformUpdateAcpiTable (
} else if (Table->Signature == SIGNATURE_32 ('R', 'T', 'C', 'T')) {
DEBUG ((DEBUG_INFO, "Find RTCT table\n"));
if (FeaturePcdGet (PcdTccEnabled)) {
TccCfgData = (TCC_CFG_DATA *) FindConfigDataByTag(CDATA_TCC_TAG);
if ((TccCfgData != NULL) && (TccCfgData->TccEnable != 0)) {
Status = UpdateAcpiRtctTable(Table);
DEBUG ( (DEBUG_INFO, "Updated Rtct Table entries in AcpiTable status: %r\n", Status) );
return Status;
}
}
return EFI_UNSUPPORTED;
} else if (Table->Signature == EFI_BDAT_TABLE_SIGNATURE) {
FspHobList = GetFspHobListPtr ();
@@ -1384,7 +1375,6 @@ PlatformUpdateAcpiGnvs (
DPTF_NVS_AREA *DptfNvs;
FSPS_UPD *FspsUpd;
FSP_S_CONFIG *FspsConfig;
TCC_CFG_DATA *TccCfgData;
SILICON_CFG_DATA *SiCfgData;
FEATURES_CFG_DATA *FeaturesCfgData;
UINT8 Index;
@@ -1394,9 +1384,6 @@ PlatformUpdateAcpiGnvs (
UINT32 Data32;
GPIO_GROUP GroupToGpeDwX[3];
UINT32 GroupDw[3];
CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;
CPUID_PROCESSOR_FREQUENCY_EBX Ebx;
PLATFORM_DATA *PlatformData;
GlobalNvs = (GLOBAL_NVS_AREA *)GnvsIn;
ZeroMem (GlobalNvs, sizeof (GLOBAL_NVS_AREA));
@@ -1846,20 +1833,4 @@ PlatformUpdateAcpiGnvs (
PlatformNvs->PpmFlags = CpuNvs->PpmFlags;
SocUpdateAcpiGnvs ((VOID *)GnvsIn);
// TCC mode enabling
if (FeaturePcdGet (PcdTccEnabled)) {
TccCfgData = (TCC_CFG_DATA *) FindConfigDataByTag(CDATA_FEATURES_TAG);
if ((TccCfgData != NULL) && (TccCfgData->TccEnable != 0)) {
AsmCpuid (CPUID_TIME_STAMP_COUNTER, NULL, &Ebx.Uint32, NULL, NULL);
AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
}
// If TCC is enabled, use the TCC policy from subregion
PlatformData = (PLATFORM_DATA *)GetPlatformDataPtr ();
if((PlatformData != NULL) && PlatformData->PlatformFeatures.TccDsoTuning){
PlatformNvs->Rtd3Support = PlatformData->PlatformFeatures.TccRtd3Support;
PlatformNvs->LowPowerS0Idle = PlatformData->PlatformFeatures.TccLowPowerS0Idle;
}
}
}

31
Silicon/MeteorlakePkg/FspBin/FspBin.inf Normal file
View File

@@ -0,0 +1,31 @@
## @file
# File to describe FSP repo information
#
# Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
##
[UserExtensions.SBL."CloneRepo"]
REPO = https://github.com/intel/FSP.git
COMMIT = cc6399e8c759ad4ed83c2d6ea568fd918fc9bc06
[UserExtensions.SBL."CopyList"]
MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.fd : Silicon/MeteorlakePkg/FspBin/FspRel.bin
MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.fd : Silicon/MeteorlakePkg/FspBin/FspDbg.bin
MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.bsf : Silicon/MeteorlakePkg/FspBin/Fsp.bsf
MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspUpd.h : Silicon/MeteorlakePkg/Include/FspUpd.h
MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FsptUpd.h : Silicon/MeteorlakePkg/Include/FsptUpd.h
MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspmUpd.h : Silicon/MeteorlakePkg/Include/FspmUpd.h
MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspsUpd.h : Silicon/MeteorlakePkg/Include/FspsUpd.h
MeteorLakeFspBinPkg/IoT/MeteorLake/Include/MemInfoHob.h : Silicon/MeteorlakePkg/Include/MemInfoHob.h
MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/VbtMtlpCrb.dat : Platform/MeteorlakeBoardPkg/VbtBin/VbtMtlpCrb.dat
MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/VbtMtlpLp5.dat : Platform/MeteorlakeBoardPkg/VbtBin/VbtMtlpLp5.dat
MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/VbtMtlpRvp.dat : Platform/MeteorlakeBoardPkg/VbtBin/VbtMtlpRvp.dat
MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/VbtMtlpsCrb.dat : Platform/MeteorlakeBoardPkg/VbtBin/VbtMtlpsCrb.dat
MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/VbtMtlpsRvp.dat : Platform/MeteorlakeBoardPkg/VbtBin/VbtMtlpsRvp.dat
MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/Vbt.json : Platform/MeteorlakeBoardPkg/VbtBin/Vbt.json
FSP_License.pdf : Silicon/MeteorlakePkg/Fsp/FSP_License.pdf

25
Silicon/MeteorlakePkg/Microcode/Microcode.inf Normal file
View File

@@ -0,0 +1,25 @@
## @file
#
# Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = Microcode
FILE_GUID = 197DB236-F856-4924-90F8-CDF12FB875F3
MODULE_TYPE = USER_DEFINED
VERSION_STRING = 1.0
[Sources]
m_e6_a06a4_0000001c.mcb
[UserExtensions.SBL."CloneRepo"]
REPO = https://github.com/slimbootloader/firmwareblob.git
COMMIT = 57cc7eb0da0c244e5e527d0c5ee571d9234c03da
[UserExtensions.SBL."CopyList"]
Microcode/Meteorlake/m_e6_a06a4_0000001c.pdb : Silicon/MeteorlakePkg/Microcode/m_e6_a06a4_0000001c.mcb