You've already forked slimbootloader.github.io
mirror of
https://github.com/Dasharo/slimbootloader.github.io.git
synced 2026-03-06 15:26:36 -08:00
Deploy slimbootloader/documentation to github.com/slimbootloader/slimbootloader.github.io.git:master
This commit is contained in:
randylintw (via Travis CI)
BIN
_images/ari-setup.jpg
Normal file
BIN
_images/ari-setup.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 213 KiB |
118
_sources/supported-hardware/arlh-ari.rst.txt
Normal file
118
_sources/supported-hardware/arlh-ari.rst.txt
Normal file
@@ -0,0 +1,118 @@
|
||||
.. _arlh-aii-board:
|
||||
|
||||
|ARLH-ARI| Board
|
||||
----------------
|
||||
|
||||
The |ARLH-ARI| Reference Design is a platform developed by Intel, featuring Core Ultra Series 2 Inel processors, specifically tailored for network and edge applications.
|
||||
|
||||
|
||||
Prerequisites
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
To start developing |SPN|, the following equipment, software and environments are required:
|
||||
|
||||
* |Arrow Island Reference Design Board|
|
||||
* DediProg SF600 Programmer
|
||||
* Mirco USB cable
|
||||
* Windows host or Linux host (see :ref:`running-on-windows` or :ref:`running-on-linux` for details)
|
||||
* Internet access
|
||||
|
||||
.. |Arrow Island Reference Design Board| raw:: html
|
||||
|
||||
<a href="https://builders.intel.com/solutionslibrary/intel-core-ultra-mobile-processor-series-2-reference-design-based-on-intel-edge-scalable-design-arrow-island" target="_blank">Arrow Island Reference Design Board</a>
|
||||
|
||||
|
||||
Board Setup
|
||||
^^^^^^^^^^^
|
||||
|
||||
.. image:: /images/ari-setup.jpg
|
||||
:width: 600
|
||||
:alt: Arrow Island Board Setup
|
||||
:align: center
|
||||
|
||||
|
||||
Before You Start
|
||||
^^^^^^^^^^^^^^^^
|
||||
|
||||
.. warning:: As you plan to reprogram the SPI flash, it's a good idea to backup the pre-installed BIOS image first.
|
||||
|
||||
Boot the board and enter BIOS setup menu to get familiar with the board features and settings.
|
||||
|
||||
For |ARLH-ARI|, serial port connector is labelled DEBUG on board
|
||||
|
||||
.. note:: Configure host PuTTY or minicom to 115200bps, 8N1, no hardware flow control.
|
||||
|
||||
|
||||
Building
|
||||
^^^^^^^^
|
||||
|
||||
|Arrow Island Reference Design Board| is based on Intel |ARLH|. To build::
|
||||
|
||||
python BuildLoader.py build arlh
|
||||
|
||||
The output image is generated under ``Outputs\arlh`` directory.
|
||||
|
||||
|
||||
Stitching
|
||||
^^^^^^^^^
|
||||
|
||||
Option 1: Stitch |SPN| image with factory BIOS IFWI image using ``StitchLoader.py``::
|
||||
|
||||
python Platform\ArrowlakeBoardPkg\Script\StitchLoader.py -i <BIOS_IFWI_IMAGE> -s Outputs\arlh\SlimBootloader.bin -o <SBL_IFWI_IMAGE> -p 0xAA00001B
|
||||
|
||||
<BIOS_IFWI_IMAGE> : Input file. Factory BIOS extracted from Arrow Island board.
|
||||
<SBL_IFWI_IMAGE> : Output file. New IFWI image with SBL in BIOS region.
|
||||
-p <value> : 4-byte platform data for platform ID (e.g. 1B) and debug UART port index (e.g. 00).
|
||||
|
||||
Refer to :ref:`stitch-tool` for more details.
|
||||
|
||||
.. note:: StitchLoader.py script works only if Boot Guard in the base image is not enabled, and the silicon is not fused with Boot Guard enabled.
|
||||
If Boot Guard is enabled, please use StitchIfwi.py script instead.
|
||||
|
||||
Option 2: Stitch |SPN| image with firmware ingredients using ``StitchIfwi.py``:
|
||||
|
||||
.. note:: Ensure all the stitch components are ready in the stitching folder.
|
||||
|
||||
::
|
||||
|
||||
python Platform\ArrowlakeBoardPkg\Script\StitchIfwi.py -b legacy -s Outputs\arlh\Stitch_Components.zip -c Platform\ArrowlakeBoardPkg\Script\StitchIfwiConfig_arlh.py -w stitching -p arlh -o isd -d 0xAA00001B
|
||||
|
||||
The output image is generated under current working directory.
|
||||
|
||||
|
||||
Flashing
|
||||
^^^^^^^^
|
||||
|
||||
Flash the generated SBL_IFWI_IMAGE to |ARLH-ARI| board using a SPI programmer. Header J9A1 on the board should be used.
|
||||
|
||||
.. note::
|
||||
|
||||
Please ensure:
|
||||
|
||||
#. The alignment/polarity when connecting Dediprog to the board.
|
||||
#. The power to the board is turned **off** while the programmer is connected (even when not in use).
|
||||
#. The programmer is set to update the flash from offset 0x0.
|
||||
|
||||
|
||||
SlimBootloader Binary for Capsule Image
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The ``SlimBootloader.bin`` image generated from the build steps above can be used to create a capsule image for firmware update::
|
||||
|
||||
python BootloaderCorePkg\Tools\GenCapsuleFirmware.py -p BIOS Outputs\arlh\SlimBootloader.bin -k <priv_key> -o FwuImage.bin
|
||||
|
||||
Refer to :ref:`generate-capsule` for more details.
|
||||
|
||||
|
||||
Triggering Firmware Update
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Refer to :ref:`firmware-update` on how to trigger firmware update flow.
|
||||
|
||||
Below is an example to trigger firmware update in |SPN| shell:
|
||||
|
||||
#. Copy ``FwuImage.bin`` into root directory on FAT partition of a USB drive
|
||||
#. Boot and press any key to enter |SPN| shell
|
||||
#. Type command ``fwupdate`` from shell
|
||||
|
||||
Observe |SPN| resets the platform and performs update flow. It resets *multiple* times to complete the update process.
|
||||
@@ -337,7 +337,7 @@ function to retrieve the location.</p>
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -204,7 +204,7 @@
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -242,7 +242,7 @@ to by the Firmware Performance Data Table (FPDT). Refer to ACPI Specification fo
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -142,7 +142,7 @@ and can also load the boot image from a raw partition using the LBA number.</p>
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -463,7 +463,7 @@ components inside it</p>
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -520,7 +520,7 @@ for GPP_A3, and GPP_A4</p>
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -153,7 +153,7 @@ and agrees to them.</p>
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -434,7 +434,7 @@ status. If the breakpoint is set properly, then it should as below:</p></li>
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -335,7 +335,7 @@
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -220,7 +220,7 @@ below image, 0x3f8000 is the LBA offset of Container image.</p>
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -287,7 +287,7 @@
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -142,7 +142,7 @@ newer Intel silicons.</p>
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -239,7 +239,7 @@
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -152,7 +152,7 @@
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -190,7 +190,7 @@ for verbosity. One can control debug messages in multiple ways by modifying the
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -301,7 +301,7 @@ will be allocated to the payload.</p></li>
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -145,7 +145,7 @@
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
@@ -178,7 +178,7 @@
|
||||
|
||||
<div role="contentinfo">
|
||||
<p>© Copyright 2018 - 2025, Intel Corporation.
|
||||
<span class="lastupdated">Last updated on Apr 23, 2025.
|
||||
<span class="lastupdated">Last updated on May 13, 2025.
|
||||
</span></p>
|
||||
</div>
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user