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275 lines
13 KiB
C
275 lines
13 KiB
C
/**
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* @file
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* @brief OpenSIL APOB struct definitions
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*/
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/* Copyright 2021-2023 Advanced Micro Devices, Inc. All rights reserved. */
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// SPDX-License-Identifier: MIT
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#pragma once
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/**********************************************************************************************************************
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* Declare macros here
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*
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*/
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#define MAX_SOCKETS_SUPPORTED 2 ///< Max number of sockets in system
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#define MAX_DIES_PER_SOCKET 4 ///< Max number of dies per socket
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#define MAX_CHANNELS_PER_DIE 2 ///< Max Channels per die
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#define MAX_CHANNELS_PER_SOCKET 12 ///< Max Channels per sockets
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#define MAX_DIMMS_PER_CHANNEL 2 ///< Max DIMMs on a memory channel (independent of platform)
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#define MAX_RBS_PER_SOCKET 12 ///< Max number of root bridges per socket
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#define MAX_THREADS_PER_CORE 2
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#define MAX_COMPLEXES_PER_CCD 2 ///< Program dependent
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#define ABL_APOB_MAX_SOCKETS_SUPPORTED 2 ///< Max number of sockets in system
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#define ABL_APOB_MAX_DIES_PER_SOCKET 1 ///< Max dies per socket
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#define ABL_APOB_MAX_CHANNELS_PER_SOCKET 12 ///< Max Channels per sockets
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#define ABL_APOB_MAX_CHANNELS_PER_DIE 12 ///< Max channels per die
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#define ABL_APOB_MAX_DIMMS_PER_CHANNEL 2 ///< Max dimms per die
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#define ABL_APOB_MAX_CS_PER_CHANNEL 4 ///< Max CS per channel
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#define MAX_PMU_SMB_SIZE 0x400 ///< Max PMU SMB size
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#define APOB_BASE_ADDRESS CONFIG_PLAT_APOB_ADDRESS
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#define CCX_MAX_SOCKETS ABL_APOB_MAX_SOCKETS_SUPPORTED
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#define CCX_MAX_DIES_PER_SOCKET 1 // Program dependent
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#define CCX_MAX_COMPLEXES_PER_DIE 2 // Program dependent
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#define CCX_MAX_CORES_PER_COMPLEX 8
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#define CCX_MAX_THREADS_PER_CORE 2
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#define CCX_NOT_PRESENT (0xFF)
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#define MAX_CORES_PER_COMPLEX 8
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#define MAX_CCDS_PER_DIE 12 ///< Program dependent
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#define MAX_APOB_CHANNELS_PER_DIE 12 ///< Max channels per die
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#define MAX_APOB_MEM_NB_BLOCK_SIZE 1528
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#define MAX_APOB_MEM_DCT_BLOCK_SIZE 976
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#define MAX_APOB_MEM_TIMINGS_BLOCK_SIZE 360
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#define MAX_APOB_MEM_CHANNEL_BLOCK_SIZE 450
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#define MAX_APOB_MEM_DIE_BLOCK_SIZE 108
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/**
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* @brief Memory DMI Type 17 - for memory use
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*
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*/
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typedef struct {
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uint8_t Socket:2; ///< Socket ID
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uint8_t Channel:4; ///< Channel ID
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uint8_t Dimm:1; ///< DIMM ID
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uint8_t DimmPresent:1; ///< Dimm Present
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uint8_t SpdAddr; ///< SPD Address
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uint16_t Handle; ///< The temporary handle, or instance number, associated
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///< with the structure
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uint16_t ConfigSpeed; ///< Configured memory clock speed
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uint16_t ConfigVoltage; ///< Configured voltage for this device, in millivolt
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} APOB_MEM_DMI_PHYSICAL_DIMM;
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/**
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* @brief Memory DMI Type 20 - for memory use
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*
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*/
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typedef struct {
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uint8_t Socket:2; ///< Socket ID
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uint8_t Channel:4; ///< Channel ID
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uint8_t Dimm:1; ///< DIMM ID
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uint8_t DimmPresent:1; ///< Dimm Present
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uint8_t Interleaved:1; ///< Interleaving enabled
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uint8_t Reserved:7; ///< Reserved
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uint16_t MemoryDeviceHandle; ///< The handle, or instance number, associated with
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///< the Memory Device structure to which this address
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///< range is mapped.
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uint32_t StartingAddr; ///< The physical address, in kilobytes, of a range
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///< of memory mapped to the referenced Memory Device.
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uint32_t EndingAddr; ///< The handle, or instance number, associated with
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///< the Memory Device structure to which this address
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///< range is mapped.
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/**
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* @brief Ext Starting Address
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* @details Union for 64 bit address or struct of upper and lower 32 bits
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*
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*/
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union {
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uint64_t ExtStartingAddr; ///< The physical address, in bytes, of a range of
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///< memory mapped to the referenced Memory Device.
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/**
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* @brief Struct for the address upper and lower 32 bits
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*
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*/
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struct {
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uint32_t ExtStartingAddrLow; ///< Lower 32 bits of the address
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uint32_t ExtStartingAddrHigh; ///< Upper 32 bits of the address
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} ExtStartingAddrForPsp;
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} UnifiedExtStartingAddr;
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/**
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* @brief Ext Ending Address
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* @details Union for 64 bit address or struct of upper and lower 32 bits
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*
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*/
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union {
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uint64_t ExtEndingAddr; ///< The physical ending address, in bytes, of the last of
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///< a range of addresses mapped to the referenced Memory Device
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/**
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* @brief Struct for the address upper and lower 32 bits
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*
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*/
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struct {
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uint32_t ExtEndingAddrLow; ///< Lower 32 bits of the address
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uint32_t ExtEndingAddrHigh; ///< Upper 32 bits of the address
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} ExtEndingAddrForPsp;
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} UnifiedExtEndingAddr;
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} APOB_MEM_DMI_LOGICAL_DIMM;
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/**
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* @brief Post Package Repair List Entry struct
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*
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*/
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typedef union DPPRCL_REPAIR_REPORT_ENTRY_V2 {
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struct {
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uint32_t Valid: 1 ; ///< [0:0] Valid entry
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uint32_t Status: 8 ; ///< [8:1] Status
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uint32_t RepairType: 3 ; ///< [11:9] Repair Type 0 - Soft,
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///< 1 - Hard, 2 - MBIST SoftPPR
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uint32_t ErrorCause: 3 ; ///< [14:12] Cause of error which initiated this repair
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uint32_t DeviceTypeRepaired : 1; ///< [15:15] Device Type which was repaird. 0 - DDR, 1 - HBM
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uint32_t DeviceWidth: 5 ; ///< [20:16] Device WIdth
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uint32_t TargetDevice: 5 ; ///< [25:21] Target Device
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uint32_t BankAddress: 5 ; ///< [30:26] Bank Address
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uint32_t Reserved_0: 1 ; ///< [31:31] Reserved
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uint32_t Socket: 3 ; ///< [2:0] Socket Number
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uint32_t Channel: 4 ; ///< [6:3] DDR Channel
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uint32_t SubChannel: 1 ; ///< [7:7] Sub Channel 0 - Subchannel A, 1 - Subchannel B
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uint32_t ChipSelect: 2 ; ///< [9:8] ChipSelect 0 -3
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uint32_t RankMultiplier: 3 ; ///< [12:10] Rank Multiplier
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uint32_t RowAddress: 18 ; ///< [30:13] RowAddress
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uint32_t Reserved_1: 1 ; ///< [31:31] Reserved
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} ddr;
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struct {
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uint32_t Valid: 1 ; ///< [0:0] Valid entry
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uint32_t Status: 8 ; ///< [8:1] Status
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uint32_t RepairType: 3 ; ///< [11:9] Repair Type 0 - Soft,
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///< 1 - Hard, 2 - MBIST SoftPPR
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uint32_t ErrorCause: 3 ; ///< [14:12] Cause of error which initiated this repair
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uint32_t DeviceTypeRepaired : 1; ///< [15:15] Device Type which was repaird. 0 - DDR, 1 - HBM
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uint32_t Socket : 3; ///< [18:16] Socket
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uint32_t Channel : 4; ///< [22:19] Channel
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uint32_t SubChannel : 1; ///< [23:23] SubChannel (DDR5)
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uint32_t MfrId : 4; ///< [27:24] Manufacturer Id
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uint32_t Reserved_0 : 4; ///< [31:28] MBZ
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uint32_t BankAddress: 5 ; ///< [4:0] Bank Address
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uint32_t Column : 5; ///< [9:5] Column Address
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uint32_t Row : 15; ///< [24:10] Row Address
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uint32_t Reserved_1:7; ///< [31:25] Reserved for hbm PPR repair update
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} hbm;
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} DPPRCL_REPAIR_REPORT_ENTRY_V2;
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#define APOB_MAX_DPPRCL_ENTRY 64 ///< Max post package repair list entires
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#define APOB_MAX_DPPRCL_SOCKETS 1 ///< Max post package repair list sockets
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#define APOB_MAX_DPPRCL_CHANNELS 1 ///< Max post package repair list channels
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/// Max post package repair list entries based on max sockets and channels
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#define APOB_MAX_DPPRCL_ENTRIES APOB_MAX_DPPRCL_SOCKETS*APOB_MAX_DPPRCL_CHANNELS
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/**
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* @brief Post Package Repair List
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* @details Contains all Post Package Repair List Entries
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*
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*/
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typedef struct _APOB_DPPRCL_STRUCT_V2 {
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DPPRCL_REPAIR_REPORT_ENTRY_V2 DppRclReportEntry [APOB_MAX_DPPRCL_ENTRY];
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} APOB_DPPRCL_STRUCT_V2;
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/**
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* @brief DDR Post Package Repair Struct
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*
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*/
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typedef struct _APOB_DPPR_STRUCT_V2 {
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bool PprResultsValid; /// Indicates that the PPR results are valid
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uint8_t Reserved;
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uint16_t Reserved1;
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APOB_DPPRCL_STRUCT_V2 Channel [APOB_MAX_DPPRCL_ENTRIES];
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} APOB_DPPR_STRUCT_V2;
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/**
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* @brief Interleaving settings
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*
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*/
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typedef union {
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/**
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* @brief Bitfields of Interleaving Settings
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*
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*/
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struct {
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uint32_t ChannelIntlv:8; ///< Bit map for channel interleave setting
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uint32_t DieIntlv:2; ///< Bit map for die interleave setting
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uint32_t SocketIntlv:1; ///< Socket interleave setting
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uint32_t :21; ///< Reserved
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} Field;
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uint32_t Value; ///< Interleaving Settings as 32 bit value
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} INTLV_SETTING;
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/**
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* @brief APOB Memory Config Info
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*
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*/
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typedef struct _APOB_MEM_CFG_INFO {
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/**
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* @brief Union for status enabled flag or configured status value
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*
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*/
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union {
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bool Enabled; ///< Status.Enabled - TRUE: Enabled.
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uint16_t Value; ///< Status.Value - Configured value.
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} Status;
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uint16_t StatusCode; ///< Status Code.
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} APOB_MEM_CFG_INFO;
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/**
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* @brief APOB Memory General Config Info Struct
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*
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*/
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typedef struct {
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uint8_t ApobTypeHeader [48]; ///< APOB Type Header
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uint32_t BootMediaTypeInfo; ///< BootMediaTypeInfo
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uint16_t MemClkFreq; ///< Data from MemClkFreq: 667/800/933/1067/1200/1333/1467/1600 Mhz
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uint16_t DdrMaxRate; ///< UMC DdrMaxRate
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bool EccEnable [ABL_APOB_MAX_CHANNELS_PER_DIE]; ///< ECC enabled or Disabled per channel. ie. Channel 0 or Channel 1
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bool NvDimmInstalled[ABL_APOB_MAX_CHANNELS_PER_DIE]; ///< NVDIMM presence per channel. ie. Channel 0 or Channel 1
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bool ChannelIntlvEn; ///< DIMM channel interleave status
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uint8_t Reserved1[7]; ///< Reserved
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APOB_DPPR_STRUCT_V2 DdrPostPackageRepair; ///< DDR Post package repaair
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INTLV_SETTING InterLeaveCurrentMode; ///< Current interleave mode
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INTLV_SETTING InterLeaveCapability; ///< Capability of interleave
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uint32_t InterLeaveSize; ///< Interleaving size
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uint32_t DimmSize[ABL_APOB_MAX_CHANNELS_PER_DIE][ABL_APOB_MAX_DIMMS_PER_CHANNEL]; ///< 2d array of DIMM sizes per
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///< channel per die
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APOB_MEM_CFG_INFO ChipselIntlv[ABL_APOB_MAX_CHANNELS_PER_DIE]; ///< Chipselect interleaving per
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///< channel
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APOB_MEM_CFG_INFO DramEcc; ///< DRAM ECC Configuration
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APOB_MEM_CFG_INFO DramParity; ///< DRAM Parity Configuration
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APOB_MEM_CFG_INFO AutoRefFineGranMode; ///< AutoRefresh Fine Granularity Mode Configuration
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APOB_MEM_CFG_INFO MbistTestEnable; ///< MBIST Test Enable Configuration
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APOB_MEM_CFG_INFO MbistAggressorEnable; ///< MBIST Aggressor Enable Configuration
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APOB_MEM_CFG_INFO MbistPerBitSecondaryDieReport; ///< MBIST Per Bit Secondary Die Report Configuration
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APOB_MEM_CFG_INFO DramTempControlledRefreshEn; ///< DRAM Temperature Controlled Refresh Configuration
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APOB_MEM_CFG_INFO UserTimingMode; ///< User Timing Mode Configuration
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APOB_MEM_CFG_INFO UserTimingValue; ///< User Timing Value Configuration
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APOB_MEM_CFG_INFO MemBusFreqLimit; ///< Memory Bus Frequency Limit Configuration
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APOB_MEM_CFG_INFO EnablePowerDown; ///< Enable Power Down Configuration
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APOB_MEM_CFG_INFO DramDoubleRefreshRate; ///< DRAM Double Refresh Rate Configuration
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APOB_MEM_CFG_INFO PmuTrainMode; ///< PMU Training Mode Configuration
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APOB_MEM_CFG_INFO EccSymbolSize; ///< ECC Symbol Size Configuration
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APOB_MEM_CFG_INFO UEccRetry; ///< Uncorrectable ECC Retry Configuration
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APOB_MEM_CFG_INFO IgnoreSpdChecksum; ///< Ignore SPD Checksum Configuration
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APOB_MEM_CFG_INFO EnableBankGroupSwapAlt; ///< Bank Group Swap Alt Control Configuration
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APOB_MEM_CFG_INFO EnableBankGroupSwap; ///< Bank Group Swap Control Configuration
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APOB_MEM_CFG_INFO DdrRouteBalancedTee; ///< Motherboard DDR Routing Configuration
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APOB_MEM_CFG_INFO NvdimmPowerSource; ///< NVDIMM Power Source Configuration 1: device, 2: host
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APOB_MEM_CFG_INFO OdtsCmdThrotEn; ///< ODTS Command Throttle Configuration
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APOB_MEM_CFG_INFO OdtsCmdThrotCyc; ///< ODTS Command Throttle Cycle Configuration
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} APOB_MEM_GENERAL_CONFIGURATION_INFO_TYPE_STRUCT;
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