Initial commit.

Signed-off-by: Paul Grimes <paul.grimes@amd.com>

.gitattributes

@@ -0,0 +1 @@
+AMD_Simnow/0ACQT007.FD filter=lfs diff=lfs merge=lfs -text

.gitignore

@@ -0,0 +1,19 @@
+docs/Code-html/
+docs/Api-html/
+Documentation/CodeSpec/build/
+Documentation/ApiSpec/build/
+Build
+*/Build
+util/kconfig/lib/__pycache__/
+cscope.files
+cscope.in.out
+cscope.out
+cscope.po.out
+tags
+*.swp
+flist-SilCfg-AllYes.txt
+reserved.txt
+xUSL/NBIO/FLI/NbioPcieStraps.h.MOVETORESRV
+xUSL/NBIO/FLI/NbioPcieStraps.h.BAK
+xUSL/Mpio/Rs/MpioPcieStrapsRs.h.BAK
+xUSL/Mpio/Rs/MpioPcieStrapsRs.h.MOVETORESRV

CODEOWNERS

@@ -0,0 +1,10 @@
+# openSIL CODEOWNERS
+#
+# Code owners are automatically requested for review when someone opens a pull request that modifies code that they own
+#
+# Default Reviewers
+#
+# Internal Members: Include everyone in the "AMD Developers" team
+# External Collaborators: From organizations who have signed the CLA and part of the development team
+#
+# @TODO: add CODEOWNERS

Documentation/readme.md

@@ -0,0 +1 @@
+Formal documentation is in final review and will be uploaded to this directory when available.

Include/Sil-api.h

@@ -0,0 +1,82 @@
+/* Copyright 2021-2023 Advanced Micro Devices, Inc. All rights reserved.    */
+// SPDX-License-Identifier: MIT
+
+/**
+ * @file  Sil-api.h
+ * @brief
+ *  This file is used to declare the Host-API functions, variables,
+ *  common definitions, constants and macros available to the Host and
+ *  openSIL modules.
+ *
+ *
+ */
+/**
+ * @cond API_Doc
+ *
+ *  @defgroup MODULES_IP         IP Modules Interfacing
+ *
+ * @endcond
+ *
+ *
+ * @cond FullCode_Doc
+ * @defgroup Host_group Hostgroup: top level page for openSIL.
+ *
+ * @endcond
+ */
+
+#pragma once
+#include <stddef.h>
+
+/** HOST_DEBUG_SERVICE
+ *  @brief This is the description for the Host provided debug output function.
+ */
+  typedef void (*HOST_DEBUG_SERVICE) (
+  size_t      MsgLevel,
+  const char  *SilPrefix,
+  const char  *Message,
+  const char  *Function,
+  size_t      Line,
+  ...
+  );
+
+/** @brief Return values
+ *
+ * @details The openSIL routines will never 'hang'. They will always return with a
+ * code or value indicating the state of the outcome of the operation. For
+ * functions returning status, these are the defined status codes for
+ * all openSIL code.
+ * Starting from value 0xF0, this enum defines reset request types from openSIL IPs.
+ */
+typedef enum {
+  SilPass = 0,                    ///< Success, function finished without error.
+  SilUnsupportedHardware,         ///< Fail, SoC does not support the function.
+  SilUnsupported,                 ///< Fail, the request is not supported.
+  SilInvalidParameter,            ///< Fail, the function was called with an
+                                  ///<   invalid parameter.
+  SilAborted,                     ///< Fail, the processing incurred an error
+                                  ///<   causing the processing to be aborted.
+                                  ///<   Host should take action.
+  SilOutOfResources,              ///< Fail, assignment of memory block failed,
+                                  ///<   due to depletion of available resources
+  SilNotFound,                    ///< Fail, The element was not found. Recheck
+                                  ///<   the ID unique identifier used.
+  SilOutOfBounds,                 ///< Fail, there is an out of bounds condition
+  SilDeviceError,                 ///< Fail, device being initialized reported
+                                  ///<   an error. Check if the IP output block
+                                  ///<   has more information.
+
+  SilResetRequestColdImm = 0xF0,  ///< The following values indicate a special
+                                  ///<   condition requiring the Host to perform
+                                  ///<   a system reset
+                                  ///< requesting Host do immediate cold reset
+  SilResetRequestColdDef,         ///< requesting Host do deferred cold reset
+  SilResetRequestWarmImm,         ///< requesting Host do immediate warm reset
+  SilResetRequestWarmDef,         ///< requesting Host do deferred warm reset
+} SIL_STATUS;
+
+/* *********************************************************************************************************************
+ * Declare common variables here
+ */
+
+
+

Include/xSIM-api.h

@@ -0,0 +1,395 @@
+/* Copyright 2023 Advanced Micro Devices, Inc. All rights reserved. */
+// SPDX-License-Identifier: MIT
+/**
+ * @file
+ * @brief xSIM-Host  API definitions
+ *
+ * @details This file is used to declare the API functions, variables and
+ * macros needed by the Host to perform the early initialization
+ * of the AMD silicon.
+ */
+/**
+ * @cond API_Doc
+ * @page TopXsim  Silicon Initialization Module (xSIM)
+ *   'xSIM' is the AMD x86 Silicon Initialization Module.
+ *   This module is responsible for the very early (basic) Si initialization
+ *   comming off of reset. It places the silicon into a state where more
+ *   general activities can be performed.
+ *
+ *   The xSIM folder contains the general infrastructure functions,
+ *   the early initialization functions and is also the central translation
+ *   point for 'SoC' to list of 'IP's. Actual IP programming is done by the xUSL.
+ *
+ *   See the 'Files - @ref xsim-api.h' section of this document for
+ *   further details.
+ *
+ *   SocList - The platform maysupport one or more SoC's in it socket(s). This
+ *   is a list of the SoC's to be supported.
+ *   IpBlkList - Each SoC is comprised of several IP blocks. This is a list of
+ *   the IP blocks contained within the SoC. There is one list per SoC.
+ *   This list contains pointers to the IP support routines in the xUSL.
+ *
+ * @endcond
+ */
+#pragma once
+
+#include <stddef.h>
+#include <stdint.h>   // needed for declarations later in this file
+#include <stdbool.h>
+#include <Sil-api.h>
+
+/*
+  Warning C4200: nonstandard extension used : zero-sized array in struct/union
+  This warning is generated by 'uint8_t  InfoBlockData[]' field in SIL_INFO_BLOCK_HEADER
+*/
+#pragma warning(disable:4200)
+
+/** @brief Data Block Identifiers
+ *
+ *  @details These are unique identifiers used by the xSIM and the Host
+ *  sides to locate an IPblock Input or Output data structure. See @ref SilFindStructure.
+ *  Each block type must have a unique identifier, so an IP  may have several
+ *  block IDs defined for the sections of memory it uses (input, output, private)
+ *  and each may have multiple instances. For example, a UART port may use one
+ *  ID for 'UART Port' but have several instances, one per port.
+ */
+typedef enum {
+  SilId_SocCommon = 0,
+  SilId_DfClass,
+  SilId_CcxClass,
+  SilId_FchClass,
+  SilId_MultiFchClass,
+  SilId_FchHwAcpiP,
+  SilId_FchAb,
+  SilId_FchSpi,
+  SilId_FchHwAcpi,
+  SilId_FchSata,
+  SilId_FchEspi,
+  SilId_FchUsb,
+  SilId_MemClass,
+  SilId_MultiFch,
+  SilId_NorthBridgePcie,
+  SilId_NbioClass,
+  SilId_XmpClass,
+  SilId_RcManager,
+  SilId_SmuClass,
+  SilId_MpioClass,
+  SilId_SdciClass,
+  SilId_CxlClass,
+  SilId_RasClass,
+                            // Add new elements above this line ^^^
+  SilId_ListEnd             ///< Value to bound the list
+} SIL_DATA_BLOCK_ID;
+
+
+/** @brief Header structure for openSIL Input & Output Blocks
+ *
+ *  @details This header is included at the front of each block assigned. It is
+ *  used to manage the space and locate the assigned blocks,
+ *  see @ref SilFindStructure.
+ */
+typedef struct  {
+  uint32_t Id;                ///< Information block identifier, see @ref SIL_DATA_BLOCK_ID
+  uint16_t Instance;          ///< Instance # of this ID (0..N) Instance '0'
+                              ///<  is reserved for the top level (class level)
+                              ///<  and values 1..N are for the ports.
+  uint8_t  RevMajor;          ///< Structure Major revision number. This is
+                              ///<  incremented when a non-backward compatible
+                              ///<  change is made.
+  uint8_t  RevMinor;          ///< Structure Minor revision number. This is
+                              ///<  is incremented for every change.
+  uint32_t InfoBlockDataSize; ///< Information block size. This is the
+                              ///<  size of block assigned, including the header,
+                              ///<  rounded up to the next full DWORD.
+  uint8_t  InfoBlockData[];   ///< start of the IP input block data struct.
+                              ///<  Cast this point to the IP structure type to
+                              ///<  reference the structure elements.
+} SIL_INFO_BLOCK_HEADER;
+
+typedef enum {
+  SIL_TP1,                    ///< In TP1 openSIL assign the memory to the Each IPs
+  SIL_TP2,                    ///< In TP2 Each Ips get the address of the memory
+                              ///< location which was assign in the TP1
+  SIL_TP3                     ///< In TP3 Each Ips get the address of the memory
+                              ///< location which was assign in the TP1
+} SIL_TIMEPOINT;
+/*********************************************************************
+ * API Function prototypes
+ *********************************************************************/
+
+/** @brief Gather Memory Requirements
+ *
+ *  @anchor HostSIL_Mem
+ * @details This is the Host's request to xSIM for the amount of memory needed.
+ * The function body will collect information from all of its
+ * sub-modules as to the size they need. The aggregated total will be
+ * returned to the Host caller.
+ *
+ * @return The return value is the minimum size, in bytes,
+ * needed by all xSIM components to complete their job.
+ */
+size_t
+xSimQueryMemoryRequirements ( void );
+
+
+/**
+ * xSimAssignMemoryTp1
+ *
+ * @brief Assign The Host Supplied Memory for timepoint 1
+ *
+ * @anchor HostSIL_Assign1
+ * @details Host informs xSIM of the allocated memory; gets defaults.
+ * The xUSL layer may record this base address for reference.
+ * The function body will call sub-modules (dependent upon the Soc design)
+ * to initialize IP related structures. Each sub module will assign the next
+ * piece of the buffer by instantiating its input block and any needed output
+ * blocks. Each instance contains the IP module identifier (a unique structure ID),
+ * information about the instance and the configuration data  (structure)
+ * for that block.
+ *
+ * Multiple instances (both input and output) can/will be assigned per the
+ * SoC design. Each instance must have access information for that instance
+ * (e.g. register base).
+ * The sub-module is also responsible for filling the configuration data
+ * section of the input block(s) with the defaults predefined at build time.
+ * The output blocks must be initialized and all response values filled with 0s.
+ * These will be updated when the IP module initializes the silicon.
+ *
+ * During TimePoint 1, openSIL is responsible for:
+ *
+ * 1. Initializing the global pointer to the Host allocated openSIL
+ *    memory block.
+ * 2. Initializing its internal APIs
+ * 3. Assigning necessary memory to each IP block.
+ *
+ * @param   BaseAddress Starting address of the block
+ *                      allocated by the Host FW.
+ * @param   MemorySize  Value containing the size of the
+ *                      allocated block (size in bytes).
+ *
+ * @return This routine provides two responses,
+ *  1. {memory block}:  filled with IP sub-modules structures and default values.
+ *  2. Completion status:
+ *   @retval OK             function completed successfully
+ *   @retval ResourceError  the block provided was insufficient for
+ *                            the quantity requested by the sub-modules.
+ */
+SIL_STATUS
+xSimAssignMemoryTp1 (
+  void*         BaseAddress,
+  size_t        MemorySize
+  );
+
+/**
+ * xSimAssignMemoryTp2
+ *
+ * @brief Assign The Host Supplied Memory for timepoint 2
+ *
+ * @anchor HostSIL_Assign2
+ * @details Host informs xSIM of the allocated memory; gets defaults.
+ * The xUSL layer may record this base address for reference.
+ * The function body will call sub-modules (dependent upon the Soc design)
+ * to initialize IP related structures. Each sub module will assign the next
+ * piece of the buffer by instantiating its input block and any needed output
+ * blocks. Each instance contains the IP module identifier (a unique structure ID),
+ * information about the instance and the configuration data  (structure)
+ * for that block.
+ *
+ * Multiple instances (both input and output) can/will be assigned per the
+ * SoC design. Each instance must have access information for that instance
+ * (e.g. register base).
+ * The sub-module is also responsible for filling the configuration data
+ * section of the input block(s) with the defaults predefined at build time.
+ * The output blocks must be initialized and all response values filled with 0s.
+ * These will be updated when the IP module initializes the silicon.
+ *
+ * During TimePoint 2, openSIL is responsible for:
+ *
+ * 1. Initializing the global pointer to the Host allocated openSIL
+ *    memory block.
+ * 2. Initializing its internal APIs
+ *
+ * @param   BaseAddress Starting address of the block
+ *                      allocated by the Host FW.
+ * @param   MemorySize  Value containing the size of the
+ *                      allocated block (size in bytes).
+ *
+ * @return This routine provides two responses,
+ *  1. {memory block}:  filled with IP sub-modules structures and default values.
+ *  2. Completion status:
+ *   @retval OK             function completed successfully
+ *   @retval ResourceError  the block provided was insufficient for
+ *                            the quantity requested by the sub-modules.
+ */
+SIL_STATUS
+xSimAssignMemoryTp2 (
+  void*         BaseAddress,
+  size_t        MemorySize
+  );
+
+/**
+ * xSimAssignMemoryTp3
+ *
+ * @brief Assign The Host Supplied Memory for timepoint 3
+ *
+ * @anchor HostSIL_Assign3
+ * @details Host informs xSIM of the allocated memory; gets defaults.
+ * The xUSL layer may record this base address for reference.
+ * The function body will call sub-modules (dependent upon the Soc design)
+ * to initialize IP related structures. Each sub module will assign the next
+ * piece of the buffer by instantiating its input block and any needed output
+ * blocks. Each instance contains the IP module identifier (a unique structure ID),
+ * information about the instance and the configuration data  (structure)
+ * for that block.
+ *
+ * Multiple instances (both input and output) can/will be assigned per the
+ * SoC design. Each instance must have access information for that instance
+ * (e.g. register base).
+ * The sub-module is also responsible for filling the configuration data
+ * section of the input block(s) with the defaults predefined at build time.
+ * The output blocks must be initialized and all response values filled with 0s.
+ * These will be updated when the IP module initializes the silicon.
+ *
+ * During TimePoint 2, openSIL is responsible for:
+ *
+ * 1. Initializing the global pointer to the Host allocated openSIL
+ *    memory block.
+ * 2. Initializing its internal APIs
+ *
+ * @param   BaseAddress Starting address of the block
+ *                      allocated by the Host FW.
+ * @param   MemorySize  Value containing the size of the
+ *                      allocated block (size in bytes).
+ *
+ * @return This routine provides two responses,
+ *  1. {memory block}:  filled with IP sub-modules structures and default values.
+ *  2. Completion status:
+ *   @retval OK             function completed successfully
+ *   @retval ResourceError  the block provided was insufficient for
+ *                            the quantity requested by the sub-modules.
+ */
+SIL_STATUS
+xSimAssignMemoryTp3 (
+  void*         BaseAddress,
+  size_t        MemorySize
+  );
+
+/** @brief Find a structure
+ *
+ *  @anchor HostSIL_Find
+ * @details Locate an assigned modules data block. Once the allocated
+ * memory block has been assigned to the IP blocks and filled with
+ * structure data, the Host will use this function to locate a structure
+ * within the memory block that was assigned by an IP block.
+ *
+ * The Host firmware may then inspect default settings and make any desired
+ * configuration content changes.
+ *
+ * @param   StructureID  value obtained from an enum list in the
+ *          API.H file which identifies the specific IP block to
+ *          be targeted.
+ * @param   InstanceNum  Always starting with 0, this value indicates which
+ *          one of many possible instances of an IP block is to be located.
+ *
+ * @return  A pointer to the address of the data block
+ *          requested. The address is within the Host allocated
+ *          memory block; e.g. writable area.
+ *   @retval  0x0000    indicates the requested block was not found.
+ */
+void*
+SilFindStructure (
+  SIL_DATA_BLOCK_ID  StructureID,
+  uint16_t InstanceNum
+  );
+
+/**--------------------------------------------------------------------
+ * SilDebugSetup
+ *
+ *  @anchor HostSIL_Debug
+ * @brief  Record pointer to host debug service routine
+ * @details The Host provides all debug output services. The openSIL code
+ * uses macros to implement tracing functions and call the Host service
+ * routine.
+ *
+ * The routine provided by the host must fit the prototype
+ * defined here: @ref xUslTracePoint .
+ * This is the fuction definition called by the macros.
+ *
+ * @param HostDbgService        Pointer to the host debug service routine
+ *
+ * @returns SilPass             The process completed successfully
+ * @returns SilInvalidParameter The HostDbgService pointer was invalid
+ **/
+SIL_STATUS
+SilDebugSetup (
+  HOST_DEBUG_SERVICE HostDbgService
+  );
+
+/**
+ * InitializeSiTp1
+ *
+ * @brief Initialize the Silicon at timepoint 1
+ *
+ * @details This is the primary Host API call to initialize all of the AMD silicon.
+ * The input parameter block(s) have been allocated and assigned to IP
+ * blocks. Input parameters that need dynamic adjustment have been modified; now
+ * is it time to say "GO". This call starts the IP block initializations.
+ * This function proceeds through each sub-module of the SoC to initialize
+ * it's related silicon modules and all instances (port) thereunder.
+ *
+ * @return  This routine provides two responses,
+ *  1. {IP output block}  each IPs output block will provide extended result information.
+ *  2. Completion status  indicates the general outcome of the process:
+ *   @retval    OK      The process completed successfully
+ *   @retval    Error   One or more of the sub-modules reported an error in
+ *              their initialization process. Please inspect the IP block
+ *              output blocks for information.
+ */
+SIL_STATUS
+InitializeSiTp1 (void);
+
+/**
+ * InitializeSiTp2
+ *
+ * @brief Initialize the Silicon at timepoint 2
+ *
+ * @details This is the primary Host API call to initialize all of the AMD silicon.
+ * The input parameter block(s) have been allocated and assigned to IP
+ * blocks. Input parameters that need dynamic adjustment have been modified; now
+ * is it time to say "GO". This call starts the IP block initializations.
+ * This function proceeds through each sub-module of the SoC to initialize
+ * it's related silicon modules and all instances (port) thereunder.
+ *
+ * @return  This routine provides two responses,
+ *  1. {IP output block}  each IPs output block will provide extended result information.
+ *  2. Completion status  indicates the general outcome of the process:
+ *   @retval    OK      The process completed successfully
+ *   @retval    Error   One or more of the sub-modules reported an error in
+ *              their initialization process. Please inspect the IP block
+ *              output blocks for information.
+ */
+SIL_STATUS
+InitializeSiTp2 (void);
+
+/**
+ * InitializeSiTp3
+ *
+ * @brief Initialize the Silicon at timepoint 3
+ *
+ * @details This is the primary Host API call to initialize all of the AMD silicon.
+ * The input parameter block(s) have been allocated and assigned to IP
+ * blocks. Input parameters that need dynamic adjustment have been modified; now
+ * is it time to say "GO". This call starts the IP block initializations.
+ * This function proceeds through each sub-module of the SoC to initialize
+ * it's related silicon modules and all instances (port) thereunder.
+ *
+ * @return  This routine provides two responses,
+ *  1. {IP output block}  each IPs output block will provide extended result information.
+ *  2. Completion status  indicates the general outcome of the process:
+ *   @retval    OK      The process completed successfully
+ *   @retval    Error   One or more of the sub-modules reported an error in
+ *              their initialization process. Please inspect the IP block
+ *              output blocks for information.
+ */
+SIL_STATUS
+InitializeSiTp3 (void);

Kconfig

@@ -0,0 +1,29 @@
+# Config for  openSIL
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: MIT
+#
+#  top level - selecting the Platform settings, SoC(s) to be included
+#               and IP device settings
+# Nomemclature:
+# * All config elements will be prefixed with "CONFIG_" by Kconfig
+# * Elements with names that start with "HAVE_" are code inclusion control
+#   elements. These will be used in the Meson build files to select which
+#   code modules will be included.
+#
+
+mainmenu "AMD openSIL project"
+comment "                                                               "
+comment " AMD open Silicon Initialization Library                       "
+comment "                                                               "
+
+source "Kconfig.Plat"
+source "Kconfig.SoC"
+source "Kconfig.IP"
+
+## Special selection for including the Example (XMP) device
+config HAVE_EXAMPLE
+    bool    "Do you want to include the Example (XMP) Device?"
+    default n
+
+
+

Kconfig.IP

@@ -0,0 +1,36 @@
+# Config for  openSIL
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: MIT
+#
+#  top level - selecting the SoC(s) to be included
+# Nomemclature:
+# * All config elements will be prefixed with "CONFIG_" by Kconfig
+# * Elements with names that start with "HAVE_" are code inclusion control
+#   elements. These will be used in the Meson build files to select which
+#   code modules will be included.
+# * Elements with names that start with "PLAT_" are platform description
+#   elements.
+#
+
+menu "AMD Silicon Feature Settings"
+comment "                                                               "
+comment " The available silicon devices and features are dependent upon "
+comment " which AMD processor(s) have been selected for inclusion into  "
+comment " the platform build.                                           "
+comment "                                                               "
+#
+
+
+
+source "xUSL/XMP/Kconfig"       ## temporary, remove when xUSL tree enabled
+source "xUSL/CCX/Kconfig"
+#source "xUSL/DF/Kconfig"
+source "xUSL/NBIO/Kconfig"
+source "xUSL/Mpio/Kconfig"
+source "xUSL/Sdci/Kconfig"
+#source "xUSL/FCH/Kconfig"
+#source "xUSL/SMU/Kconfig"
+#source "xUSL/RAS/Kconfig"
+#source "xUSL/MEM/Kconfig"
+
+endmenu

Kconfig.Plat

@@ -0,0 +1,62 @@
+# Config for  opoenSIL
+#  Platform level - set the platform values needed by openSIL
+#
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: MIT
+#
+# These are the patform descriptors needed by the openSIL code base. These
+# must be defined for the platform.
+# These values are 'static' in nature - once set, they are not changed by code.
+#
+
+menu "PLATFORM Description Settings"
+
+comment "The following items are placed in the platform address map by the "
+comment "porting Engineer. These locations must be propogated into openSIL."
+comment "                                                                  "
+
+config PLAT_APOB_ADDRESS
+    hex  "AMD Platform Output Block (APOB) location (32bit Hex address)"
+    default 0x75BA0000
+    help
+      Location (32bit Hex address) in the platform memory address
+      allocation map where you have the APOB. (platform dependent)
+      The APOB is the AMD embedded firmware data block describing the
+      topology for the processor found during early power-on. The platform
+      must allocate a <size> space in the memory map to accomodate the data.
+
+
+config PSP_BIOS_BIN_BASE
+    hex  "Base of the initial bootblock"
+    default 0x75CA0000
+    help
+      Location (32bit Hex address) in the platform memory address
+      allocation map where the initial bootblock is placed.
+
+config PSP_BIOS_BIN_SIZE
+    hex "Size of initial bootblock"
+    default 0x360000
+    help
+      Size of the initial bootblock placed in memroy by the PSP.
+
+
+config PLAT_CPU_MICROCODE_LOCATION
+    hex  "CPU uCode buffer location (32bit Hex address)"
+    default 0x003FFF00
+    help
+      Location (32bit Hex address) in the platform memory address
+      allocation map where you have located the buffer containing
+      the CPU core Micro-code patch.
+
+
+config PLAT_NUMBER_SOCKETS
+    int  "Motherboard has N sockets."
+    range 1 2
+    default     1
+    help
+      The SoC may support 1 or 2 sockets, but the motherboard may
+      implement fewer than the SoC max. This is a design decision and
+      is present here to inform the openSIL code.
+
+endmenu
+

Kconfig.Skt

@@ -0,0 +1,55 @@
+# Config for  opoenSIL
+#  Platform level - set the platform values needed by openSIL
+#
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: MIT
+#
+# These are config fields used to select the Market Segment
+#  and Socket type for the platform. These will then be used to further
+#  select the group of SoC available in those sockets.
+# These values are 'static' in nature - once set, they are not changed by code.
+#
+
+choice  MARKET_SEGMENT
+    prompt "Market segment for this plaform"
+    default MKT_SEG_SERVER
+    help
+      The AMD processors are grouped and sold by these market classes.
+      This field is used to limit the SoC choice list to those sold
+      in the selected market group/segment.
+
+config  MKT_SEG_SERVER
+    bool  "Server"
+    help
+      Larger towers or rack mount systems possibly multi-socket
+
+
+endchoice
+
+## optionally define a string for the Market Segment name for use in messages
+config PLAT_MARKET_SEGMENT_NAME
+    string
+    default  "Data Center"      if MKT_SEG_SERVER
+
+
+##-------------------------------------------------------------
+#   Select the Socket type
+#
+choice PLAT_SOCKET_TYPE
+    prompt  "Motherboard socket(s) type:"
+    default SKT_TYPE_SP5
+
+config  SKT_TYPE_SP5
+    bool "SP5"
+    depends on MKT_SEG_SERVER
+    help
+      Server
+
+
+endchoice
+
+## optionally define a string for the socket name for use in messages
+config PLAT_SOCKET_TYPE_NAME
+    string
+    default  "SP5"      if SKT_TYPE_SP5
+

Kconfig.SoC

@@ -0,0 +1,44 @@
+# Config for  openSIL
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: MIT
+#
+#  top level - selecting the SoC(s) to be included
+# Nomemclature:
+# * All config elements will be prefixed with "CONFIG_" by Kconfig
+# * Elements with names that start with "HAVE_" are code inclusion control
+#   elements. These will be used in the Meson build files to select which
+#   code modules will be included.
+# * Elements with names that start with "PLAT_" are platform description
+#   elements.
+#
+
+menu "AMD Processor(s) Selection"
+comment " This is the list of supported AMD processors for openSIL. Please "
+comment " select the Socket and processor designed into your motherboard.  "
+comment "                                                                  "
+
+source "Kconfig.Skt"
+
+# This is where the SoC(s) are determined for the build
+# The select statements define which IP-Version are used in each SoC
+# Several SoCs may use the same IP-version
+
+##if  (PLAT_SOCKET_TYPE = "SP5")
+if (SKT_TYPE_SP5)
+config SOC_F19M10
+    boolean "F19M10 (Genoa) Support"
+    select HAVE_SOC_COMMON
+    select HAVE_DF_DFX
+    select HAVE_CCX_ZEN4
+    select HAVE_MPIO
+    select HAVE_SDCI
+    select HAVE_NBIO_IOD
+    select HAVE_FCH_9004
+    select HAVE_SMU_V13
+    select HAVE_XMP_VER_B  if HAVE_EXAMPLE
+    help
+      Does your project use a Family 19h Model 10h
+      Choose 'y' to include the Genoa support code
+endif
+
+endmenu

LICENSE/MIT-License.txt

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2023 Advanced Micro Devices, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of this software and
+associated documentation files (the "Software"), to deal in the Software without restriction,
+including without limitation the rights to use, copy, modify, merge, publish, distribute,
+sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies
+or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.

README.md

@@ -0,0 +1,70 @@
+# AMD openSIL: Proof-of-Concept (POC)
+
+
+## About the project:
+
+The AMD open Silicon Initialization Library (openSIL) is a collection of C libraries which can be integrated into an x86 host firmware, by directly compiling source or by linking with static libraries.
+
+AMD openSIL consists of three statically linked libraries; xSIM (x86 Silicon Initialization Libraries), xPRF (x86 Platform Reference Library), and xUSL (x86 Utilities & Services Library).  These libraries can be statically linked to a host firmware during compile/link time.
+
+Source for the libraries resides under [xSIM](xSIM), [xPRF](xPRF), and [xUSL](xUSL).
+
+Formal documentation is in final review and will be uploaded to the [GitHub project page](https://github.com/openSIL/openSIL/tree/master/Documentation) when available.<br>
+The AMD blog "[Empowering The Industry with Open System Firmware - AMD openSIL](https://community.amd.com/t5/business/empowering-the-industry-with-open-system-firmware-amd-opensil/ba-p/599644)" provides a starting point to grasp the openSIL design goals.<br><br>
+
+## AMD openSIL open-source projected roadmap: 
+   ### Evaluation Only Phases (no support for production implementations):
+   1. Phase I   - Internal POC (complete).
+   2. Phase II  - AMD openSIL POC open-sourced for evaluation on AMD 4th Gen EPYC&trade; based CRB (complete: this source).
+   3. Phase III - POC openSIL POC open-sourced, trending Q4 2024.
+   ### Production Phase:
+   4. Phase IV: - AMD openSIL POR with UEFI Host FW trending 2026.<br><br>
+## Getting Started:
+
+1. Clone Repository:
+   1. Establish your GitHub user account and your SSH keys (details are beyond this doc)
+   2. Open a command/terminal window
+   3. Run git to obtain the project:
+       ```> git clone git@github.com:openSIL/openSIL.git```<br><br>
+
+2. Establish the project environment variables.
+
+   * You will find a shell/cmd file (SetSilEnv) in the 'util' directory for this purpose.<br><br>
+
+3. Configure your project
+   * This release of the AMD openSIL libraries supports AMD 4th Gen EPYC&trade; on the Onyx CRB only.
+
+   * The openSIL project uses the python version of the Kconfig tool for this purpose. (See GitHub Kconfiglib).
+
+   * Run the interactive configuration UI:
+      ```> python %PYTHONPATH%\menuconfig.py Kconfig```<br><br>
+
+4. Build openSIL Libraries:
+   *  The AMD openSIL library build is performed using 'Meson build', an open source python tool (see GitHub).  Several targets allow a focused build for xUSL, xSIM, xPRF or openSIL(xUSL + xSIM + XPRF) static libraries. AMD openSIL specific Meson build documentation is not yet available.
+   * The project can be built for 32bit and/or 64bit compilation and static libraries.
+   * The project supports both the GNU/GCC or LLVM/clang tool chain and the Microsoft Visual C tool chain. Generally it is recommended to use the latest versions of these tool chains.<br />
+   Specific versions being used today (June 2023) are:
+     *  GCC - v10.2.0
+     *  llvm/clang - v10.0
+     *  MSVC v19.00.24210  (Visual Studio 2015)<br>
+
+5. Integrate with Host Firmware:
+
+   * AMD has a separate repository ("opensil-uefi-interface" ) for helping customers integrate openSIL with previous UEFI-AGESA installations.  Please contact your AMD representative for more information.<br><br>
+
+6. Test Host Firmware on reference platform
+
+   * All AMD openSIL testing has been performed on AMD an AMD reference platform (Onyx CRB).
+   * Present list of supported reference platforms is shown in the following table.
+
+     | Market<br>Segment | AMD Processor<br>Family Model | Firmware | Reference Platform<br>Name |
+     | ------------------- | -------------------------------- | -------- | ----------------------------- |
+     | Server              | F19M10                           | UEFI     | Onyx                          |
+
+## Forthcoming items:
+   * Formal documentation to be publishd to this repository.
+   * Continuous integration (CI) tools will be implemented as a pre-requisite to merging pull requests.
+
+## License:
+
+The MIT License (MIT): https://rem.mit-license.org

amd-checkers.txt

@@ -0,0 +1,70 @@
+-en
+BUFFER_SIZE
+-en
+CHECKED_RETURN
+-en
+CONSTANT_EXPRESSION_RESULT
+-en
+DC.STRING_BUFFER
+-en
+DEADCODE
+-en
+ENUM_AS_BOOLEAN
+-en
+FORWARD_NULL
+-en
+HARDCODED_CREDENTIALS
+-en
+HFA
+-en
+IDENTICAL_BRANCHES
+-en
+INCOMPATIBLE_CAST
+-en
+INTEGER_OVERFLOW
+-en
+MISSING_BREAK
+-en
+MISSING_COMMA
+-en
+MIXED_ENUMS
+-en
+NEGATIVE_RETURNS
+-en
+NO_EFFECT
+-en
+NULL_RETURNS
+-en
+OVERRUN
+-en
+PARSE_ERROR
+-en
+PASS_BY_VALUE
+-en
+REVERSE_INULL
+-en
+SIZEOF_MISMATCH
+-en
+STRING_OVERFLOW
+-en
+UNENCRYPTED_SENSITIVE_DATA
+-en
+UNINIT
+-en
+UNUSED_VALUE
+-en
+USER_POINTER
+-en
+WEAK_GUARD
+-en
+WEAK_PASSWORD_HASH
+-en
+OVERRUN
+--all
+--enable-constraint-fpp
+--enable-fnptr
+--enable-virtual
+--enable-callgraph-metrics
+--enable-parse-warnings
+-j
+auto

cert-c-all.config

@@ -0,0 +1,8 @@
+// Do not edit this file! Make a copy and edit it to produce your own configuration
+// Configuration for CERT, rule categories: L1, L2, L3
+{
+    "version": "2.0",
+    "standard": "cert-c",
+    "title": "CERT C All Rules",
+    "deviations": []
+}

configs/Onyx_SilCfg

@@ -0,0 +1,251 @@
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: MIT
+
+#
+#  AMD open Silicon Initialization Library
+#
+#
+# PLATFORM Description Settings
+#
+#
+# The following items are placed in the platform address map by the
+# porting Engineer. These locations must be propogated into openSIL.
+#
+CONFIG_PLAT_APOB_ADDRESS=0x4000000
+CONFIG_PSP_BIOS_BIN_BASE=0x76D00000
+CONFIG_PSP_BIOS_BIN_SIZE=0x300000
+CONFIG_PLAT_CPU_MICROCODE_LOCATION=0x003FFF00
+CONFIG_PLAT_NUMBER_SOCKETS=1
+# end of PLATFORM Description Settings
+
+#
+# AMD Processor(s) Selection
+#
+
+#
+#  This is the list of supported AMD processors for openSIL. Please
+#  select the Socket and processor designed into your motherboard.
+#
+CONFIG_MKT_SEG_SERVER=y
+CONFIG_PLAT_MARKET_SEGMENT_NAME="Data Center"
+CONFIG_SKT_TYPE_SP5=y
+# CONFIG_SKT_TYPE_SP5 is set
+CONFIG_PLAT_SOCKET_TYPE_NAME="SP5"
+# CONFIG_SOC_F19M10 is set
+CONFIG_SOC_F19M10=y
+# end of AMD Processor(s) Selection
+
+#
+# AMD Silicon Feature Settings
+#
+#  The available silicon devices and features are dependent upon
+#  which AMD processor(s) have been selected for inclusion into
+#  the platform build.
+#
+CONFIG_HAVE_CCX_ZEN4=y
+
+#
+# Compute Core Complex (CCX) Device
+#
+CONFIG_CHOICE_APIC_AUTO=y
+CONFIG_CCX_APIC_MODE=0xFF
+CONFIG_CHOICE_NUMCCD_AUTO=y
+CONFIG_CCX_CCD_MODE=0
+CONFIG_CCX_SMT_MODE=1
+CONFIG_CCX_CSTATE_ENABLE=1
+CONFIG_CCX_CSTATE_IO_ADDR=0x0813
+CONFIG_CCX_CSTATE_CC6_ENABLE=1
+CONFIG_CCX_CPB_ENABLE=1
+CONFIG_CCX_SMEE_ENABLE=0
+
+# end of Compute Core Complex (CCX) Device
+
+CONFIG_HAVE_NBIO_IOD=y
+
+#
+# IOAPIC settings
+#
+CONFIG_IOAPIC_MMIO_ADDRESS_RESERVED_ENABLE=1
+CONFIG_IOAPIC_ID_PREDEFINE_EN=0
+CONFIG_IOAPIC_ID_BASE=0xF1
+# end of IOAPIC settings
+
+CONFIG_CHOICE_AUTO=y
+# CONFIG_CHOICE_DISABLED is not set
+CONFIG_NBIO_GLOBAL_CG_OVERRIDE=0x0f
+CONFIG_SSTUNL_CLK_GATING=1
+CONFIG_NBIF_MGCG_CLK_GATING=1
+CONFIG_NBIF_MGCG_HYSTERESIS=0
+CONFIG_SYSHUB_MGCG_CLK_GATING=0
+CONFIG_SYSHUB_MGCG_HYSTERESIS=0
+CONFIG_IOHC_CLK_GATING_SUPPORT=1
+CONFIG_NTB_CLOCK_GATING_ENABLE=1
+CONFIG_IOHC_PG_ENABLE=1
+CONFIG_IOHC_NONPCI_BAR_INIT_DBG=0
+CONFIG_IOHC_NONPCI_BAR_INIT_FAST_REG=0
+CONFIG_IOHC_NONPCI_BAR_INIT_FAST_REGCTL=0
+# end of NBIO PMM - General
+
+#
+# NBIO common Options
+#
+CONFIG_IOMMU_SUPPORT=1
+CONFIG_IOMMU_L1_CLOCK_GATING_EN=1
+CONFIG_IOMMU_L2_CLOCK_GATING_EN=1
+CONFIG_IOMMU_AVIC_SUPPORT=0
+CONFIG_IOMMU_MMIO_ADDRESS_RESERVED_ENABLE=1
+CONFIG_PCIE_ECRC_ENABLEMENT=1
+CONFIG_AUTO_SPEED_CHANGE_EN=0
+CONFIG_PCIE_ARI_SUPPORT=1
+CONFIG_RX_MARGIN_PERSISTENCE_MODE=1
+# end of NBIO common Options
+
+#
+# Advanced Error Reporting
+#
+CONFIG_AER_ENABLE=1
+CONFIG_ACS_ENABLE=1
+CONFIG_PCIE_LTR_ENABLE=1
+CONFIG_TPH_COMPLETER_ENABLE=1
+CONFIG_SRIOV_EN_DEV0F1=0
+CONFIG_ARI_EN_DEV0F1=0
+CONFIG_AER_EN_DEV0F1=0
+CONFIG_ACS_EN_DEV0F1=0
+CONFIG_ATS_EN_DEV0F1=0
+CONFIG_PASID_EN_DEV0F1=0
+CONFIG_RTR_EN_DEV0F1=0
+CONFIG_PRI_EN_DEV0F1=0
+CONFIG_ATC_ENABLE=0
+CONFIG_ACS_EN_RCC_DEV0=0
+CONFIG_AER_EN_RCC_DEV0=0
+CONFIG_ACS_SOURCE_VAL_STRAP5=1
+CONFIG_ACS_TRANSLATIONAL_BLOCKING_STRAP5=1
+CONFIG_ACS_P2P_REQ_STRAP5=1
+CONFIG_ACS_P2P_COMP_STRAP5=1
+CONFIG_ACS_UPSTREAM_FWD_STRAP5=1
+CONFIG_ACS_P2P_EGRESS_STRAP5=0
+CONFIG_ACS_DIRECT_TRANSLATED_STRAP5=1
+CONFIG_ACS_SSID_EN_STRAP5=1
+CONFIG_DLF_EN_STRAP1=1
+CONFIG_PHY_16GT_STRAP1=1
+CONFIG_MARGIN_EN_STRAP1=1
+CONFIG_PRI_EN_PAGE_REQ=1
+CONFIG_PRI_RESET_PAGE_REQ=1
+CONFIG_ACS_SOURCE_VAL=1
+CONFIG_ACS_TRANSLATIONAL_BLOCKING=0
+CONFIG_ACS_P2P_REQ=1
+CONFIG_ACS_P2P_COMP=1
+CONFIG_ACS_UPSTREAM_FWD=1
+CONFIG_ACS_P2P_EGRESS=0
+CONFIG_AMD_MASK_DPC_CAPABILITY=0
+# end of Advanced Error Reporting
+
+CONFIG_CHOICE_PCIE_SPEEDCTRL_AUTO=y
+CONFIG_PCIE_SPEED_CONTROL=0x0F
+CONFIG_PWR_EN_DEV0F1=0
+CONFIG_TLP_PREFIX_SETTING=0
+CONFIG_RCC_DEV0_EXTENDED_FMT_SUPPORTED=0
+CONFIG_DLF_CAP_EN=1
+CONFIG_DL_FEX_EN=1
+CONFIG_PRE_CODE_REQUEST_ENABLE=0
+CONFIG_ADVERTISE_EQ_TO_HIGH_RATE_SUPPORT=0
+CONFIG_FABRIC_SDCI=0
+CONFIG_ESM_EN_ALL_ROOT_PORTS=0
+# end of Northbridge IO (NBIO) Device
+
+CONFIG_HAVE_MPIO=y
+
+#
+# MicroProcessor Input Output (MPIO)
+#
+CONFIG_MPIO_CLOCKGATING_ENABLE=1
+CONFIG_MPIO_TIMINGCTRL_ENABLE=0
+CONFIG_PCIE_LINK_RECEIVER_DETECT_TIMEOUT=0
+CONFIG_PCIE_LINK_RESET_TO_TRAINING_TIMEOUT=0
+CONFIG_PCIE_LINK_L0_STATE_TIMEOUT=0
+CONFIG_MPIO_EXACT_MATCH_ENABLE=0
+CONFIG_MPIO_PHY_VALID=1
+CONFIG_MPIO_PHY_PROGRAMMING=1
+CONFIG_MPIO_SKIP_PSP_MSG=1
+CONFIG_CHOICE_SAVE_RESTORE_MODE_DEFAULT=y
+CONFIG_MPIO_SAVE_RESTORE_MODE=0xFF
+CONFIG_CHOICE_ENABLE_PCIE_POLLING=y
+CONFIG_MPIO_ALLOW_PCIE_POLLING=0x00
+CONFIG_CHOICE_HOT_PLUG_AUTO=y
+CONFIG_MPIO_HOT_PLUG_MODE=0xFF
+CONFIG_CHOICE_PCIE_SRIS_AUTO=y
+CONFIG_MPIO_PCIE_SRIS_CONTROL=0xFF
+CONFIG_CHOICE_PCIE_SRIS_SKIP_INTERVAL_0=y
+CONFIG_MPIO_PCIE_SRIS_SKIP_INTERVAL=0x00
+CONFIG_MPIO_SRIS_SKIP_INTERVAL_SELECT=1
+CONFIG_MPIO_SRIS_CONFIG_TYPE=0
+CONFIG_CHOICE_SRIS_AUTO_DETECT_MODE_AUTO=y
+CONFIG_MPIO_SRIS_AUTO_DETECT_MODE=0x0F
+CONFIG_MPIO_SRIS_AUTODETECT_FACTOR=0
+CONFIG_CHOICE_SRIS_SKP_TRANSMISSION_UNSUPPORTED=y
+CONFIG_MPIO_PCIE_SRIS_SKP_TRANSMISSION_CONTROL=0x00
+CONFIG_CHOICE_SRIS_SKP_RECEPTION_UNSUPPORTED=y
+CONFIG_MPIO_PCIE_SRIS_SKP_RECEPTION_CONTROL=0x00
+CONFIG_MPIO_CXL_PORT_CONTROL=1
+CONFIG_MPIO_CXL_CORRECTABLE_ERROR_LOGGING=1
+CONFIG_MPIO_CXL_UNCORRECTABLE_ERROR_LOGGING=1
+CONFIG_MPIO_ADVANCED_ERROR_REPORTING_ENABLE=1
+CONFIG_MPIO_PCIE_MULTICAST_ENABLE=0
+CONFIG_MPIO_RECEIVE_ERROR_ENABLE=0
+CONFIG_MPIO_EARLY_BMC_LINK_TRAIN_ENABLE=1
+CONFIG_CHOICE_SOCKET_NUM_0=y
+CONFIG_MPIO_EARLY_BMC_LINK_SOCKET=0x00
+CONFIG_MPIO_EARLY_BMC_LINK_LANE=134
+CONFIG_CHOICE_LANE_0_TO_31=y
+CONFIG_MPIO_EARLY_BMC_LINK_DIE=0x00
+CONFIG_MPIO_SURPRISE_DOWN_ENABLE=1
+CONFIG_MPIO_PCIE_LINK_TRAINING_SPEED=0
+CONFIG_MPIO_RX_MARGIN_ENABLE=1
+CONFIG_MPIO_PCIE_CV_TEST_CONFIG=1
+CONFIG_MPIO_PCIE_ARI_SUPPORT=1
+CONFIG_MPIO_TOGGLE_NBIO_TO_SC=0
+CONFIG_MPIO_TOGGLE_NBIO_IGNORE_CTO_ERROR=1
+CONFIG_NBIO_CONTROLLER_SSID=0
+CONFIG_IOMMU_CONTROLLER_SSID=0
+CONFIG_PSP_CCP_CONTROLLER_SSID=0
+CONFIG_NTB_CCP_CONTROLLER_SSID=0
+CONFIG_NBIF0_CONTROLLER_SSID=0
+CONFIG_NTB_CONTROLLER_SSID=0
+CONFIG_PCIE_SUBSYSTEM_DEVICE_ID=0
+CONFIG_PCIE_SUBSYSTEM_VENDOR_ID=0
+CONFIG_MPIO_GPP_ATOMIC_OPS=1
+CONFIG_MPIO_GPFXATOMIC_OPS=1
+CONFIG_MPIO_EDB_ERROR_REPORTING_ENABLE=0
+CONFIG_MPIO_OPN_SPARE=0
+CONFIG_AMD_PRE_SIL_CONTROL=0
+CONFIG_MPIO_ANCILLARY_DATA_SUPPORT_ENABLE=0
+CONFIG_MPIO_AFTER_RESET_DELAY=0
+CONFIG_MPIO_EARLY_LINK_TRAINING_ENABLE=0
+CONFIG_CHOICE_USE_PLATFORM_CONFIG_DEFAULT=y
+CONFIG_MPIO_EXPOSE_UNUSED_PCIE_PORTS=0xFF
+CONFIG_CHOICE_NO_LINK_SPEED_LIMIT=y
+CONFIG_MPIO_MAX_PCIE_LINK_SPEED=0
+CONFIG_MPIO_SATA_PHY_TUNING=0
+CONFIG_PCIE_LINK_COMPILANCE_MODE_ENABLE=1
+CONFIG_MPIO_MCTP_SUPPORT_ENABLE=0
+CONFIG_SBR_BROKEN_LANE_AVOIDANCE_ENABLE=1
+CONFIG_AUTO_FULL_MARGINING_SUPPORT_ENABLE=1
+CONFIG_GEN3_PCIE_PRESET_MASK=0xFFFFFFFF
+CONFIG_GEN4_PCIE_PRESET_MASK=0xFFFFFFFF
+CONFIG_GEN5_PCIE_PRESET_MASK=0xFFFFFFFF
+CONFIG_CHOICE_ACTIVE_STATE_PWR_MGMT_AUTO=y
+CONFIG_PCIE_LINK_ACTIVE_STATE_PWR_MGMT=0xFF
+CONFIG_MCTP_MASTER_PCI_ADDR_SEGMENT=0
+CONFIG_MCTP_MASTER_PCI_ADDR=0
+# end of MicroProcessor Input Output (MPIO)
+
+CONFIG_HAVE_SDCI=y
+
+#
+# Smart Data Cache Injection (SDCI)
+#
+CONFIG_SDCI_SMART_DATA_CACHE_INJECTION_ENABLE=0
+# end of Smart Data Cache Injection (SDCI)
+# end of AMD Silicon Feature Settings
+
+# CONFIG_HAVE_EXAMPLE is not set

configs/Onyx_SilCfg.h

@@ -0,0 +1,177 @@
+/* Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.    */
+// SPDX-License-Identifier: MIT
+#define CONFIG_PLAT_APOB_ADDRESS 0x4000000
+#define CONFIG_PSP_BIOS_BIN_BASE 0x76D00000
+#define CONFIG_PSP_BIOS_BIN_SIZE 0x300000
+#define CONFIG_PLAT_CPU_MICROCODE_LOCATION 0x003FFF00
+#define CONFIG_PLAT_NUMBER_SOCKETS 1
+#define CONFIG_MKT_SEG_SERVER 1
+#define CONFIG_PLAT_MARKET_SEGMENT_NAME "Data Center"
+#define CONFIG_SKT_TYPE_SP5 1
+#define CONFIG_PLAT_SOCKET_TYPE_NAME "SP5"
+#define CONFIG_SOC_F19M10 1
+#define CONFIG_HAVE_CCX_ZEN4 1
+#define CONFIG_CHOICE_APIC_AUTO 1
+#define CONFIG_CCX_APIC_MODE 0xFF
+#define CONFIG_CHOICE_NUMCCD_AUTO 1
+#define CONFIG_CCX_CCD_MODE 0
+#define CONFIG_CCX_SMT_MODE 1
+#define CONFIG_CCX_CSTATE_ENABLE 1
+#define CONFIG_CCX_CSTATE_IO_ADDR 0x0813
+#define CONFIG_CCX_CSTATE_CC6_ENABLE 1
+#define CONFIG_CCX_CPB_ENABLE 1
+#define CONFIG_CCX_SMEE_ENABLE 0
+#define CONFIG_HAVE_NBIO_IOD 1
+#define CONFIG_IOAPIC_MMIO_ADDRESS_RESERVED_ENABLE 1
+#define CONFIG_IOAPIC_ID_PREDEFINE_EN 0
+#define CONFIG_IOAPIC_ID_BASE 0xF1
+#define CONFIG_CHOICE_AUTO 1
+#define CONFIG_NBIO_GLOBAL_CG_OVERRIDE 0x0f
+#define CONFIG_SSTUNL_CLK_GATING 1
+#define CONFIG_NBIF_MGCG_CLK_GATING 1
+#define CONFIG_NBIF_MGCG_HYSTERESIS 0
+#define CONFIG_SYSHUB_MGCG_CLK_GATING 0
+#define CONFIG_SYSHUB_MGCG_HYSTERESIS 0
+#define CONFIG_IOHC_CLK_GATING_SUPPORT 1
+#define CONFIG_NTB_CLOCK_GATING_ENABLE 1
+#define CONFIG_IOHC_PG_ENABLE 1
+#define CONFIG_IOHC_NONPCI_BAR_INIT_DBG 0
+#define CONFIG_IOHC_NONPCI_BAR_INIT_FAST_REG 0
+#define CONFIG_IOHC_NONPCI_BAR_INIT_FAST_REGCTL 0
+#define CONFIG_IOMMU_SUPPORT 1
+#define CONFIG_IOMMU_L1_CLOCK_GATING_EN 1
+#define CONFIG_IOMMU_L2_CLOCK_GATING_EN 1
+#define CONFIG_IOMMU_AVIC_SUPPORT 0
+#define CONFIG_IOMMU_MMIO_ADDRESS_RESERVED_ENABLE 1
+#define CONFIG_PCIE_ECRC_ENABLEMENT 1
+#define CONFIG_AUTO_SPEED_CHANGE_EN 0x0
+#define CONFIG_PCIE_ARI_SUPPORT 1
+#define CONFIG_RX_MARGIN_PERSISTENCE_MODE 1
+#define CONFIG_AER_ENABLE 1
+#define CONFIG_ACS_ENABLE 1
+#define CONFIG_PCIE_LTR_ENABLE 1
+#define CONFIG_TPH_COMPLETER_ENABLE 1
+#define CONFIG_SRIOV_EN_DEV0F1 0
+#define CONFIG_ARI_EN_DEV0F1 0
+#define CONFIG_AER_EN_DEV0F1 0
+#define CONFIG_ACS_EN_DEV0F1 0
+#define CONFIG_ATS_EN_DEV0F1 0
+#define CONFIG_PASID_EN_DEV0F1 0
+#define CONFIG_RTR_EN_DEV0F1 0
+#define CONFIG_PRI_EN_DEV0F1 0
+#define CONFIG_ATC_ENABLE 0
+#define CONFIG_ACS_EN_RCC_DEV0 0
+#define CONFIG_AER_EN_RCC_DEV0 0
+#define CONFIG_ACS_SOURCE_VAL_STRAP5 1
+#define CONFIG_ACS_TRANSLATIONAL_BLOCKING_STRAP5 1
+#define CONFIG_ACS_P2P_REQ_STRAP5 1
+#define CONFIG_ACS_P2P_COMP_STRAP5 1
+#define CONFIG_ACS_UPSTREAM_FWD_STRAP5 1
+#define CONFIG_ACS_P2P_EGRESS_STRAP5 0
+#define CONFIG_ACS_DIRECT_TRANSLATED_STRAP5 1
+#define CONFIG_ACS_SSID_EN_STRAP5 1
+#define CONFIG_DLF_EN_STRAP1 1
+#define CONFIG_PHY_16GT_STRAP1 1
+#define CONFIG_MARGIN_EN_STRAP1 1
+#define CONFIG_PRI_EN_PAGE_REQ 1
+#define CONFIG_PRI_RESET_PAGE_REQ 1
+#define CONFIG_ACS_SOURCE_VAL 1
+#define CONFIG_ACS_TRANSLATIONAL_BLOCKING 0
+#define CONFIG_ACS_P2P_REQ 1
+#define CONFIG_ACS_P2P_COMP 1
+#define CONFIG_ACS_UPSTREAM_FWD 1
+#define CONFIG_ACS_P2P_EGRESS 0
+#define CONFIG_AMD_MASK_DPC_CAPABILITY 0
+#define CONFIG_CHOICE_PCIE_SPEEDCTRL_AUTO 1
+#define CONFIG_PCIE_SPEED_CONTROL 0x0F
+#define CONFIG_PWR_EN_DEV0F1 0
+#define CONFIG_TLP_PREFIX_SETTING 0
+#define CONFIG_RCC_DEV0_EXTENDED_FMT_SUPPORTED 0
+#define CONFIG_DLF_CAP_EN 1
+#define CONFIG_DL_FEX_EN 1
+#define CONFIG_PRE_CODE_REQUEST_ENABLE 0
+#define CONFIG_ADVERTISE_EQ_TO_HIGH_RATE_SUPPORT 0
+#define CONFIG_FABRIC_SDCI 0
+#define CONFIG_ESM_EN_ALL_ROOT_PORTS 0
+#define CONFIG_HAVE_MPIO 1
+#define CONFIG_MPIO_CLOCKGATING_ENABLE 1
+#define CONFIG_MPIO_TIMINGCTRL_ENABLE 0
+#define CONFIG_PCIE_LINK_RECEIVER_DETECT_TIMEOUT 0
+#define CONFIG_PCIE_LINK_RESET_TO_TRAINING_TIMEOUT 0
+#define CONFIG_PCIE_LINK_L0_STATE_TIMEOUT 0
+#define CONFIG_MPIO_EXACT_MATCH_ENABLE 0
+#define CONFIG_MPIO_PHY_VALID 1
+#define CONFIG_MPIO_PHY_PROGRAMMING 1
+#define CONFIG_MPIO_SKIP_PSP_MSG 1
+#define CONFIG_CHOICE_SAVE_RESTORE_MODE_DEFAULT 1
+#define CONFIG_MPIO_SAVE_RESTORE_MODE 0xFF
+#define CONFIG_CHOICE_ENABLE_PCIE_POLLING 1
+#define CONFIG_MPIO_ALLOW_PCIE_POLLING 0x00
+#define CONFIG_CHOICE_HOT_PLUG_AUTO 1
+#define CONFIG_MPIO_HOT_PLUG_MODE 0xFF
+#define CONFIG_CHOICE_PCIE_SRIS_AUTO 1
+#define CONFIG_MPIO_PCIE_SRIS_CONTROL 0xFF
+#define CONFIG_CHOICE_PCIE_SRIS_SKIP_INTERVAL_0 1
+#define CONFIG_MPIO_PCIE_SRIS_SKIP_INTERVAL 0x00
+#define CONFIG_MPIO_SRIS_SKIP_INTERVAL_SELECT 1
+#define CONFIG_MPIO_SRIS_CONFIG_TYPE 0
+#define CONFIG_CHOICE_SRIS_AUTO_DETECT_MODE_AUTO 1
+#define CONFIG_MPIO_SRIS_AUTO_DETECT_MODE 0x0F
+#define CONFIG_MPIO_SRIS_AUTODETECT_FACTOR 0
+#define CONFIG_CHOICE_SRIS_SKP_TRANSMISSION_UNSUPPORTED 1
+#define CONFIG_MPIO_PCIE_SRIS_SKP_TRANSMISSION_CONTROL 0x00
+#define CONFIG_CHOICE_SRIS_SKP_RECEPTION_UNSUPPORTED 1
+#define CONFIG_MPIO_PCIE_SRIS_SKP_RECEPTION_CONTROL 0x00
+#define CONFIG_MPIO_CXL_PORT_CONTROL 1
+#define CONFIG_MPIO_CXL_CORRECTABLE_ERROR_LOGGING 1
+#define CONFIG_MPIO_CXL_UNCORRECTABLE_ERROR_LOGGING 1
+#define CONFIG_MPIO_ADVANCED_ERROR_REPORTING_ENABLE 1
+#define CONFIG_MPIO_PCIE_MULTICAST_ENABLE 0
+#define CONFIG_MPIO_RECEIVE_ERROR_ENABLE 0
+#define CONFIG_MPIO_EARLY_BMC_LINK_TRAIN_ENABLE 1
+#define CONFIG_CHOICE_SOCKET_NUM_0 1
+#define CONFIG_MPIO_EARLY_BMC_LINK_SOCKET 0x00
+#define CONFIG_MPIO_EARLY_BMC_LINK_LANE 134
+#define CONFIG_CHOICE_LANE_0_TO_31 1
+#define CONFIG_MPIO_EARLY_BMC_LINK_DIE 0x00
+#define CONFIG_MPIO_SURPRISE_DOWN_ENABLE 1
+#define CONFIG_MPIO_PCIE_LINK_TRAINING_SPEED 0
+#define CONFIG_MPIO_RX_MARGIN_ENABLE 1
+#define CONFIG_MPIO_PCIE_CV_TEST_CONFIG 1
+#define CONFIG_MPIO_PCIE_ARI_SUPPORT 1
+#define CONFIG_MPIO_TOGGLE_NBIO_TO_SC 0
+#define CONFIG_MPIO_TOGGLE_NBIO_IGNORE_CTO_ERROR 1
+#define CONFIG_NBIO_CONTROLLER_SSID 0
+#define CONFIG_IOMMU_CONTROLLER_SSID 0
+#define CONFIG_PSP_CCP_CONTROLLER_SSID 0
+#define CONFIG_NTB_CCP_CONTROLLER_SSID 0
+#define CONFIG_NBIF0_CONTROLLER_SSID 0
+#define CONFIG_NTB_CONTROLLER_SSID 0
+#define CONFIG_PCIE_SUBSYSTEM_DEVICE_ID 0
+#define CONFIG_PCIE_SUBSYSTEM_VENDOR_ID 0
+#define CONFIG_MPIO_GPP_ATOMIC_OPS 1
+#define CONFIG_MPIO_GPFXATOMIC_OPS 1
+#define CONFIG_MPIO_EDB_ERROR_REPORTING_ENABLE 0
+#define CONFIG_MPIO_OPN_SPARE 0
+#define CONFIG_AMD_PRE_SIL_CONTROL 0
+#define CONFIG_MPIO_ANCILLARY_DATA_SUPPORT_ENABLE 0
+#define CONFIG_MPIO_AFTER_RESET_DELAY 0
+#define CONFIG_MPIO_EARLY_LINK_TRAINING_ENABLE 0
+#define CONFIG_CHOICE_USE_PLATFORM_CONFIG_DEFAULT 1
+#define CONFIG_MPIO_EXPOSE_UNUSED_PCIE_PORTS 0xFF
+#define CONFIG_CHOICE_NO_LINK_SPEED_LIMIT 1
+#define CONFIG_MPIO_MAX_PCIE_LINK_SPEED 0
+#define CONFIG_MPIO_SATA_PHY_TUNING 0
+#define CONFIG_PCIE_LINK_COMPILANCE_MODE_ENABLE 1
+#define CONFIG_MPIO_MCTP_SUPPORT_ENABLE 0
+#define CONFIG_SBR_BROKEN_LANE_AVOIDANCE_ENABLE 1
+#define CONFIG_AUTO_FULL_MARGINING_SUPPORT_ENABLE 1
+#define CONFIG_GEN3_PCIE_PRESET_MASK 0xFFFFFFFF
+#define CONFIG_GEN4_PCIE_PRESET_MASK 0xFFFFFFFF
+#define CONFIG_GEN5_PCIE_PRESET_MASK 0xFFFFFFFF
+#define CONFIG_CHOICE_ACTIVE_STATE_PWR_MGMT_AUTO 1
+#define CONFIG_PCIE_LINK_ACTIVE_STATE_PWR_MGMT 0xFF
+#define CONFIG_MCTP_MASTER_PCI_ADDR_SEGMENT 0
+#define CONFIG_MCTP_MASTER_PCI_ADDR 0
+#define CONFIG_HAVE_SDCI 1
+#define CONFIG_SDCI_SMART_DATA_CACHE_INJECTION_ENABLE 0

configs/SilCfg.Template

@@ -0,0 +1,14 @@
+/* Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.    */
+// SPDX-License-Identifier: MIT
+
+#pragma once
+
+/* fixup coverity build issues */
+#mesondefine IS_COVERITY_BUILD
+#ifdef IS_COVERITY_BUILD
+  #include "util/meson/mason-coverity.h"
+#endif
+
+/* Now include the platform openSIL config file generated from Kconfig */
+#include "@PlatFormKcfg@.h"
+