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257 lines
6.9 KiB
C
257 lines
6.9 KiB
C
/**
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* @file PciOps.c
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* @brief OpenSIL PCI access functions
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*
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*/
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/* Copyright 2021-2023 Advanced Micro Devices, Inc. All rights reserved. */
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// SPDX-License-Identifier: MIT
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#include <SilCommon.h>
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#include "PciExpress.h"
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#include "Pci.h"
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/**
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* xUSLPciRead8
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* @brief Read 8-bit PCI register
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* @param Address 32-bit PCI address that encodes the PCI Bus, Device, Function and Register
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*
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*/
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uint8_t xUSLPciRead8 (uint32_t Address)
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{
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return xUSLPciExpressRead8 ((void*)(size_t)Address);
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}
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/**
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* @brief Write 8-bit PCI register
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* @param Address 32-bit PCI address that encodes the PCI Bus, Device, Function and Register
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*
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*/
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void xUSLPciWrite8 (uint32_t Address, uint8_t Value)
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{
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xUSLPciExpressWrite8 ((void*)(size_t)Address, Value);
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}
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/**
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* @brief Read 16-bit PCI register
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* @param Address 32-bit PCI address that encodes the PCI Bus, Device, Function and Register
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*
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*/
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uint16_t xUSLPciRead16 (uint32_t Address)
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{
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return xUSLPciExpressRead16 ((void*)(size_t)Address);
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}
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/**
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* @brief Write 16-bit PCI register
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* @param Address 32-bit PCI address that encodes the PCI Bus, Device, Function and Register
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* @param Value The value to be written in Address.
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*
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*/
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void xUSLPciWrite16 (uint32_t Address, uint16_t Value)
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{
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xUSLPciExpressWrite16 ((void*)(size_t)Address, Value);
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}
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/**
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* @brief Read 32-bit PCI register
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* @param Address 32-bit PCI address that encodes the PCI Bus, Device, Function and Register
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*
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*/
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uint32_t xUSLPciRead32 (uint32_t Address)
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{
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return xUSLPciExpressRead32 ((void*)(size_t)Address);
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}
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/**
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* @brief Write 32-bit PCI register
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* @param Address 32-bit PCI address that encodes the PCI Bus, Device, Function and Register
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* @param Value The value to be written in Address.
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*
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*/
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void xUSLPciWrite32 (uint32_t Address, uint32_t Value)
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{
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xUSLPciExpressWrite32 ((void*)(size_t)Address, Value);
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}
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/**
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* @brief Read 64-bit PCI register
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* @param Address 32-bit PCI address that encodes the PCI Bus, Device, Function and Register
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*
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*/
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uint64_t xUSLPciRead64 (uint32_t Address)
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{
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return xUSLPciExpressRead64 ((void*)(size_t)Address);
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}
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/**
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* @brief Write 64-bit PCI register
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* @param Address 32-bit PCI address that encodes the PCI Bus, Device, Function and Register
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* @param Value The value to be written in Address.
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*
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*/
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void xUSLPciWrite64 (uint32_t Address, uint64_t Value)
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{
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xUSLPciExpressWrite64 ((void*)(size_t)Address, Value);
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}
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/**
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* @brief Modify 8-bit PCI register using AND mask and OR mask
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* @param Address 32-bit PCI address that encodes the PCI Bus, Device, Function and Register
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* @param AndMask 8-bit value to AND with the value at Address
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* @param OrMask 8-bit value to OR with the value at Address
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*/
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void xUSLPciReadModifyWrite8(uint32_t Address, uint8_t AndMask, uint8_t OrMask)
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{
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uint8_t Value;
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Value = xUSLPciRead8(Address);
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Value &= AndMask;
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Value |= OrMask;
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xUSLPciWrite8(Address, Value);
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}
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/**
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* @brief Modify 16-bit PCI register using AND mask and OR mask
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* @param Address 32-bit PCI address that encodes the PCI Bus, Device, Function and Register
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* @param AndMask 16-bit value to AND with the value at Address
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* @param OrMask 16-bit value to OR with the value at Address
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*
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*/
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void xUSLPciReadModifyWrite16(uint32_t Address, uint16_t AndMask, uint16_t OrMask)
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{
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uint16_t Value;
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Value = xUSLPciRead16(Address);
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Value &= AndMask;
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Value |= OrMask;
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xUSLPciWrite16(Address, Value);
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}
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/**
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* @brief Modify 32-bit PCI register using AND mask and OR mask
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* @param Address 32-bit PCI address that encodes the PCI Bus, Device, Function and Register
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* @param AndMask 32-bit value to AND with the value at Address
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* @param OrMask 32-bit value to OR with the value at Address
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*
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*/
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void xUSLPciReadModifyWrite32(uint32_t Address, uint32_t AndMask, uint32_t OrMask)
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{
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uint32_t Value;
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Value = xUSLPciRead32(Address);
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Value &= AndMask;
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Value |= OrMask;
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xUSLPciWrite32(Address, Value);
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}
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/**
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* @brief Indirect Pci Read Access
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* @param PciBase 32-bit PCI base address of indirect register
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* @param IndexAddress Offset of indirect register
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* @param Value pointer to hold read value.
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*
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*/
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void xUSLIndirectPciRead32 (volatile uint32_t PciBase, uint32_t IndexAddress, uint32_t *Value)
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{
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PciBase |= 0xB8;
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xUSLPciWrite32 (PciBase, IndexAddress);
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*Value = xUSLPciRead32 (PciBase + sizeof(uint32_t));
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}
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/**
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* @brief Indirect Pci Write Access
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* @param PciBase 32-bit PCI base address of indirect register
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* @param IndexAddress Offset of indirect register
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* @param Value The value to be written.
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*
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*/
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void xUSLIndirectPciWrite32 (volatile uint32_t PciBase, uint32_t IndexAddress, uint32_t Value)
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{
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PciBase |= 0xB8;
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xUSLPciWrite32 (PciBase, IndexAddress);
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xUSLPciWrite32 (PciBase + sizeof(uint32_t), Value);
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Read PCI registers
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*
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*
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*
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* @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue)
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* @param[in] Width Access width
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* @param[out] Value Pointer to value
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*/
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void
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xUSLPciRead (uint32_t Address, ACCESS_WIDTH Width, void *Value)
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{
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switch (Width) {
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case AccessWidth8:
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case AccessS3SaveWidth8:
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*((uint8_t *) Value) = xUSLPciRead8 (Address);
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break;
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case AccessWidth16:
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case AccessS3SaveWidth16:
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*((uint16_t *) Value) = xUSLPciRead16 (Address);
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break;
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case AccessWidth32:
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case AccessS3SaveWidth32:
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*((uint32_t *) Value) = xUSLPciRead32 (Address);
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break;
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default:
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XUSL_TRACEPOINT (SIL_TRACE_ERROR, "Invalid Pci Read access width.\n");
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}
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Read/Modify/Write PCI registers
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*
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*
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*
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* @param[in] Address PCI address
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* @param[in] Width Access width
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* @param[in] Mask AND Mask
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* @param[in] Value OR Value
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*/
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void xUSLPciRMW(uint32_t Address, ACCESS_WIDTH Width, uint32_t Mask, uint32_t Value)
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{
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uint32_t Data;
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xUSLPciRead (Address, Width, &Data);
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Data = (Data & Mask) | Value;
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xUSLPciWrite (Address, Width, &Data);
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Write PCI registers
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*
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*
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*
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* @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue)
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* @param[in] Width Access width
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* @param[in] Value Pointer to value
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* @param[in] StdHeader Pointer to standard header
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*/
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void xUSLPciWrite (uint32_t Address, ACCESS_WIDTH Width, void *Value)
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{
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switch (Width) {
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case AccessWidth8:
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case AccessS3SaveWidth8:
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xUSLPciWrite8 (Address, *((uint8_t *) Value));
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break;
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case AccessWidth16:
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case AccessS3SaveWidth16:
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xUSLPciWrite16 (Address, *((uint16_t *) Value));
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break;
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case AccessWidth32:
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case AccessS3SaveWidth32:
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xUSLPciWrite32 (Address, *((uint32_t *) Value));
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break;
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default:
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XUSL_TRACEPOINT (SIL_TRACE_ERROR, "Invalid Pci access width.\n");
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}
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} |