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203 lines
8.9 KiB
C
203 lines
8.9 KiB
C
/**
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* @file CpuLib.h
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* @brief CPU registers type definition, CPU functions prototype
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*/
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/* Copyright 2021-2023 Advanced Micro Devices, Inc. All rights reserved. */
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// SPDX-License-Identifier: MIT
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#pragma once
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#include <stdint.h>
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/// Native Die CPUID PCI Register
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typedef struct {
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uint32_t Stepping:4; ///< Stepping
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uint32_t BaseModel:4; ///< Base Model
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uint32_t BaseFamily:4; ///< Base Family
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uint32_t :4; ///< Reserved
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uint32_t ExtModel:4; ///< Extended Model
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uint32_t ExtFamily:8; ///< Extended Family
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uint32_t :4; ///< Reserved
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} NATIVE_DIE_CPUID_REGISTER;
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/// CPUID data received registers format
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typedef struct {
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uint32_t EaxReg; ///< CPUID instruction result in EAX
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uint32_t EbxReg; ///< CPUID instruction result in EBX
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uint32_t EcxReg; ///< CPUID instruction result in ECX
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uint32_t EdxReg; ///< CPUID instruction result in EDX
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} CPUID_DATA;
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/// CPUID related registers
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#define AMD_CPUID_FMF 0x80000001ul // Family Model Features information
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#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006ul
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#define CPUID_ASSOCIATIVITY_DISABLED 0x00
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#define CPUID_ASSOCIATIVITY_1_WAY 0x01
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#define CPUID_ASSOCIATIVITY_2_WAY 0x02
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#define CPUID_ASSOCIATIVITY_4_WAY 0x04
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#define CPUID_ASSOCIATIVITY_8_WAY 0x06
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#define CPUID_ASSOCIATIVITY_16_WAY 0x08
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#define CPUID_ASSOCIATIVITY_32_WAY 0x0A
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#define CPUID_ASSOCIATIVITY_48_WAY 0x0B
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#define CPUID_ASSOCIATIVITY_64_WAY 0x0C
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#define CPUID_ASSOCIATIVITY_96_WAY 0x0D
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#define CPUID_ASSOCIATIVITY_128_WAY 0x0E
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#define CPUID_ASSOCIATIVITY_FULLY 0x0F
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#define AMD_CPUID_TLB_L1Cache 0x80000005ul
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#define AMD_CPUID_L1L2Tlb1GIdentifiers 0x80000019ul
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#define AMD_CPUID_APM 0x80000007ul
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#define LOCAL_APIC_ID 24
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#define LOGICAL_PROCESSOR_COUNT 16
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#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008ul // Address Size, Physical Core Count
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// CPUID
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#define CPUID_PROCESSOR_TOPOLOGY_INFORMATION 0x8000001Eul
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#define CPUID_PROCESSOR_AND_FEATURE_IDENTIFIERS 0x00000001ul
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#define CPUID_PROCESSOR_CAPACITY_PARAMETERS 0x80000008ul
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//
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// Memory cache types
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//
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typedef enum {
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CacheUncacheable = 0,
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CacheWriteCombining = 1,
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CacheWriteThrough = 4,
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CacheWriteProtected = 5,
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CacheWriteBack = 6,
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CacheInvalid = 7
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} MTRR_MEMORY_CACHE_TYPE;
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#define AMD_AP_MTRR_VARIABLE_BASE0 0x200
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#define AMD_AP_MTRR_VARIABLE_BASE6 0x20C
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#define AMD_AP_MTRR_FIX64k_00000 0x250
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#define AMD_AP_MTRR_FIX16k_80000 0x258
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#define AMD_AP_MTRR_FIX16k_A0000 0x259
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#define AMD_AP_MTRR_FIX4k_C0000 0x268
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#define AMD_AP_MTRR_FIX4k_C8000 0x269
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#define AMD_AP_MTRR_FIX4k_D0000 0x26A
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#define AMD_AP_MTRR_FIX4k_D8000 0x26B
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#define AMD_AP_MTRR_FIX4k_E0000 0x26C
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#define AMD_AP_MTRR_FIX4k_E8000 0x26D
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#define AMD_AP_MTRR_FIX4k_F0000 0x26E
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#define AMD_AP_MTRR_FIX4k_F8000 0x26F
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#define AMD_MTRR_FIX64K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
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#define AMD_MTRR_FIX64K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
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#define AMD_MTRR_FIX64K_UC_DRAM 0x1818181818181818ull
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#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
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#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
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#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818ull
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#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
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#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
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#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818ull
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#define ENABLE_CF8_EXT_CFG 0x00004000ul // [46]
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#define INIT_APIC_CPUID_LO 0x00400000ul // [54]
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#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFFull // Mask of the Performance control Reserve bits
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#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2ul // Configure the controller to capture the
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// CAR Corruption
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// FUNC_0 registers
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// ----------------
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#define LINK_INIT_CTRL 0x6C
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#define LINK_INIT_CTRL_REQ_DIS 0x02 // [1] = ReqDis
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#define LINK_INIT_COLD_RST_DET BIT4
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#define LINK_INIT_BIOS_RST_DET_0 BIT5
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#define LINK_INIT_BIOS_RST_DET_1 BIT9
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#define LINK_INIT_BIOS_RST_DET_2 BIT10
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#define LINK_INIT_BIOS_RST_DET BIT9 | BIT10
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#define EXTENDED_NODE_ID 0x160
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#define CORE_CTRL 0x1DC
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#define CORE_CTRL_CORE1_EN 0x00000002ul
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#define CORE_CTRL_CORE2_EN 0x00000004ul
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#define CORE_CTRL_CORE3_EN 0x00000008ul
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#define CORE_CTRL_CORE4_EN 0x00000010ul
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#define CORE_CTRL_CORE5_EN 0x00000020ul
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#define CORE_CTRL_CORE6_EN 0x00000040ul
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#define CORE_CTRL_CORE7_EN 0x00000080ul
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#define CORE_CTRL_CORE8_EN 0x00000100ul
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#define CORE_CTRL_CORE9_EN 0x00000200ul
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// FUNC_3 registers
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// ----------------
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#define HARDWARE_THERMAL_CTRL_REG 0x64
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#define SOFTWARE_THERMAL_CTRL_REG 0x68
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#define ACPI_PSC_0_REG 0x80 // ACPI Power State Control Registers
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#define ACPI_PSC_4_REG 0x84
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#define POWER_CTRL_MISCELLANEOUS_REG 0xA0
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#define CLOCK_POWER_TIMING_CTRL2_REG 0xDC
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#define NORTH_BRIDGE_CAPABILITIES_REG 0xE8
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#define MULTI_NODE_CPU 29
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#define CPUID_FMR 0xFC // Family / Model registers
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#define DOWNCORE_CTRL 0x190 // Downcore Control Register
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#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148
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#define REG_HT4_PHY_OFFSET_BASE_4X180 0x180
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#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184
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// FUNC_4 registers
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// ----------------
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/* Native Die CPUID Register F4x160 */
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#define NATIVE_DIE_CPUID_REG 0x160
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#define NATIVE_DIE_CPUID_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, NATIVE_DIE_CPUID_REG))
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// FUNC_5 registers
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// ----------------
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#define COMPUTE_UNIT_STATUS 0x80
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#define NORTH_BRIDGE_CAPABILITIES_2_REG 0x84
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// Misc. defines.
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#define PCI_DEV_BASE 24
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#define CPUID_STEPPING_MASK 0x0000000Ful
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#define CPUID_BASE_MODEL_MASK 0x000000F0ul
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#define CPUID_BASE_FAMILY_MASK 0x00000F00ul
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#define CPUID_EXT_MODEL_MASK 0x000F0000ul
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#define CPUID_EXT_FAMILY_MASK 0x0FF00000ul
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#define CPUID_BASE_MODEL_OFFSET 4
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#define CPUID_BASE_FAMILY_OFFSET 8
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#define CPUID_EXT_MODEL_OFFSET 16
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#define CPUID_EXT_FAMILY_OFFSET 20
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#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull
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#define APIC_EXT_BRDCST_MASK 0x000E0000ul
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#define APIC_ENABLE_BIT 0x00000800ul
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#define LOCAL_APIC_ADDR 0xFEE00000ul
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#define INT_CMD_REG_LO 0x300
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#define INT_CMD_REG_HI 0x310
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#define REMOTE_MSG_REG 0x380
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#define REMOTE_READ_REG 0xC0
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#define APIC_ID_REG 0x20
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#define APIC20_ApicId 24
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#define CMD_REG_TO_READ_DATA 0x338
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#define MAX_CORE_ID_SIZE 8
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#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1)
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/*-------------------------
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* Default definitions
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*-------------------------
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*/
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#define DELIVERY_STATUS BIT13
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#define REMOTE_READ_STAT_MASK 0x00030000ul
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#define REMOTE_DELIVERY_PENDING 0x00010000ul
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#define REMOTE_DELIVERY_DONE 0x00020000ul
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void xUslCpuSleep (void);
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uint8_t xUslGetThreadsPerCore (void);
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uint32_t xUslGetPackageType (void);
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uint32_t xUslGetInitialApicId (void);
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void xUslWrMsr (uint32_t MsrAddress, uint64_t MsrValue);
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uint64_t xUslRdMsr (uint32_t MsrAddress);
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uint8_t xUslGetPhysAddrSize (void);
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uint8_t xUslGetPhysAddrReduction (void);
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uint32_t xUslGetRawIdOnExecutingCore (void);
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void xUslMsrAnd (uint32_t Index, uint64_t AndData);
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uint32_t xUslIsSmtDisabled(void);
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uint32_t xUslGetProcessorId(void);
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void xUslMsrOr (uint32_t Index, uint64_t OrData);
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void xUslMsrAndThenOr (uint32_t Index, uint64_t AndData, uint64_t OrData);
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void xUslWbinvd(void);
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uint32_t xUslGetSecureEncryption(void);
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uint64_t xUslReadCr3(void);
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