Florent Kermarrec
69451fad09
test/test_cpu: Disable test_cva6 for now since seems to be failing.
2022-05-25 09:32:30 +02:00
Massimiliano Giacometti
c95ddbbff8
UART_POLLING
2022-05-19 15:07:46 +02:00
Robert Szczepanski
22abe1d543
Add tests for FIFOSyncMacro
2022-04-27 10:53:52 +02:00
Rafal Kolucki
8c1bc139ab
soc/interconnect/wishbone: Cleanup in burst cycles support logic
2022-04-12 15:32:29 +02:00
Rafal Kolucki
ad46a57403
test/test_wishbone: Add test for Wishbone SRAM constant address burst cycle
2022-04-12 14:06:22 +02:00
Rafal Kolucki
cdd216f692
test/test_wishbone: Add basic test for SRAM with burst cycles support
...
Tests incrementing address burst cycle with linear and wrapped increments.
Only 4-beat wrap burst is tested in `test_sram_burst_wrap` test.
2022-04-12 14:06:22 +02:00
Florent Kermarrec
ed6a6a83a9
litex_setup: Switch to manual install for Amaranth/Minerva (No longer supporting Python 3.6).
...
We could revert when upgrading LiteX python requirement.
2022-04-04 15:39:05 +02:00
Florent Kermarrec
d39c3ed626
soc/cores/led: Review/Rework #1265 .
...
- Split FSM in Main FSM/Xfer FSM to decouple Led data read from bit xfer and do read during xfer.
- Only keep optimization that are easily to understand.
- Default to new WS2812 revision (Since also works on old revision).
- Test 75/50/25MHz sys_clk_freq.
2022-04-04 15:24:54 +02:00
Wolfgang Nagele
67369403a9
Improve WS2812 timings and add different hardware revision support
2022-04-03 17:09:56 +02:00
Florent Kermarrec
6ef96b17bc
soc/interconnect/csr: Fix CSRConstant read method (And add test_csr_constant to test_csr).
2022-03-21 15:21:08 +01:00
Florent Kermarrec
dbde036162
soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus.
...
The generic version of the HyperRAM core is simple enough to be directly integrated in LiteX
which avoid an additional dependency.
2022-03-01 09:11:55 +01:00
Florent Kermarrec
f62eca77e3
test/test_axi: Minor cleanups.
2022-02-17 15:13:05 +01:00
Florent Kermarrec
77c6cdd78e
cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency.
2022-01-25 11:09:15 +01:00
Florent Kermarrec
ea6bb3dd80
test/test_clock: Add minimal ECP5Delay test (syntax), rename tests with underscore.
2022-01-25 10:49:33 +01:00
Florent Kermarrec
e50ff33c6e
test/test_cpu: Disable Minerva test for now.
2021-12-13 16:51:23 +01:00
Florent Kermarrec
12d53790a9
test/test_cpu: Prepare microwatt/lm32 test.
...
microwatt: Still requires Yoys/GHDL-Synth installation.
lm32: Still requires prebuilt toolchain.
2021-10-26 16:37:38 +02:00
Florent Kermarrec
e617f52e34
test/test_cpu: Comment test_mor1kx for now (test work but issue seems related to the pre-built toolchain).
2021-10-26 16:30:02 +02:00
Florent Kermarrec
cb9f0fb1b0
ci/test_cpu: Install OpenRISC GCC toolchain in CI and add mor1kx to test_cpu.
2021-10-26 15:45:43 +02:00
Florent Kermarrec
71a91eac15
test: Rename test_boot.py to test_cpu.py.
2021-10-26 08:35:16 +02:00
Florent Kermarrec
47b3c9bc08
soc/interconnect/packet: Remove last_be support in LiteX, specialized Packetizer/Depacketizer have been moved to LiteEth to simplify development and avoid eventual regresion on others cores.
...
As seen during the last LiteEth developments, last_be data qualifier is not easy to handle correctly and should be replaced by a simpler data qualifier (similar to AXI's tkeep/tstrb). It will
be easier to do so by having a local copy of Packetizer/Depacketizer directly in LiteEth (still with last_be support) and work on the simpler data qualifier in LiteX (and test it on LitePCIe).
2021-10-25 11:17:36 +02:00
Navaneeth Bhardwaj
2886fe1701
Add bios test mode for CI ( #1076 )
...
* Add bios test mode for CI
This enables to test the booting of each CPU configurations with the bios in Verilator simulation.
2021-10-24 12:08:58 +02:00
Florent Kermarrec
8e448592f0
interconnect/packet: Revert old last/ready logic handling (new one breaks test_packet) and comment out test_packet2 tests (does not seems to be working with previous last/ready handling).
2021-10-23 18:21:47 +02:00
Florent Kermarrec
59fd2d31c7
test/test_packet2: Fix imports.
2021-10-23 17:54:00 +02:00
Florent Kermarrec
32bb2554bc
test: Rename new test_packet/stream to test_packet2/stream2 and revert old tests.
...
Old and new tests are complementary and would need to be merged.
2021-10-23 17:40:41 +02:00
enjoy-digital
434b3a3654
Merge pull request #1008 from lschuermann/dev/packetizer-last_be-fix
...
{Dep,P}acketizer: properly handle last_be wraparound
2021-10-23 17:33:29 +02:00
