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soc/cores/interconnect: Rely on WaitTimer's new automatic cast to int.

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This commit is contained in:
Florent Kermarrec
2023-07-31 11:32:48 +02:00
parent bf79c9032a
commit e257ff916f
7 changed files with 19 additions and 19 deletions
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10
litex/soc/cores/esc.py
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@@ -141,15 +141,15 @@ class ESCDShot(LiteXModule):
timings.compute()
# Timers.
t0h_timer = WaitTimer(int(timings.t0h*sys_clk_freq))
t0l_timer = WaitTimer(int(timings.t0l*sys_clk_freq) - 1) # Compensate Xfer FSM latency.
t0h_timer = WaitTimer(timings.t0h*sys_clk_freq)
t0l_timer = WaitTimer(timings.t0l*sys_clk_freq - 1) # Compensate Xfer FSM latency.
self.submodules += t0h_timer, t0l_timer
t1h_timer = WaitTimer(int(timings.t1h*sys_clk_freq))
t1l_timer = WaitTimer(int(timings.t1l*sys_clk_freq) - 1) # Compensate Xfer FSM latency.
t1h_timer = WaitTimer(timings.t1h*sys_clk_freq)
t1l_timer = WaitTimer(timings.t1l*sys_clk_freq - 1) # Compensate Xfer FSM latency.
self.submodules += t1h_timer, t1l_timer
tgap_timer = WaitTimer(int(timings.tgap*sys_clk_freq))
tgap_timer = WaitTimer(timings.tgap*sys_clk_freq)
self.submodules += tgap_timer
# XFER FSM.

2
litex/soc/cores/hyperbus.py
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@@ -66,7 +66,7 @@ class HyperRAM(LiteXModule):
# Burst Timer ------------------------------------------------------------------------------
sys_clk_freq = 10e6 if sys_clk_freq is None else sys_clk_freq
burst_timer = WaitTimer(int(sys_clk_freq*self.tCSM))
burst_timer = WaitTimer(sys_clk_freq*self.tCSM)
self.burst_timer = burst_timer
# Clock Generation (sys_clk/4) -------------------------------------------------------------

12
litex/soc/cores/led.py
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@@ -32,7 +32,7 @@ class LedChaser(LiteXModule):
chaser = Signal(self.n)
mode = Signal(reset=_CHASER_MODE)
timer = WaitTimer(int(period*sys_clk_freq/(2*self.n)))
timer = WaitTimer(period*sys_clk_freq/(2*self.n))
leds = Signal(self.n)
self.submodules += timer
self.comb += timer.wait.eq(~timer.done)
@@ -165,15 +165,15 @@ class WS2812(LiteXModule):
self.t1l = t1l = 0.45e-6
# Timers.
trst_timer = WaitTimer(int(trst*sys_clk_freq))
trst_timer = WaitTimer(trst*sys_clk_freq)
self.submodules += trst_timer
t0h_timer = WaitTimer(int(t0h*sys_clk_freq))
t0l_timer = WaitTimer(int(t0l*sys_clk_freq) - 1) # Compensate Xfer FSM latency.
t0h_timer = WaitTimer(t0h*sys_clk_freq)
t0l_timer = WaitTimer(t0l*sys_clk_freq - 1) # Compensate Xfer FSM latency.
self.submodules += t0h_timer, t0l_timer
t1h_timer = WaitTimer(int(t1h*sys_clk_freq))
t1l_timer = WaitTimer(int(t1l*sys_clk_freq) - 1) # Compensate Xfer FSM latency.
t1h_timer = WaitTimer(t1h*sys_clk_freq)
t1l_timer = WaitTimer(t1l*sys_clk_freq - 1) # Compensate Xfer FSM latency.
self.submodules += t1h_timer, t1l_timer
# Main FSM.

4
litex/soc/cores/uart.py
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@@ -293,7 +293,7 @@ class UART(LiteXModule, UARTInterface):
# Flush TX FIFO when Source.ready is inactive for timeout (with interval cycles between
# each ready).
self.timer = timer = WaitTimer(int(timeout*sys_clk_freq))
self.timer = timer = WaitTimer(timeout*sys_clk_freq)
self.comb += timer.wait.eq(~self.source.ready)
self.sync += flush_count.eq(flush_count + 1)
self.comb += If(timer.done, flush_ep.ready.eq(flush_count == 0))
@@ -330,7 +330,7 @@ class Stream2Wishbone(LiteXModule):
words_count_done = (words_count == (length - 1))
self.fsm = fsm = ResetInserter()(FSM(reset_state="RECEIVE-CMD"))
self.timer = timer = WaitTimer(int(100e-3*clk_freq))
self.timer = timer = WaitTimer(100e-3*clk_freq)
self.comb += timer.wait.eq(~fsm.ongoing("RECEIVE-CMD"))
self.comb += fsm.reset.eq(timer.done)
fsm.act("RECEIVE-CMD",

4
litex/soc/interconnect/axi/axi_full.py
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@@ -371,8 +371,8 @@ class AXITimeout(LiteXModule):
self.comb += self.error.eq(wr_error | rd_error)
wr_timer = WaitTimer(int(cycles))
rd_timer = WaitTimer(int(cycles))
wr_timer = WaitTimer(cycles)
rd_timer = WaitTimer(cycles)
self.submodules += wr_timer, rd_timer
def channel_fsm(timer, wait_cond, error, response):

4
litex/soc/interconnect/axi/axi_lite.py
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@@ -525,8 +525,8 @@ class AXILiteTimeout(LiteXModule):
self.comb += self.error.eq(wr_error | rd_error)
wr_timer = WaitTimer(int(cycles))
rd_timer = WaitTimer(int(cycles))
wr_timer = WaitTimer(cycles)
rd_timer = WaitTimer(cycles)
self.submodules += wr_timer, rd_timer
def channel_fsm(timer, wait_cond, error, response):

2
litex/soc/interconnect/wishbone.py
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@@ -130,7 +130,7 @@ class Timeout(Module):
# # #
timer = WaitTimer(int(cycles))
timer = WaitTimer(cycles)
self.submodules += timer
self.comb += [
timer.wait.eq(master.stb & master.cyc & ~master.ack),