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CHANGES: Update.

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Florent Kermarrec
2022-02-17 10:36:05 +01:00
parent c494ea231b
commit d0dc5c8d95
1 changed files with 4 additions and 0 deletions
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@@ -26,6 +26,10 @@
- cores/jtag: Add initial JTAG-UART/JTAGBone Altera/Intel support.
- LiteScope: Add Samplerate support.
- cores/bitbang: Add optional I2C initialization by CPU.
- libliteeth/tftp: Add blocksize support an increase to 1024 bytes (allow 64MB filesize).
- soc/add_sdram: Make AXI integration more flexible (remove some specific Rocket hardcoding).
- cpu/neorv32: Add initial support (RV32I, VHDL converted to Verilog through GHDL-Yosys-synth).
- cpu/naxriscv: Add initial support (RV32IMA, already able to run Linux).
[> API changes/Deprecation
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