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https://github.com/Dasharo/litex.git
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build/efinix/ifacewriter: adding method to generate lvds python code
This commit is contained in:
Gwenhael Goavec-Merou
@@ -72,8 +72,6 @@ class InterfaceWriter:
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if isinstance(block, InterfaceWriterXMLBlock):
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block.generate(root, namespaces)
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else:
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if block["type"] == "LVDS":
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self.add_lvds_xml(root, block)
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if block["type"] == "DRAM":
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self.add_dram_xml(root, block)
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@@ -367,6 +365,66 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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cmds.append(f"# ---------- END JTAG {id} ---------\n")
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return "\n".join(cmds)
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def generate_lvds(self, block, verbose=True):
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name = block["name"]
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mode = block["mode"]
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location = block["location"]
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size = block["size"]
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sig = block["sig"]
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cmd = []
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if mode == "INPUT":
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block_type = "LVDS_TX"
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tx_mode = block["tx_mode"]
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cmd.append('design.create_block("{}", block_type="{}", tx_mode="{}")'.format(name, block_type, tx_mode))
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cmd.append('design.set_property("{}", "TX_DELAY", "0", "{}")'.format(name, block_type))
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cmd.append('design.set_property("{}", "TX_DIFF_TYPE", "LVDS", "{}")'.format(name, block_type))
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cmd.append('design.set_property("{}", "TX_EN_SER", "0", "{}")'.format(name, block_type))
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cmd.append('design.set_property("{}", "TX_FASTCLK_PIN", "", "{}")'.format(name, block_type))
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cmd.append('design.set_property("{}", "TX_HALF_RATE", "0", "{}")'.format(name, block_type))
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cmd.append('design.set_property("{}", "TX_MODE", "{}", "{}")'.format(name, tx_mode, block_type))
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cmd.append('design.set_property("{}", "TX_OE_PIN", "", "{}")'.format(name, block_type))
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cmd.append('design.set_property("{}", "TX_OUT_PIN", "{}", "{}")'.format(name, sig.name, block_type))
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cmd.append('design.set_property("{}", "TX_PRE_EMP", "MEDIUM_LOW", "{}")'.format(name, block_type))
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cmd.append('design.set_property("{}", "TX_RST_PIN", "", "{}")'.format(name, block_type))
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cmd.append('design.set_property("{}", "TX_SER", "{}", "{}")'.format(name, size, block_type))
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cmd.append('design.set_property("{}", "TX_SLOWCLK_PIN", "", "{}")'.format(name, block_type))
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cmd.append('design.set_property("{}", "TX_VOD", "TYPICAL", "{}")'.format(name, block_type))
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else:
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# FIXME: untested
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block_type = "LVDS_RX"
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rx_mode = block["rx_mode"]
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cmd.append('design.create_block("{}", block_type="{}", rx_conn_type="{}")'.format(name, block_type, rx_mode))
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cmd.append('design.set_property("{}","GBUF","","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_CONN_TYPE","{}","{}")'.format(name, block_type, rx_mode))
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cmd.append('design.set_property("{}","RX_DBG_PIN","","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_DELAY","16","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_DELAY_MODE","STATIC","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_DESER","1","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_DLY_ENA_PIN","lvds_rx_inst1_RX_DLY_ENA","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_DLY_INC_PIN","lvds_rx_inst1_RX_DLY_INC","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_DLY_RST_PIN","lvds_rx_inst1_RX_DLY_RST","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_ENA_PIN","","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_EN_DESER","0","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_FASTCLK_PIN","","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_FIFO","0","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_FIFOCLK_PIN","","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_FIFO_EMPTY_PIN","lvds_rx_inst1_RX_FIFO_EMPTY","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_FIFO_RD_PIN","lvds_rx_inst1_RX_FIFO_RD","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_HALF_RATE","0","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_IN_PIN","lvds_rx_inst1_RX_DATA","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_LOCK_PIN","lvds_rx_inst1_RX_LOCK","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_RST_PIN","lvds_rx_inst1_RX_RST","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_SLOWCLK_PIN","","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_SLVS","0","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_TERM","ON","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_TERM_PIN","lvds_rx_inst1_RX_TERM","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_VOC_DRIVER","0","{}")'.format(name, block_type))
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cmd.append('design.assign_resource("{}", "{}", "{}")\n'.format(name, location, block_type))
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return '\n'.join(cmd)
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def generate(self, partnumber):
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output = ""
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for block in self.blocks:
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@@ -381,6 +439,8 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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output += self.generate_mipi_tx(block)
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if block["type"] == "MIPI_RX_LANE":
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output += self.generate_mipi_rx(block)
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if block["type"] == "LVDS":
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output += self.generate_lvds(block)
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if block["type"] == "JTAG":
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output += self.generate_jtag(block)
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return output
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@@ -393,45 +453,6 @@ design.generate(enable_bitstream=True)
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design.save()"""
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def add_lvds_xml(self, root, params):
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lvds_info = root.find("efxpt:lvds_info", namespaces)
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if params["mode"] == "OUTPUT":
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dir = "tx"
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mode = "out"
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else:
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dir = "rx"
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mode = "in"
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pad = self.platform.parser.get_pad_name_from_pin(params["location"][0])
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pad = pad.replace("TXP", "TX")
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pad = pad.replace("TXN", "TX")
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pad = pad.replace("RXP", "RX")
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pad = pad.replace("RXN", "RX")
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# Sometimes there is an extra identifier at the end
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# TODO: do a better parser
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if pad.count("_") == 2:
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pad = pad.rsplit("_", 1)[0]
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lvds = et.SubElement(lvds_info, "efxpt:lvds",
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name = params["name"],
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lvds_def = pad,
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ops_type = dir
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)
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et.SubElement(lvds, "efxpt:ltx_info",
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pll_instance = "",
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fast_clock_name = "{}".format(params["fast_clk"]),
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slow_clock_name = "{}".format(params["slow_clk"]),
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reset_name = "",
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out_bname = "{}".format(params["name"]),
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oe_name = "",
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clock_div = "1",
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mode = "{}".format(mode),
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serialization = "{}".format(params["serialisation"]),
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reduced_swing = "false",
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load = "3"
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)
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def add_iobank_info_xml(self, root, iobank_info):
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dev = root.find("efxpt:device_info", namespaces)
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bank_info = dev.find("efxpt:iobank_info", namespaces)
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