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Add verilog submodule from CPU cores to manifest

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This commit is contained in:
Arnaud Durand
2019-07-04 00:58:26 +02:00
committed by GitHub
parent 4ee9c53f18
commit 68eeba9181
1 changed files with 4 additions and 1 deletions
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5
MANIFEST.in
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@@ -1,5 +1,8 @@
graft litex/build/sim
graft litex/soc/software
graft litex/soc/cores/cpu/lm32/verilog
graft litex/soc/cores/cpu/minerva/verilog
graft litex/soc/cores/cpu/mor1kx/verilog
graft litex/soc/cores/cpu/picorv32/verilog
graft litex/soc/cores/cpu/picorv32/verilog
graft litex/soc/cores/cpu/rocket/verilog
graft litex/soc/cores/cpu/vexriscv/verilog