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replace litex.gen imports with migen imports

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This commit is contained in:
Florent Kermarrec
2018-02-23 13:38:19 +01:00
parent 43164b9a2c
commit 1925ba176f
57 changed files with 141 additions and 138 deletions
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4
litex/boards/targets/arty.py
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@@ -2,8 +2,8 @@
import argparse
from litex.gen import *
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import arty

3
litex/boards/targets/de0nano.py
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@@ -2,7 +2,8 @@
import argparse
from litex.gen import *
from migen import *
from litex.boards.platforms import de0nano
from litex.soc.integration.soc_sdram import *

4
litex/boards/targets/kc705.py
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@@ -2,8 +2,8 @@
import argparse
from litex.gen import *
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import kc705

5
litex/boards/targets/minispartan6.py
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@@ -3,8 +3,9 @@
import argparse
from fractions import Fraction
from litex.gen import *
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import minispartan6
from litex.soc.integration.soc_sdram import *

4
litex/boards/targets/nexys4ddr.py
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@@ -2,8 +2,8 @@
import argparse
from litex.gen import *
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import nexys4ddr

4
litex/boards/targets/nexys_video.py
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@@ -2,8 +2,8 @@
import argparse
from litex.gen import *
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import nexys_video

5
litex/boards/targets/sim.py
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@@ -3,9 +3,10 @@
import argparse
import importlib
from litex.gen import *
from migen import *
from migen.genlib.io import CRG
from litex.boards.platforms import sim
from litex.gen.genlib.io import CRG
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *

4
litex/boards/targets/simple.py
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@@ -3,8 +3,8 @@
import argparse
import importlib
from litex.gen import *
from litex.gen.genlib.io import CRG
from migen import *
from migen.genlib.io import CRG
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *

6
litex/build/altera/common.py
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@@ -1,6 +1,6 @@
from litex.gen.fhdl.module import Module
from litex.gen.fhdl.specials import Instance
from litex.gen.genlib.io import DifferentialInput, DifferentialOutput
from migen.fhdl.module import Module
from migen.fhdl.specials import Instance
from migen.genlib.io import DifferentialInput, DifferentialOutput
class AlteraDifferentialInputImpl(Module):

2
litex/build/altera/quartus.py
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@@ -4,7 +4,7 @@
import os
import subprocess
from litex.gen.fhdl.structure import _Fragment
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import Pins, IOStandard, Misc
from litex.build import tools

9
litex/build/generic_platform.py
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@@ -1,9 +1,10 @@
import os
from litex.gen.fhdl.structure import Signal
from litex.gen.genlib.record import Record
from litex.gen.genlib.io import CRG
from litex.gen.fhdl import verilog
from migen.fhdl.structure import Signal
from migen.genlib.record import Record
from migen.genlib.io import CRG
from migen.fhdl import verilog
from litex.build import tools

8
litex/build/lattice/common.py
View File

@@ -1,7 +1,7 @@
from litex.gen.fhdl.module import Module
from litex.gen.fhdl.specials import Instance
from litex.gen.genlib.io import *
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from migen.fhdl.module import Module
from migen.fhdl.specials import Instance
from migen.genlib.io import *
from migen.genlib.resetsync import AsyncResetSynchronizer
class DiamondAsyncResetSynchronizerImpl(Module):

4
litex/build/lattice/diamond.py
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@@ -6,8 +6,8 @@ import sys
import subprocess
import shutil
from litex.gen.fhdl.structure import _Fragment
from litex.gen.fhdl.verilog import DummyAttrTranslate
from migen.fhdl.structure import _Fragment
from migen.fhdl.verilog import DummyAttrTranslate
from litex.build.generic_platform import *
from litex.build import tools

2
litex/build/lattice/icestorm.py
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@@ -5,7 +5,7 @@ import os
import sys
import subprocess
from litex.gen.fhdl.structure import _Fragment
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import *
from litex.build import tools

5
litex/build/sim/platform.py
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@@ -1,5 +1,6 @@
from litex.gen.fhdl.structure import Signal
from litex.gen.genlib.record import Record
from migen.fhdl.structure import Signal
from migen.genlib.record import Record
from litex.build.generic_platform import GenericPlatform
from litex.build.sim import common, verilator

3
litex/build/sim/verilator.py
View File

@@ -5,7 +5,8 @@
import os
import subprocess
from litex.gen.fhdl.structure import _Fragment
from migen.fhdl.structure import _Fragment
from litex.build import tools
from litex.build.generic_platform import *

12
litex/build/xilinx/common.py
View File

@@ -11,12 +11,12 @@ try:
except ImportError:
_have_colorama = False
from litex.gen.fhdl.structure import *
from litex.gen.fhdl.specials import Instance
from litex.gen.fhdl.module import Module
from litex.gen.genlib.cdc import *
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from litex.gen.genlib.io import *
from migen.fhdl.structure import *
from migen.fhdl.specials import Instance
from migen.fhdl.module import Module
from migen.genlib.cdc import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.io import *
from litex.build import tools

3
litex/build/xilinx/ise.py
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@@ -2,7 +2,8 @@ import os
import subprocess
import sys
from litex.gen.fhdl.structure import _Fragment
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import *
from litex.build import tools
from litex.build.xilinx import common

3
litex/build/xilinx/vivado.py
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@@ -5,7 +5,8 @@ import os
import subprocess
import sys
from litex.gen.fhdl.structure import _Fragment
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import *
from litex.build import tools
from litex.build.xilinx import common

10
litex/gen/__init__.py
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@@ -1,11 +1 @@
from litex.gen.fhdl.structure import *
from litex.gen.fhdl.module import *
from litex.gen.fhdl.specials import *
from litex.gen.fhdl.bitcontainer import *
from litex.gen.fhdl.decorators import *
from litex.gen.fhdl.simplify import *
from litex.gen.sim import *
from litex.gen.genlib.record import *
from litex.gen.genlib.fsm import *

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