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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

Browse Source 
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (180 commits)
  powerpc: clean up ssi.txt, add definition for fsl,ssi-asynchronous
  powerpc/85xx: Add support for the "socrates" board (MPC8544).
  powerpc: Fix bugs introduced by sysfs changes
  powerpc: Sanitize stack pointer in signal handling code
  powerpc: Add write barrier before enabling DTL flags
  powerpc/83xx: Update ranges in gianfar node to match other dts
  powerpc/86xx: Move gianfar mdio nodes under the ethernet nodes
  powerpc/85xx: Move gianfar mdio nodes under the ethernet nodes
  powerpc/83xx: Move gianfar mdio nodes under the ethernet nodes
  powerpc/83xx: Add power management support for MPC837x boards
  powerpc/mm: Introduce early_init_mmu() on 64-bit
  powerpc/mm: Add option for non-atomic PTE updates to ppc64
  powerpc/mm: Fix printk type warning in mmu_context_nohash
  powerpc/mm: Rename arch/powerpc/kernel/mmap.c to mmap_64.c
  powerpc/mm: Merge various PTE bits and accessors definitions
  powerpc/mm: Tweak PTE bit combination definitions
  powerpc/cell: Fix iommu exception reporting
  powerpc/mm: e300c2/c3/c4 TLB errata workaround
  powerpc/mm: Used free register to save a few cycles in SW TLB miss handling
  powerpc/mm: Remove unused register usage in SW TLB miss handling
  ...
This commit is contained in:
Linus Torvalds
2009-03-30 10:23:53 -07:00
parent 25c1a411e8 9ff9a26b78
commit ebc8eca169
284 changed files with 20115 additions and 4646 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
Documentation/powerpc/dts-bindings/fsl/dma.txt
View File

@@ -35,30 +35,30 @@ Example:
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
reg = <82a8 4>;
ranges = <0 8100 1a4>;
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a4>;
interrupt-parent = <&ipic>;
interrupts = <47 8>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
cell-index = <0>;
reg = <0 80>;
reg = <0 0x80>;
};
dma-channel@80 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
cell-index = <1>;
reg = <80 80>;
reg = <0x80 0x80>;
};
dma-channel@100 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
cell-index = <2>;
reg = <100 80>;
reg = <0x100 0x80>;
};
dma-channel@180 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
cell-index = <3>;
reg = <180 80>;
reg = <0x180 0x80>;
};
};
@@ -93,36 +93,36 @@ Example:
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
reg = <21300 4>;
ranges = <0 21100 200>;
reg = <0x21300 4>;
ranges = <0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <0 80>;
reg = <0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <14 2>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <80 80>;
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <15 2>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <100 80>;
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <180 80>;
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <17 2>;
interrupts = <23 2>;
};
};

24
Documentation/powerpc/dts-bindings/fsl/esdhc.txt Normal file
View File

@@ -0,0 +1,24 @@
* Freescale Enhanced Secure Digital Host Controller (eSDHC)
The Enhanced Secure Digital Host Controller provides an interface
for MMC, SD, and SDIO types of memory cards.
Required properties:
- compatible : should be
"fsl,<chip>-esdhc", "fsl,mpc8379-esdhc" for MPC83xx processors.
"fsl,<chip>-esdhc", "fsl,mpc8536-esdhc" for MPC85xx processors.
- reg : should contain eSDHC registers location and length.
- interrupts : should contain eSDHC interrupt.
- interrupt-parent : interrupt source phandle.
- clock-frequency : specifies eSDHC base clock frequency.
Example:
sdhci@2e000 {
compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
reg = <0x2e000 0x1000>;
interrupts = <42 0x8>;
interrupt-parent = <&ipic>;
/* Filled in by U-Boot */
clock-frequency = <0>;
};

68
Documentation/powerpc/dts-bindings/fsl/ssi.txt
View File

@@ -4,44 +4,56 @@ The SSI is a serial device that communicates with audio codecs. It can
be programmed in AC97, I2S, left-justified, or right-justified modes.
Required properties:
- compatible : compatible list, containing "fsl,ssi"
- cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
- reg : offset and length of the register set for the device
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and
level information for the interrupt. This should be
encoded based on the information in section 2)
depending on the type of interrupt controller you
have.
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
- fsl,mode : the operating mode for the SSI interface
"i2s-slave" - I2S mode, SSI is clock slave
"i2s-master" - I2S mode, SSI is clock master
"lj-slave" - left-justified mode, SSI is clock slave
"lj-master" - l.j. mode, SSI is clock master
"rj-slave" - right-justified mode, SSI is clock slave
"rj-master" - r.j., SSI is clock master
"ac97-slave" - AC97 mode, SSI is clock slave
"ac97-master" - AC97 mode, SSI is clock master
- fsl,playback-dma: phandle to a node for the DMA channel to use for
- compatible: Compatible list, contains "fsl,ssi".
- cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
- reg: Offset and length of the register set for the device.
- interrupts: <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and
level information for the interrupt. This should be
encoded based on the information in section 2)
depending on the type of interrupt controller you
have.
- interrupt-parent: The phandle for the interrupt controller that
services interrupts for this device.
- fsl,mode: The operating mode for the SSI interface.
"i2s-slave" - I2S mode, SSI is clock slave
"i2s-master" - I2S mode, SSI is clock master
"lj-slave" - left-justified mode, SSI is clock slave
"lj-master" - l.j. mode, SSI is clock master
"rj-slave" - right-justified mode, SSI is clock slave
"rj-master" - r.j., SSI is clock master
"ac97-slave" - AC97 mode, SSI is clock slave
"ac97-master" - AC97 mode, SSI is clock master
- fsl,playback-dma: Phandle to a node for the DMA channel to use for
playback of audio. This is typically dictated by SOC
design. See the notes below.
- fsl,capture-dma: phandle to a node for the DMA channel to use for
- fsl,capture-dma: Phandle to a node for the DMA channel to use for
capture (recording) of audio. This is typically dictated
by SOC design. See the notes below.
- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
This number is the maximum allowed value for SFCSR[TFWM0].
- fsl,ssi-asynchronous:
If specified, the SSI is to be programmed in asynchronous
mode. In this mode, pins SRCK, STCK, SRFS, and STFS must
all be connected to valid signals. In synchronous mode,
SRCK and SRFS are ignored. Asynchronous mode allows
playback and capture to use different sample sizes and
sample rates. Some drivers may require that SRCK and STCK
be connected together, and SRFS and STFS be connected
together. This would still allow different sample sizes,
but not different sample rates.
Optional properties:
- codec-handle : phandle to a 'codec' node that defines an audio
codec connected to this SSI. This node is typically
a child of an I2C or other control node.
- codec-handle: Phandle to a 'codec' node that defines an audio
codec connected to this SSI. This node is typically
a child of an I2C or other control node.
Child 'codec' node required properties:
- compatible : compatible list, contains the name of the codec
- compatible: Compatible list, contains the name of the codec
Child 'codec' node optional properties:
- clock-frequency : The frequency of the input clock, which typically
comes from an on-board dedicated oscillator.
- clock-frequency: The frequency of the input clock, which typically comes
from an on-board dedicated oscillator.
Notes on fsl,playback-dma and fsl,capture-dma:

74
arch/powerpc/Kconfig
View File

@@ -111,6 +111,7 @@ config PPC
select HAVE_FTRACE_MCOUNT_RECORD
select HAVE_DYNAMIC_FTRACE
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_GRAPH_TRACER
select ARCH_WANT_OPTIONAL_GPIOLIB
select HAVE_IDE
select HAVE_IOREMAP_PROT
@@ -312,7 +313,7 @@ config ARCH_ENABLE_MEMORY_HOTREMOVE
config KEXEC
bool "kexec system call (EXPERIMENTAL)"
depends on (PPC_PRPMC2800 || PPC_MULTIPLATFORM) && EXPERIMENTAL
depends on BOOK3S && EXPERIMENTAL
help
kexec is a system call that implements the ability to shutdown your
current kernel, and to start another kernel. It is like a reboot
@@ -409,6 +410,18 @@ config PPC_HAS_HASH_64K
depends on PPC64
default n
config STDBINUTILS
bool "Using standard binutils settings"
depends on 44x
default y
help
Turning this option off allows you to select 256KB PAGE_SIZE on 44x.
Note, that kernel will be able to run only those applications,
which had been compiled using binutils later than 2.17.50.0.3 with
'-zmax-page-size' set to 256K (the default is 64K). Or, if using
the older binutils, you can patch them with a trivial patch, which
changes the ELF_MAXPAGESIZE definition from 0x10000 to 0x40000.
choice
prompt "Page size"
default PPC_4K_PAGES
@@ -444,6 +457,19 @@ config PPC_64K_PAGES
bool "64k page size" if 44x || PPC_STD_MMU_64
select PPC_HAS_HASH_64K if PPC_STD_MMU_64
config PPC_256K_PAGES
bool "256k page size" if 44x
depends on !STDBINUTILS && (!SHMEM || BROKEN)
help
Make the page size 256k.
As the ELF standard only requires alignment to support page
sizes up to 64k, you will need to compile all of your user
space applications with a non-standard binutils settings
(see the STDBINUTILS description for details).
Say N unless you know what you are doing.
endchoice
config FORCE_MAX_ZONEORDER
@@ -456,6 +482,8 @@ config FORCE_MAX_ZONEORDER
default "9" if PPC_STD_MMU_32 && PPC_16K_PAGES
range 7 64 if PPC_STD_MMU_32 && PPC_64K_PAGES
default "7" if PPC_STD_MMU_32 && PPC_64K_PAGES
range 5 64 if PPC_STD_MMU_32 && PPC_256K_PAGES
default "5" if PPC_STD_MMU_32 && PPC_256K_PAGES
range 11 64
default "11"
help
@@ -594,6 +622,7 @@ config FSL_SOC
config FSL_PCI
bool
select PPC_INDIRECT_PCI
select PCI_QUIRKS
config 4xx_SOC
bool
@@ -730,6 +759,22 @@ config LOWMEM_SIZE
hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL
default "0x30000000"
config LOWMEM_CAM_NUM_BOOL
bool "Set number of CAMs to use to map low memory"
depends on ADVANCED_OPTIONS && FSL_BOOKE
help
This option allows you to set the maximum number of CAM slots that
will be used to map low memory. There are a limited number of slots
available and even more limited number that will fit in the L1 MMU.
However, using more entries will allow mapping more low memory. This
can be useful in optimizing the layout of kernel virtual memory.
Say N here unless you know what you are doing.
config LOWMEM_CAM_NUM
int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL
default 3
config RELOCATABLE
bool "Build a relocatable kernel (EXPERIMENTAL)"
depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE
@@ -794,7 +839,7 @@ config PHYSICAL_START
config PHYSICAL_ALIGN
hex
default "0x10000000" if FSL_BOOKE
default "0x04000000" if FSL_BOOKE
help
This value puts the alignment restrictions on physical address
where kernel is loaded and run from. Kernel is compiled for an
@@ -815,31 +860,6 @@ config TASK_SIZE
default "0x80000000" if PPC_PREP || PPC_8xx
default "0xc0000000"
config CONSISTENT_START_BOOL
bool "Set custom consistent memory pool address"
depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE
help
This option allows you to set the base virtual address
of the consistent memory pool. This pool of virtual
memory is used to make consistent memory allocations.
config CONSISTENT_START
hex "Base virtual address of consistent memory pool" if CONSISTENT_START_BOOL
default "0xfd000000" if (NOT_COHERENT_CACHE && 8xx)
default "0xff100000" if NOT_COHERENT_CACHE
config CONSISTENT_SIZE_BOOL
bool "Set custom consistent memory pool size"
depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE
help
This option allows you to set the size of the
consistent memory pool. This pool of virtual memory
is used to make consistent memory allocations.
config CONSISTENT_SIZE
hex "Size of consistent memory pool" if CONSISTENT_SIZE_BOOL
default "0x00200000" if NOT_COHERENT_CACHE
config PIN_TLB
bool "Pinned Kernel TLBs (860 ONLY)"
depends on ADVANCED_OPTIONS && 8xx

2
arch/powerpc/Kconfig.debug
View File

@@ -129,7 +129,7 @@ config BDI_SWITCH
config BOOTX_TEXT
bool "Support for early boot text console (BootX or OpenFirmware only)"
depends on PPC_OF && PPC_MULTIPLATFORM
depends on PPC_OF && PPC_BOOK3S
help
Say Y here to see progress messages from the boot firmware in text
mode. Requires either BootX or Open Firmware.

4
arch/powerpc/Makefile
View File

@@ -147,8 +147,8 @@ core-y += arch/powerpc/kernel/ \
arch/powerpc/mm/ \
arch/powerpc/lib/ \
arch/powerpc/sysdev/ \
arch/powerpc/platforms/
core-$(CONFIG_MATH_EMULATION) += arch/powerpc/math-emu/
arch/powerpc/platforms/ \
arch/powerpc/math-emu/
core-$(CONFIG_XMON) += arch/powerpc/xmon/
core-$(CONFIG_KVM) += arch/powerpc/kvm/

9
arch/powerpc/boot/Makefile
View File

@@ -70,7 +70,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
cuboot-acadia.c
cuboot-acadia.c cuboot-amigaone.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -235,7 +235,9 @@ image-$(CONFIG_PPC_ADDER875) += cuImage.adder875-uboot \
dtbImage.adder875-redboot
# Board ports in arch/powerpc/platform/52xx/Kconfig
image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 cuImage.lite5200b
image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 lite5200.dtb
image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200b lite5200b.dtb
image-$(CONFIG_PPC_MEDIA5200) += cuImage.media5200 media5200.dtb
# Board ports in arch/powerpc/platform/82xx/Kconfig
image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads
@@ -274,6 +276,9 @@ image-$(CONFIG_STORCENTER) += cuImage.storcenter
image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2
image-$(CONFIG_PPC_C2K) += cuImage.c2k
# Board port in arch/powerpc/platform/amigaone/Kconfig
image-$(CONFIG_AMIGAONE) += cuImage.amigaone
# For 32-bit powermacs, build the COFF and miboot images
# as well as the ELF images.
ifeq ($(CONFIG_PPC32),y)

35
arch/powerpc/boot/cuboot-amigaone.c Normal file
View File

@@ -0,0 +1,35 @@
/*
* Old U-boot compatibility for AmigaOne
*
* Author: Gerhard Pircher (gerhard_pircher@gmx.net)
*
* Based on cuboot-83xx.c
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "stdio.h"
#include "cuboot.h"
#include "ppcboot.h"
static bd_t bd;
static void platform_fixups(void)
{
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
fdt_init(_dtb_start);
serial_console_init();
platform_ops.fixups = platform_fixups;
}

173
arch/powerpc/boot/dts/amigaone.dts Normal file
View File

@@ -0,0 +1,173 @@
/*
* AmigaOne Device Tree Source
*
* Copyright 2008 Gerhard Pircher (gerhard_pircher@gmx.net)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "AmigaOne";
compatible = "eyetech,amigaone";
coherency-off;
#address-cells = <1>;
#size-cells = <1>;
cpus {
#cpus = <1>;
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // 33.3 MHz, from U-boot
clock-frequency = <0>; // From U-boot
bus-frequency = <0>; // From U-boot
};
};
memory {
device_type = "memory";
reg = <0 0>; // From U-boot
};
pci@80000000 {
device_type = "pci";
compatible = "mai-logic,articia-s";
bus-frequency = <33333333>;
bus-range = <0 0xff>;
ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00c00000 // PCI I/O
0x02000000 0 0x80000000 0x80000000 0 0x7d000000 // PCI memory
0x02000000 0 0x00000000 0xfd000000 0 0x01000000>; // PCI alias memory (ISA)
// Configuration address and data register.
reg = <0xfec00cf8 4
0xfee00cfc 4>;
8259-interrupt-acknowledge = <0xfef00000>;
// Do not define a interrupt-parent here, if there is no
// interrupt-map property.
#address-cells = <3>;
#size-cells = <2>;
isa@7 {
device_type = "isa";
compatible = "pciclass,0601";
vendor-id = <0x00001106>;
device-id = <0x00000686>;
revision-id = <0x00000010>;
class-code = <0x00060100>;
subsystem-id = <0>;
subsystem-vendor-id = <0>;
devsel-speed = <0x00000001>;
min-grant = <0>;
max-latency = <0>;
/* First 64k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */
ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00010000>;
interrupt-parent = <&i8259>;
#interrupt-cells = <2>;
#address-cells = <2>;
#size-cells = <1>;
dma-controller@0 {
compatible = "pnpPNP,200";
reg = <1 0x00000000 0x00000020
1 0x00000080 0x00000010
1 0x000000c0 0x00000020>;
};
i8259: interrupt-controller@20 {
device_type = "interrupt-controller";
compatible = "pnpPNP,000";
interrupt-controller;
reg = <1 0x00000020 0x00000002
1 0x000000a0 0x00000002
1 0x000004d0 0x00000002>;
reserved-interrupts = <2>;
#interrupt-cells = <2>;
};
timer@40 {
// Also adds pcspkr to platform devices.
compatible = "pnpPNP,100";
reg = <1 0x00000040 0x00000020>;
};
8042@60 {
device_type = "8042";
reg = <1 0x00000060 0x00000001
1 0x00000064 0x00000001>;
interrupts = <1 3 12 3>;
#address-cells = <1>;
#size-cells = <0>;
keyboard@0 {
compatible = "pnpPNP,303";
reg = <0>;
};
mouse@1 {
compatible = "pnpPNP,f03";
reg = <1>;
};
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 0x00000070 0x00000002>;
interrupts = <8 3>;
};
serial@3f8 {
device_type = "serial";
compatible = "pnpPNP,501","pnpPNP,500";
reg = <1 0x000003f8 0x00000008>;
interrupts = <4 3>;
clock-frequency = <1843200>;
current-speed = <115200>;
};
serial@2f8 {
device_type = "serial";
compatible = "pnpPNP,501","pnpPNP,500";
reg = <1 0x000002f8 0x00000008>;
interrupts = <3 3>;
clock-frequency = <1843200>;
current-speed = <115200>;
};
parallel@378 {
device_type = "parallel";
// No ECP support for now, otherwise add "pnpPNP,401".
compatible = "pnpPNP,400";
reg = <1 0x00000378 0x00000003
1 0x00000778 0x00000003>;
};
fdc@3f0 {
device_type = "fdc";
compatible = "pnpPNP,700";
reg = <1 0x000003f0 0x00000008>;
interrupts = <6 3>;
#address-cells = <1>;
#size-cells = <0>;
disk@0 {
reg = <0>;
};
};
};
};
chosen {
linux,stdout-path = "/pci@80000000/isa@7/serial@3f8";
};
};

82
arch/powerpc/boot/dts/asp834x-redboot.dts
View File

@@ -181,70 +181,76 @@
phy_type = "ulpi";
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x1>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x2>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@25520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x25520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 08 e5 11 32 33 ];
interrupts = <32 0x8 33 0x8 34 0x8>;
interrupt-parent = <&ipic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
linux,network-index = <0>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x1>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x2>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 08 e5 11 32 34 ];
interrupts = <35 0x8 36 0x8 37 0x8>;
interrupt-parent = <&ipic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
linux,network-index = <1>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {

28
arch/powerpc/boot/dts/canyonlands.dts
View File

@@ -149,6 +149,20 @@
/*RXDE*/ 0x5 0x4>;
};
USB0: ehci@bffd0400 {
compatible = "ibm,usb-ehci-460ex", "usb-ehci";
interrupt-parent = <&UIC2>;
interrupts = <0x1d 4>;
reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
};
USB1: usb@bffd0000 {
compatible = "ohci-le";
reg = <4 0xbffd0000 0x60>;
interrupt-parent = <&UIC2>;
interrupts = <0x1e 4>;
};
POB0: opb {
compatible = "ibm,opb-460ex", "ibm,opb";
#address-cells = <1>;
@@ -252,6 +266,20 @@
reg = <0xef600700 0x00000014>;
interrupt-parent = <&UIC0>;
interrupts = <0x2 0x4>;
#address-cells = <1>;
#size-cells = <0>;
rtc@68 {
compatible = "stm,m41t80";
reg = <0x68>;
interrupt-parent = <&UIC2>;
interrupts = <0x19 0x8>;
};
sttm@48 {
compatible = "ad,ad7414";
reg = <0x48>;
interrupt-parent = <&UIC1>;
interrupts = <0x14 0x8>;
};
};
IIC1: i2c@ef600800 {

49
arch/powerpc/boot/dts/cm5200.dts
View File

@@ -17,6 +17,7 @@
compatible = "schindler,cm5200";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus {
#address-cells = <1>;
@@ -66,7 +67,6 @@
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x600 0x10>;
interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt;
};
@@ -74,84 +74,76 @@
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x610 0x10>;
interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x620 0x10>;
interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x630 0x10>;
interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x640 0x10>;
interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x650 0x10>;
interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x660 0x10>;
interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x670 0x10>;
interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
};
rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio@b00 {
gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
gpio-controller;
#gpio-cells = <2>;
};
gpio@c00 {
gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
gpio-controller;
#gpio-cells = <2>;
};
spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
dma-controller@1200 {
@@ -161,7 +153,6 @@
3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
xlb@1f00 {
@@ -170,48 +161,34 @@
};
serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
reg = <0x2000 0x100>;
interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
};
serial@2200 { // PSC2
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart";
port-number = <1>; // Logical port assignment
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2200 0x100>;
interrupts = <2 2 0>;
interrupt-parent = <&mpc5200_pic>;
};
serial@2400 { // PSC3
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart";
port-number = <2>; // Logical port assignment
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2400 0x100>;
interrupts = <2 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
serial@2c00 { // PSC6
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <5>; // Logical port assignment
reg = <0x2c00 0x100>;
interrupts = <2 4 0>;
interrupt-parent = <&mpc5200_pic>;
};
ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>;
};
@@ -221,10 +198,8 @@
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@0 {
device_type = "ethernet-phy";
reg = <0>;
};
};
@@ -235,7 +210,6 @@
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
@@ -245,9 +219,8 @@
};
};
lpb {
model = "fsl,lpb";
compatible = "fsl,lpb";
localbus {
compatible = "fsl,mpc5200b-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xfc000000 0x2000000>;

254
arch/powerpc/boot/dts/digsy_mtc.dts Normal file
View File

@@ -0,0 +1,254 @@
/*
* Digsy MTC board Device Tree Source
*
* Copyright (C) 2009 Semihalf
*
* Based on the CM5200 by M. Balakowicz
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "intercontrol,digsy-mtc";
compatible = "intercontrol,digsy-mtc";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,5200@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <0x4000>; // L1, 16K
i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x02000000>; // 32MB
};
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc5200b-immr";
ranges = <0 0xf0000000 0x0000c000>;
reg = <0xf0000000 0x00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
reg = <0x200 0x38>;
};
mpc5200_pic: interrupt-controller@500 {
// 5200 interrupts are encoded into two levels;
interrupt-controller;
#interrupt-cells = <3>;
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x600 0x10>;
interrupts = <1 9 0>;
fsl,has-wdt;
};
timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x610 0x10>;
interrupts = <1 10 0>;
};
timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x620 0x10>;
interrupts = <1 11 0>;
};
timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x630 0x10>;
interrupts = <1 12 0>;
};
timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x640 0x10>;
interrupts = <1 13 0>;
};
timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x650 0x10>;
interrupts = <1 14 0>;
};
timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x660 0x10>;
interrupts = <1 15 0>;
};
timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x670 0x10>;
interrupts = <1 16 0>;
};
gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>;
interrupts = <1 7 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
gpio-controller;
#gpio-cells = <2>;
};
spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
};
usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>;
interrupts = <2 6 0>;
};
dma-controller@1200 {
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>;
};
xlb@1f00 {
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
reg = <0x1f00 0x100>;
};
serial@2600 { // PSC4
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2600 0x100>;
interrupts = <2 11 0>;
};
serial@2800 { // PSC5
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2800 0x100>;
interrupts = <2 12 0>;
};
ethernet@3000 {
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
phy-handle = <&phy0>;
};
mdio@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ata@3a00 {
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
};
i2c@3d00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
fsl5200-clocking;
rtc@50 {
compatible = "at,24c08";
reg = <0x50>;
};
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
reg = <0x8000 0x4000>;
};
};
lpb {
compatible = "fsl,mpc5200b-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xff000000 0x1000000>;
// 16-bit flash device at LocalPlus Bus CS0
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x1000000>;
bank-width = <2>;
device-width = <2>;
#size-cells = <1>;
#address-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x00200000>;
};
partition@200000 {
label = "root";
reg = <0x00200000 0x00300000>;
};
partition@500000 {
label = "user";
reg = <0x00500000 0x00a00000>;
};
partition@f00000 {
label = "u-boot";
reg = <0x00f00000 0x100000>;
};
};
};
};

367
arch/powerpc/boot/dts/gef_ppc9a.dts Normal file
View File

@@ -0,0 +1,367 @@
/*
* GE Fanuc PPC9A Device Tree Source
*
* Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Based on: SBS CM6 Device Tree Source
* Copyright 2007 SBS Technologies GmbH & Co. KG
* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
* Copyright 2006 Freescale Semiconductor Inc.
*/
/*
* Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
*/
/dts-v1/;
/ {
model = "GEF_PPC9A";
compatible = "gef,ppc9a";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>; // set by uboot
};
localbus@fef05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
reg = <0xfef05000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
1 0 0xe8000000 0x08000000 // Paged Flash 0
2 0 0xe0000000 0x08000000 // Paged Flash 1
3 0 0xfc100000 0x00020000 // NVRAM
4 0 0xfc000000 0x00008000 // FPGA
5 0 0xfc008000 0x00008000 // AFIX FPGA
6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
/* flash@0,0 is a mirror of part of the memory in flash@1,0
flash@0,0 {
compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
reg = <0x0 0x0 0x1000000>;
bank-width = <4>;
device-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "firmware";
reg = <0x0 0x1000000>;
read-only;
};
};
*/
flash@1,0 {
compatible = "gef,ppc9a-paged-flash", "cfi-flash";
reg = <0x1 0x0 0x8000000>;
bank-width = <4>;
device-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "user";
reg = <0x0 0x7800000>;
};
partition@7800000 {
label = "firmware";
reg = <0x7800000 0x800000>;
read-only;
};
};
fpga@4,0 {
compatible = "gef,ppc9a-fpga-regs";
reg = <0x4 0x0 0x40>;
};
wdt@4,2000 {
compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
"gef,fpga-wdt";
reg = <0x4 0x2000 0x8>;
interrupts = <0x1a 0x4>;
interrupt-parent = <&gef_pic>;
};
/* Second watchdog available, driver currently supports one.
wdt@4,2010 {
compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
"gef,fpga-wdt";
reg = <0x4 0x2010 0x8>;
interrupts = <0x1b 0x4>;
interrupt-parent = <&gef_pic>;
};
*/
gef_pic: pic@4,4000 {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
reg = <0x4 0x4000 0x20>;
interrupts = <0x8
0x9>;
interrupt-parent = <&mpic>;
};
gef_gpio: gpio@7,14000 {
#gpio-cells = <2>;
compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
reg = <0x7 0x14000 0x24>;
gpio-controller;
};
};
soc@fef00000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
compatible = "fsl,mpc8641-soc", "simple-bus";
ranges = <0x0 0xfef00000 0x00100000>;
reg = <0xfef00000 0x100000>; // CCSRBAR 1M
bus-frequency = <33333333>;
i2c1: i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
hwmon@48 {
compatible = "national,lm92";
reg = <0x48>;
};
hwmon@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
rtc@51 {
compatible = "epson,rx8581";
reg = <0x00000051>;
};
eti@6b {
compatible = "dallas,ds1682";
reg = <0x6b>;
};
};
i2c2: i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "gmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>;
interrupts = <0x8 0x4>;
reg = <3>;
};
};
};
enet1: ethernet@26000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy2>;
phy-connection-type = "gmii";
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <0x2a 0x2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <0x1c 0x2>;
interrupt-parent = <&mpic>;
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};
pci0: pcie@fef08000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xfef08000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <0x18 0x2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000
0x0 0x40000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00400000>;
};
};
};

367
arch/powerpc/boot/dts/gef_sbc310.dts Normal file
View File

@@ -0,0 +1,367 @@
/*
* GE Fanuc SBC310 Device Tree Source
*
* Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Based on: SBS CM6 Device Tree Source
* Copyright 2007 SBS Technologies GmbH & Co. KG
* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
* Copyright 2006 Freescale Semiconductor Inc.
*/
/*
* Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
*/
/dts-v1/;
/ {
model = "GEF_SBC310";
compatible = "gef,sbc310";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>; // set by uboot
};
localbus@fef05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
reg = <0xfef05000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
1 0 0xe0000000 0x08000000 // Paged Flash 0
2 0 0xe8000000 0x08000000 // Paged Flash 1
3 0 0xfc100000 0x00020000 // NVRAM
4 0 0xfc000000 0x00010000>; // FPGA
/* flash@0,0 is a mirror of part of the memory in flash@1,0
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x01000000>;
bank-width = <2>;
device-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "firmware";
reg = <0x00000000 0x01000000>;
read-only;
};
};
*/
flash@1,0 {
compatible = "cfi-flash";
reg = <1 0 0x8000000>;
bank-width = <2>;
device-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "user";
reg = <0x00000000 0x07800000>;
};
partition@7800000 {
label = "firmware";
reg = <0x07800000 0x00800000>;
read-only;
};
};
fpga@4,0 {
compatible = "gef,fpga-regs";
reg = <0x4 0x0 0x40>;
};
wdt@4,2000 {
#interrupt-cells = <2>;
device_type = "watchdog";
compatible = "gef,fpga-wdt";
reg = <0x4 0x2000 0x8>;
interrupts = <0x1a 0x4>;
interrupt-parent = <&gef_pic>;
};
/*
wdt@4,2010 {
#interrupt-cells = <2>;
device_type = "watchdog";
compatible = "gef,fpga-wdt";
reg = <0x4 0x2010 0x8>;
interrupts = <0x1b 0x4>;
interrupt-parent = <&gef_pic>;
};
*/
gef_pic: pic@4,4000 {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "gef,fpga-pic";
reg = <0x4 0x4000 0x20>;
interrupts = <0x8
0x9>;
interrupt-parent = <&mpic>;
};
gef_gpio: gpio@4,8000 {
#gpio-cells = <2>;
compatible = "gef,sbc310-gpio";
reg = <0x4 0x8000 0x24>;
gpio-controller;
};
};
soc@fef00000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xfef00000 0x00100000>;
reg = <0xfef00000 0x100000>; // CCSRBAR 1M
bus-frequency = <33333333>;
i2c1: i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
rtc@51 {
compatible = "epson,rx8581";
reg = <0x00000051>;
};
};
i2c2: i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
hwmon@48 {
compatible = "national,lm92";
reg = <0x48>;
};
hwmon@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
eti@6b {
compatible = "dallas,ds1682";
reg = <0x6b>;
};
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "gmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>;
interrupts = <0x8 0x4>;
reg = <3>;
};
};
};
enet1: ethernet@26000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy2>;
phy-connection-type = "gmii";
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <0x2a 0x2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <0x1c 0x2>;
interrupt-parent = <&mpic>;
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};
pci0: pcie@fef08000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xfef08000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <0x18 0x2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000
0x0 0x40000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00400000>;
};
};
};

41
arch/powerpc/boot/dts/gef_sbc610.dts
View File

@@ -71,7 +71,7 @@
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
reg = <0xf8005000 0x1000>;
reg = <0xfef05000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
@@ -202,34 +202,37 @@
};
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>;
interrupts = <0x8 0x4>;
reg = <3>;
};
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "gmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>;
interrupts = <0x8 0x4>;
reg = <3>;
};
};
};
enet1: ethernet@26000 {

79
arch/powerpc/boot/dts/ksi8560.dts
View File

@@ -124,67 +124,72 @@
};
};
mdio@24520 { /* For TSECs */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
PHY1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
reg = <0x1>;
device_type = "ethernet-phy";
};
PHY2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
reg = <0x2>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@25520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x25520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
/* Mac address filled in by bootwrapper */
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&PHY1>;
mdio@520 { /* For TSECs */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
PHY1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
reg = <0x1>;
device_type = "ethernet-phy";
};
PHY2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
reg = <0x2>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
/* Mac address filled in by bootwrapper */
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&PHY2>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
mpic: pic@40000 {

52
arch/powerpc/boot/dts/lite5200.dts
View File

@@ -17,6 +17,7 @@
compatible = "fsl,lite5200";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus {
#address-cells = <1>;
@@ -58,96 +59,74 @@
// 5200 interrupts are encoded into two levels;
interrupt-controller;
#interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "fsl,mpc5200-pic";
reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <0>;
reg = <0x600 0x10>;
interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt;
};
timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <1>;
reg = <0x610 0x10>;
interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <2>;
reg = <0x620 0x10>;
interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <3>;
reg = <0x630 0x10>;
interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <4>;
reg = <0x640 0x10>;
interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <5>;
reg = <0x650 0x10>;
interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <6>;
reg = <0x660 0x10>;
interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <7>;
reg = <0x670 0x10>;
interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
};
rtc@800 { // Real time clock
compatible = "fsl,mpc5200-rtc";
reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
can@900 {
compatible = "fsl,mpc5200-mscan";
cell-index = <0>;
interrupts = <2 17 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x900 0x80>;
};
can@980 {
compatible = "fsl,mpc5200-mscan";
cell-index = <1>;
interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x980 0x80>;
};
@@ -155,39 +134,33 @@
compatible = "fsl,mpc5200-gpio";
reg = <0xb00 0x40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio@c00 {
compatible = "fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
spi@f00 {
compatible = "fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
compatible = "fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
dma-controller@1200 {
device_type = "dma-controller";
compatible = "fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
xlb@1f00 {
@@ -196,13 +169,10 @@
};
serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
cell-index = <0>;
reg = <0x2000 0x100>;
interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
};
// PSC2 in ac97 mode example
@@ -211,7 +181,6 @@
// cell-index = <1>;
// reg = <0x2200 0x100>;
// interrupts = <2 2 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC3 in CODEC mode example
@@ -220,27 +189,22 @@
// cell-index = <2>;
// reg = <0x2400 0x100>;
// interrupts = <2 3 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC4 in uart mode example
//serial@2600 { // PSC4
// device_type = "serial";
// compatible = "fsl,mpc5200-psc-uart";
// cell-index = <3>;
// reg = <0x2600 0x100>;
// interrupts = <2 11 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC5 in uart mode example
//serial@2800 { // PSC5
// device_type = "serial";
// compatible = "fsl,mpc5200-psc-uart";
// cell-index = <4>;
// reg = <0x2800 0x100>;
// interrupts = <2 12 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC6 in spi mode example
@@ -249,16 +213,13 @@
// cell-index = <5>;
// reg = <0x2c00 0x100>;
// interrupts = <2 4 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200-fec";
reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>;
};
@@ -268,30 +229,24 @@
compatible = "fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@1 {
device_type = "ethernet-phy";
reg = <1>;
};
};
ata@3a00 {
device_type = "ata";
compatible = "fsl,mpc5200-ata";
reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
i2c@3d00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
@@ -299,14 +254,12 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
sram@8000 {
compatible = "fsl,mpc5200-sram","sram";
compatible = "fsl,mpc5200-sram";
reg = <0x8000 0x4000>;
};
};
@@ -325,7 +278,6 @@
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000

63
arch/powerpc/boot/dts/lite5200b.dts
View File

@@ -17,6 +17,7 @@
compatible = "fsl,lite5200b";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus {
#address-cells = <1>;
@@ -58,136 +59,112 @@
// 5200 interrupts are encoded into two levels;
interrupt-controller;
#interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <0>;
reg = <0x600 0x10>;
interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt;
};
timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <1>;
reg = <0x610 0x10>;
interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <2>;
reg = <0x620 0x10>;
interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <3>;
reg = <0x630 0x10>;
interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <4>;
reg = <0x640 0x10>;
interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <5>;
reg = <0x650 0x10>;
interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <6>;
reg = <0x660 0x10>;
interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <7>;
reg = <0x670 0x10>;
interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
};
rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
can@900 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
cell-index = <0>;
interrupts = <2 17 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x900 0x80>;
};
can@980 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
cell-index = <1>;
interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x980 0x80>;
};
gpio@b00 {
gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
gpio-controller;
#gpio-cells = <2>;
};
gpio@c00 {
gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
gpio-controller;
#gpio-cells = <2>;
};
spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
dma-controller@1200 {
device_type = "dma-controller";
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
xlb@1f00 {
@@ -196,13 +173,10 @@
};
serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
cell-index = <0>;
reg = <0x2000 0x100>;
interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
};
// PSC2 in ac97 mode example
@@ -211,7 +185,6 @@
// cell-index = <1>;
// reg = <0x2200 0x100>;
// interrupts = <2 2 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC3 in CODEC mode example
@@ -220,27 +193,22 @@
// cell-index = <2>;
// reg = <0x2400 0x100>;
// interrupts = <2 3 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC4 in uart mode example
//serial@2600 { // PSC4
// device_type = "serial";
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
// cell-index = <3>;
// reg = <0x2600 0x100>;
// interrupts = <2 11 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC5 in uart mode example
//serial@2800 { // PSC5
// device_type = "serial";
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
// cell-index = <4>;
// reg = <0x2800 0x100>;
// interrupts = <2 12 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC6 in spi mode example
@@ -249,49 +217,40 @@
// cell-index = <5>;
// reg = <0x2c00 0x100>;
// interrupts = <2 4 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>;
};
mdio@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@0 {
device_type = "ethernet-phy";
reg = <0>;
};
};
ata@3a00 {
device_type = "ata";
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
i2c@3d00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
@@ -299,14 +258,13 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
reg = <0x8000 0x4000>;
};
};
@@ -330,7 +288,6 @@
0xc800 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000

318
arch/powerpc/boot/dts/media5200.dts Normal file
View File

@@ -0,0 +1,318 @@
/*
* Freescale Media5200 board Device Tree Source
*
* Copyright 2009 Secret Lab Technologies Ltd.
* Grant Likely <grant.likely@secretlab.ca>
* Steven Cavanagh <scavanagh@secretlab.ca>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "fsl,media5200";
compatible = "fsl,media5200";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
aliases {
console = &console;
ethernet0 = &eth0;
};
chosen {
linux,stdout-path = &console;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,5200@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <0x4000>; // L1, 16K
i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
bus-frequency = <132000000>; // 132 MHz
clock-frequency = <396000000>; // 396 MHz
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>; // 128MB RAM
};
soc@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc5200b-immr";
ranges = <0 0xf0000000 0x0000c000>;
reg = <0xf0000000 0x00000100>;
bus-frequency = <132000000>;// 132 MHz
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
reg = <0x200 0x38>;
};
mpc5200_pic: interrupt-controller@500 {
// 5200 interrupts are encoded into two levels;
interrupt-controller;
#interrupt-cells = <3>;
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x600 0x10>;
interrupts = <1 9 0>;
fsl,has-wdt;
};
timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x610 0x10>;
interrupts = <1 10 0>;
};
timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x620 0x10>;
interrupts = <1 11 0>;
};
timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x630 0x10>;
interrupts = <1 12 0>;
};
timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x640 0x10>;
interrupts = <1 13 0>;
};
timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x650 0x10>;
interrupts = <1 14 0>;
};
timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x660 0x10>;
interrupts = <1 15 0>;
};
timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x670 0x10>;
interrupts = <1 16 0>;
};
rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>;
};
can@900 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
interrupts = <2 17 0>;
reg = <0x900 0x80>;
};
can@980 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
interrupts = <2 18 0>;
reg = <0x980 0x80>;
};
gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>;
interrupts = <1 7 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
gpio-controller;
#gpio-cells = <2>;
};
spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
};
usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0x100>;
interrupts = <2 6 0>;
};
dma-controller@1200 {
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>;
};
xlb@1f00 {
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
reg = <0x1f00 0x100>;
};
// PSC6 in uart mode
console: serial@2c00 { // PSC6
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
cell-index = <5>;
port-number = <0>; // Logical port assignment
reg = <0x2c00 0x100>;
interrupts = <2 4 0>;
};
eth0: ethernet@3000 {
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
phy-handle = <&phy0>;
};
mdio@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ata@3a00 {
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
};
i2c@3d00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
fsl5200-clocking;
};
i2c@3d40 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
fsl5200-clocking;
};
sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
reg = <0x8000 0x4000>;
};
};
pci@f0000d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
reg = <0xf0000d00 0x100>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
0xc000 0 0 2 &media5200_fpga 0 3
0xc000 0 0 3 &media5200_fpga 0 4
0xc000 0 0 4 &media5200_fpga 0 5
0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
0xc800 0 0 2 &media5200_fpga 0 4
0xc800 0 0 3 &media5200_fpga 0 5
0xc800 0 0 4 &media5200_fpga 0 2
0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
0xd000 0 0 2 &media5200_fpga 0 5
0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
};
localbus {
compatible = "fsl,mpc5200b-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = < 0 0 0xfc000000 0x02000000
1 0 0xfe000000 0x02000000
2 0 0xf0010000 0x00010000
3 0 0xf0020000 0x00010000 >;
flash@0,0 {
compatible = "amd,am29lv28ml", "cfi-flash";
reg = <0 0x0 0x2000000>; // 32 MB
bank-width = <4>; // Width in bytes of the flash bank
device-width = <2>; // Two devices on each bank
};
flash@1,0 {
compatible = "amd,am29lv28ml", "cfi-flash";
reg = <1 0 0x2000000>; // 32 MB
bank-width = <4>; // Width in bytes of the flash bank
device-width = <2>; // Two devices on each bank
};
media5200_fpga: fpga@2,0 {
compatible = "fsl,media5200-fpga";
interrupt-controller;
#interrupt-cells = <2>; // 0:bank 1:id; no type field
reg = <2 0 0x10000>;
interrupt-parent = <&mpc5200_pic>;
interrupts = <0 0 3 // IRQ bank 0
1 1 3>; // IRQ bank 1
};
uart@3,0 {
compatible = "ti,tl16c752bpt";
reg = <3 0 0x10000>;
interrupt-parent = <&media5200_fpga>;
interrupts = <0 0 0 1>; // 2 irqs
};
};
};

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