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Merge tag 'soc-drivers-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Browse Source 
Pull ARM SoC driver updates from Arnd Bergmann:
 "Nothing surprising in the SoC specific drivers, with the usual
  updates:

   - Added or improved SoC driver support for Tegra234, Exynos4121,
     RK3588, as well as multiple Mediatek and Qualcomm chips

   - SCMI firmware gains support for multiple SMC/HVC transport and
     version 3.2 of the protocol

   - Cleanups amd minor changes for the reset controller, memory
     controller, firmware and sram drivers

   - Minor changes to amd/xilinx, samsung, tegra, nxp, ti, qualcomm,
     amlogic and renesas SoC specific drivers"

* tag 'soc-drivers-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (118 commits)
  dt-bindings: interrupt-controller: Convert Amlogic Meson GPIO interrupt controller binding
  MAINTAINERS: add PHY-related files to Amlogic SoC file list
  drivers: meson: secure-pwrc: always enable DMA domain
  tee: optee: Use kmemdup() to replace kmalloc + memcpy
  soc: qcom: geni-se: Do not bother about enable/disable of interrupts in secondary sequencer
  dt-bindings: sram: qcom,imem: document qdu1000
  soc: qcom: icc-bwmon: Fix MSM8998 count unit
  dt-bindings: soc: qcom,rpmh-rsc: Require power-domains
  soc: qcom: socinfo: Add Soc ID for IPQ5300
  dt-bindings: arm: qcom,ids: add SoC ID for IPQ5300
  soc: qcom: Fix a IS_ERR() vs NULL bug in probe
  soc: qcom: socinfo: Add support for new fields in revision 19
  soc: qcom: socinfo: Add support for new fields in revision 18
  dt-bindings: firmware: scm: Add compatible for SDX75
  soc: qcom: mdt_loader: Fix split image detection
  dt-bindings: memory-controllers: drop unneeded quotes
  soc: rockchip: dtpm: use C99 array init syntax
  firmware: tegra: bpmp: Add support for DRAM MRQ GSCs
  soc/tegra: pmc: Use devm_clk_notifier_register()
  soc/tegra: pmc: Simplify debugfs initialization
  ...
This commit is contained in:
Linus Torvalds
2023-06-29 15:22:19 -07:00
parent a9025a5f16 356fa49759
commit e4c8d01865
116 changed files with 3087 additions and 945 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/firmware/arm,scmi.yaml
View File

@@ -34,6 +34,10 @@ properties:
- description: SCMI compliant firmware with ARM SMC/HVC transport
items:
- const: arm,scmi-smc
- description: SCMI compliant firmware with ARM SMC/HVC transport
with shmem address(4KB-page, offset) as parameters
items:
- const: arm,scmi-smc-param
- description: SCMI compliant firmware with SCMI Virtio transport.
The virtio transport only supports a single device.
items:
@@ -299,7 +303,9 @@ else:
properties:
compatible:
contains:
const: arm,scmi-smc
enum:
- arm,scmi-smc
- arm,scmi-smc-param
then:
required:
- arm,smc-id

1
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
View File

@@ -51,6 +51,7 @@ properties:
- qcom,scm-sdm845
- qcom,scm-sdx55
- qcom,scm-sdx65
- qcom,scm-sdx75
- qcom,scm-sm6115
- qcom,scm-sm6125
- qcom,scm-sm6350

38
Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
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@@ -1,38 +0,0 @@
Amlogic meson GPIO interrupt controller
Meson SoCs contains an interrupt controller which is able to watch the SoC
pads and generate an interrupt on edge or level. The controller is essentially
a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
or level and polarity. It does not expose all 256 mux inputs because the
documentation shows that the upper part is not mapped to any pad. The actual
number of interrupt exposed depends on the SoC.
Required properties:
- compatible : must have "amlogic,meson8-gpio-intc" and either
"amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or
"amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
"amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
"amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
"amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
"amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
"amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
"amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value must be 2.
- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These
are the hwirqs used on the parent interrupt controller.
Example:
gpio_interrupt: interrupt-controller@9880 {
compatible = "amlogic,meson-gxbb-gpio-intc",
"amlogic,meson-gpio-intc";
reg = <0x0 0x9880 0x0 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
meson,channel-interrupts = <64 65 66 67 68 69 70 71>;
};

72
Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml Normal file
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@@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/amlogic,meson-gpio-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson GPIO interrupt controller
maintainers:
- Heiner Kallweit <hkallweit1@gmail.com>
description: |
Meson SoCs contains an interrupt controller which is able to watch the SoC
pads and generate an interrupt on edge or level. The controller is essentially
a 256 pads to 8 or 12 GIC interrupt multiplexer, with a filter block to select
edge or level and polarity. It does not expose all 256 mux inputs because the
documentation shows that the upper part is not mapped to any pad. The actual
number of interrupts exposed depends on the SoC.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
oneOf:
- const: amlogic,meson-gpio-intc
- items:
- enum:
- amlogic,meson8-gpio-intc
- amlogic,meson8b-gpio-intc
- amlogic,meson-gxbb-gpio-intc
- amlogic,meson-gxl-gpio-intc
- amlogic,meson-axg-gpio-intc
- amlogic,meson-g12a-gpio-intc
- amlogic,meson-sm1-gpio-intc
- amlogic,meson-a1-gpio-intc
- amlogic,meson-s4-gpio-intc
- const: amlogic,meson-gpio-intc
reg:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 2
amlogic,channel-interrupts:
description: Array with the upstream hwirq numbers
minItems: 8
maxItems: 12
$ref: /schemas/types.yaml#/definitions/uint32-array
required:
- compatible
- reg
- interrupt-controller
- "#interrupt-cells"
- amlogic,channel-interrupts
additionalProperties: false
examples:
- |
interrupt-controller@9880 {
compatible = "amlogic,meson-gxbb-gpio-intc",
"amlogic,meson-gpio-intc";
reg = <0x9880 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
};

78
Documentation/devicetree/bindings/media/s5p-mfc.txt
View File

@@ -1,78 +0,0 @@
* Samsung Multi Format Codec (MFC)
Multi Format Codec (MFC) is the IP present in Samsung SoCs which
supports high resolution decoding and encoding functionalities.
The MFC device driver is a v4l2 driver which can encode/decode
video raw/elementary streams and has support for all popular
video codecs.
Required properties:
- compatible : value should be either one among the following
(a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
(b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
(c) "samsung,exynos3250-mfc", "samsung,mfc-v7" for MFC v7
present in Exynos3250 SoC
(d) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
(e) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
(f) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
(g) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
- reg : Physical base address of the IP registers and length of memory
mapped region.
- interrupts : MFC interrupt number to the CPU.
- clocks : from common clock binding: handle to mfc clock.
- clock-names : from common clock binding: must contain "mfc",
corresponding to entry in the clocks property.
Optional properties:
- power-domains : power-domain property defined with a phandle
to respective power domain.
- memory-region : from reserved memory binding: phandles to two reserved
memory regions, first is for "left" mfc memory bus interfaces,
second if for the "right" mfc memory bus, used when no SYSMMU
support is available; used only by MFC v5 present in Exynos4 SoCs
Obsolete properties:
- samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region
property instead
Example:
SoC specific DT entry:
mfc: codec@13400000 {
compatible = "samsung,mfc-v5";
reg = <0x13400000 0x10000>;
interrupts = <0 94 0>;
power-domains = <&pd_mfc>;
clocks = <&clock 273>;
clock-names = "mfc";
};
Reserved memory specific DT entry for given board (see reserved memory binding
for more information):
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
mfc_left: region@51000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x51000000 0x800000>;
};
mfc_right: region@43000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x43000000 0x800000>;
};
};
Board specific DT entry:
codec@13400000 {
memory-region = <&mfc_left>, <&mfc_right>;
};

184
Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml Normal file
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@@ -0,0 +1,184 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/samsung,s5p-mfc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos Multi Format Codec (MFC)
maintainers:
- Marek Szyprowski <m.szyprowski@samsung.com>
- Aakarsh Jain <aakarsh.jain@samsung.com>
description:
Multi Format Codec (MFC) is the IP present in Samsung SoCs which
supports high resolution decoding and encoding functionalities.
properties:
compatible:
oneOf:
- enum:
- samsung,exynos5433-mfc # Exynos5433
- samsung,mfc-v5 # Exynos4
- samsung,mfc-v6 # Exynos5
- samsung,mfc-v7 # Exynos5420
- samsung,mfc-v8 # Exynos5800
- samsung,mfc-v10 # Exynos7880
- items:
- enum:
- samsung,exynos3250-mfc # Exynos3250
- const: samsung,mfc-v7 # Fall back for Exynos3250
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
maxItems: 3
interrupts:
maxItems: 1
iommus:
minItems: 1
maxItems: 2
iommu-names:
minItems: 1
maxItems: 2
power-domains:
maxItems: 1
memory-region:
minItems: 1
maxItems: 2
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos3250-mfc
then:
properties:
clocks:
maxItems: 2
clock-names:
items:
- const: mfc
- const: sclk_mfc
iommus:
maxItems: 1
iommus-names: false
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos5433-mfc
then:
properties:
clocks:
maxItems: 3
clock-names:
items:
- const: pclk
- const: aclk
- const: aclk_xiu
iommus:
maxItems: 2
iommus-names:
items:
- const: left
- const: right
- if:
properties:
compatible:
contains:
enum:
- samsung,mfc-v5
then:
properties:
clocks:
maxItems: 2
clock-names:
items:
- const: mfc
- const: sclk_mfc
iommus:
maxItems: 2
iommus-names:
items:
- const: left
- const: right
- if:
properties:
compatible:
contains:
enum:
- samsung,mfc-v6
- samsung,mfc-v8
then:
properties:
clocks:
maxItems: 1
clock-names:
items:
- const: mfc
iommus:
maxItems: 2
iommus-names:
items:
- const: left
- const: right
- if:
properties:
compatible:
contains:
enum:
- samsung,mfc-v7
then:
properties:
clocks:
minItems: 1
maxItems: 2
iommus:
minItems: 1
maxItems: 2
examples:
- |
#include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
codec@13400000 {
compatible = "samsung,mfc-v5";
reg = <0x13400000 0x10000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_mfc>;
clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
clock-names = "mfc", "sclk_mfc";
iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
iommu-names = "left", "right";
};

2
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
View File

@@ -165,7 +165,7 @@ patternProperties:
const: 0
lpddr2:
$ref: "ddr/jedec,lpddr2.yaml#"
$ref: ddr/jedec,lpddr2.yaml#
type: object
patternProperties:

2
Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml
View File

@@ -129,7 +129,7 @@ patternProperties:
The child device node represents the device connected to the GPMC
bus. The device can be a NAND chip, SRAM device, NOR device
or an ASIC.
$ref: "ti,gpmc-child.yaml"
$ref: ti,gpmc-child.yaml
required:

4
Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
View File

@@ -24,6 +24,10 @@ properties:
- enum:
- mediatek,mt7623-mipi-tx
- const: mediatek,mt2701-mipi-tx
- items:
- enum:
- mediatek,mt6795-mipi-tx
- const: mediatek,mt8173-mipi-tx
- items:
- enum:
- mediatek,mt8365-mipi-tx

4
Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
View File

@@ -22,7 +22,9 @@ properties:
- mediatek,mt8173-disp-pwm
- mediatek,mt8183-disp-pwm
- items:
- const: mediatek,mt8167-disp-pwm
- enum:
- mediatek,mt6795-disp-pwm
- mediatek,mt8167-disp-pwm
- const: mediatek,mt8173-disp-pwm
- items:
- enum:

32
Documentation/devicetree/bindings/reset/oxnas,reset.txt
View File

@@ -1,32 +0,0 @@
Oxford Semiconductor OXNAS SoC Family RESET Controller
================================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: For OX810SE, should be "oxsemi,ox810se-reset"
For OX820, should be "oxsemi,ox820-reset"
- #reset-cells: 1, see below
Parent node should have the following properties :
- compatible: For OX810SE, should be :
"oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
For OX820, should be :
"oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"
Reset indices are in dt-bindings include files :
- For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h
- For OX820: include/dt-bindings/reset/oxsemi,ox820.h
example:
sys: sys-ctrl@000000 {
compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
reg = <0x000000 0x100000>;
reset: reset-controller {
compatible = "oxsemi,ox810se-reset";
#reset-cells = <1>;
};
};

1
Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
View File

@@ -33,6 +33,7 @@ properties:
- mediatek,mt2701-pwrap
- mediatek,mt6765-pwrap
- mediatek,mt6779-pwrap
- mediatek,mt6795-pwrap
- mediatek,mt6797-pwrap
- mediatek,mt6873-pwrap
- mediatek,mt7622-pwrap

1
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
View File

@@ -26,6 +26,7 @@ properties:
items:
- enum:
- qcom,qdu1000-aoss-qmp
- qcom,sa8775p-aoss-qmp
- qcom,sc7180-aoss-qmp
- qcom,sc7280-aoss-qmp
- qcom,sc8180x-aoss-qmp

4
Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml
View File

@@ -55,9 +55,10 @@ additionalProperties: false
examples:
- |
eud@88e0000 {
compatible = "qcom,sc7280-eud","qcom,eud";
compatible = "qcom,sc7280-eud", "qcom,eud";
reg = <0x88e0000 0x2000>,
<0x88e2000 0x1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -67,6 +68,7 @@ examples:
remote-endpoint = <&usb2_role_switch>;
};
};
port@1 {
reg = <1>;
eud_con: endpoint {

69
Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml Normal file
View File

@@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,rpm-master-stats.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) RPM Master Stats
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
The Qualcomm RPM (Resource Power Manager) architecture includes a concept
of "RPM Masters". They can be thought of as "the local gang leaders", usually
spanning a single subsystem (e.g. APSS, ADSP, CDSP). All of the RPM decisions
(particularly around entering hardware-driven low power modes: XO shutdown
and total system-wide power collapse) are first made at Master-level, and
only then aggregated for the entire system.
The Master Stats provide a few useful bits that can be used to assess whether
our device has entered the desired low-power mode, how long it took to do so,
the duration of that residence, how long it took to come back online,
how many times a given sleep state was entered and which cores are actively
voting for staying awake.
This scheme has been used on various SoCs in the 2013-2023 era, with some
newer or higher-end designs providing this information through an SMEM query.
properties:
compatible:
const: qcom,rpm-master-stats
qcom,rpm-msg-ram:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: Phandle to an RPM MSG RAM slice containing the master stats
minItems: 1
maxItems: 5
qcom,master-names:
$ref: /schemas/types.yaml#/definitions/string-array
description:
The name of the RPM Master which owns the MSG RAM slice where this
instance of Master Stats resides
minItems: 1
maxItems: 5
required:
- compatible
- qcom,rpm-msg-ram
- qcom,master-names
additionalProperties: false
examples:
- |
stats {
compatible = "qcom,rpm-master-stats";
qcom,rpm-msg-ram = <&apss_master_stats>,
<&mpss_master_stats>,
<&adsp_master_stats>,
<&cdsp_master_stats>,
<&tz_master_stats>;
qcom,master-names = "APSS",
"MPSS",
"ADSP",
"CDSP",
"TZ";
};
...

2
Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
View File

@@ -124,6 +124,7 @@ required:
- qcom,tcs-offset
- reg
- reg-names
- power-domains
additionalProperties: false
@@ -179,6 +180,7 @@ examples:
<SLEEP_TCS 1>,
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
power-domains = <&CLUSTER_PD>;
};
- |

1
Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
View File

@@ -81,6 +81,7 @@ if:
contains:
enum:
- qcom,rpm-apq8084
- qcom,rpm-msm8226
- qcom,rpm-msm8916
- qcom,rpm-msm8936
- qcom,rpm-msm8974

3
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
View File

@@ -24,6 +24,7 @@ properties:
- rockchip,rk3588-bigcore1-grf
- rockchip,rk3588-ioc
- rockchip,rk3588-php-grf
- rockchip,rk3588-pipe-phy-grf
- rockchip,rk3588-sys-grf
- rockchip,rk3588-pcie3-phy-grf
- rockchip,rk3588-pcie3-pipe-grf
@@ -52,6 +53,7 @@ properties:
- rockchip,rk3399-pmugrf
- rockchip,rk3568-grf
- rockchip,rk3568-pmugrf
- rockchip,rk3588-usb2phy-grf
- rockchip,rv1108-grf
- rockchip,rv1108-pmugrf
- rockchip,rv1126-grf
@@ -199,6 +201,7 @@ allOf:
- rockchip,rk3308-usb2phy-grf
- rockchip,rk3328-usb2phy-grf
- rockchip,rk3399-grf
- rockchip,rk3588-usb2phy-grf
- rockchip,rv1108-grf
then:

5
Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
View File

@@ -17,6 +17,7 @@ select:
enum:
- samsung,exynos3250-pmu
- samsung,exynos4210-pmu
- samsung,exynos4212-pmu
- samsung,exynos4412-pmu
- samsung,exynos5250-pmu
- samsung,exynos5260-pmu
@@ -36,6 +37,7 @@ properties:
- enum:
- samsung,exynos3250-pmu
- samsung,exynos4210-pmu
- samsung,exynos4212-pmu
- samsung,exynos4412-pmu
- samsung,exynos5250-pmu
- samsung,exynos5260-pmu
@@ -50,6 +52,7 @@ properties:
- enum:
- samsung,exynos3250-pmu
- samsung,exynos4210-pmu
- samsung,exynos4212-pmu
- samsung,exynos4412-pmu
- samsung,exynos5250-pmu
- samsung,exynos5420-pmu
@@ -125,6 +128,7 @@ allOf:
enum:
- samsung,exynos3250-pmu
- samsung,exynos4210-pmu
- samsung,exynos4212-pmu
- samsung,exynos4412-pmu
- samsung,exynos5250-pmu
- samsung,exynos5410-pmu
@@ -143,6 +147,7 @@ allOf:
enum:
- samsung,exynos3250-pmu
- samsung,exynos4210-pmu
- samsung,exynos4212-pmu
- samsung,exynos4412-pmu
- samsung,exynos5250-pmu
- samsung,exynos5420-pmu

11
Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
View File

@@ -18,9 +18,14 @@ allOf:
properties:
compatible:
enum:
- mediatek,mt6873-spmi
- mediatek,mt8195-spmi
oneOf:
- enum:
- mediatek,mt6873-spmi
- mediatek,mt8195-spmi
- items:
- enum:
- mediatek,mt8186-spmi
- const: mediatek,mt8195-spmi
reg:
maxItems: 2

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