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sparc64: Add Niagara2 RNG driver.
With feedback and suggestions from Sam Ravnborg. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
@@ -59,6 +59,19 @@ config HW_RANDOM_GEODE
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If unsure, say Y.
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config HW_RANDOM_N2RNG
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tristate "Niagara2 Random Number Generator support"
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depends on HW_RANDOM && SPARC64
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default HW_RANDOM
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---help---
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This driver provides kernel-side support for the Random Number
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Generator hardware found on Niagara2 cpus.
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To compile this driver as a module, choose M here: the
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module will be called n2-rng.
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If unsure, say Y.
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config HW_RANDOM_VIA
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tristate "VIA HW Random Number Generator support"
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depends on HW_RANDOM && X86_32
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@@ -7,6 +7,8 @@ rng-core-y := core.o
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obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o
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obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o
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obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o
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obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o
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n2-rng-y := n2-drv.o n2-asm.o
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obj-$(CONFIG_HW_RANDOM_VIA) += via-rng.o
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obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o
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obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o
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79
drivers/char/hw_random/n2-asm.S
Normal file
79
drivers/char/hw_random/n2-asm.S
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@@ -0,0 +1,79 @@
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/* n2-asm.S: Niagara2 RNG hypervisor call assembler.
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*
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* Copyright (C) 2008 David S. Miller <davem@davemloft.net>
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*/
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#include <linux/linkage.h>
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#include <asm/hypervisor.h>
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#include "n2rng.h"
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.text
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ENTRY(sun4v_rng_get_diag_ctl)
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mov HV_FAST_RNG_GET_DIAG_CTL, %o5
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ta HV_FAST_TRAP
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retl
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nop
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ENDPROC(sun4v_rng_get_diag_ctl)
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ENTRY(sun4v_rng_ctl_read_v1)
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mov %o1, %o3
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mov %o2, %o4
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mov HV_FAST_RNG_CTL_READ, %o5
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ta HV_FAST_TRAP
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stx %o1, [%o3]
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retl
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stx %o2, [%o4]
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ENDPROC(sun4v_rng_ctl_read_v1)
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ENTRY(sun4v_rng_ctl_read_v2)
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save %sp, -192, %sp
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mov %i0, %o0
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mov %i1, %o1
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mov HV_FAST_RNG_CTL_READ, %o5
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ta HV_FAST_TRAP
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stx %o1, [%i2]
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stx %o2, [%i3]
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stx %o3, [%i4]
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stx %o4, [%i5]
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ret
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restore %g0, %o0, %o0
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ENDPROC(sun4v_rng_ctl_read_v2)
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ENTRY(sun4v_rng_ctl_write_v1)
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mov %o3, %o4
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mov HV_FAST_RNG_CTL_WRITE, %o5
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ta HV_FAST_TRAP
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retl
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stx %o1, [%o4]
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ENDPROC(sun4v_rng_ctl_write_v1)
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ENTRY(sun4v_rng_ctl_write_v2)
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mov HV_FAST_RNG_CTL_WRITE, %o5
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ta HV_FAST_TRAP
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retl
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nop
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ENDPROC(sun4v_rng_ctl_write_v2)
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ENTRY(sun4v_rng_data_read_diag_v1)
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mov %o2, %o4
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mov HV_FAST_RNG_DATA_READ_DIAG, %o5
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ta HV_FAST_TRAP
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retl
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stx %o1, [%o4]
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ENDPROC(sun4v_rng_data_read_diag_v1)
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ENTRY(sun4v_rng_data_read_diag_v2)
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mov %o3, %o4
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mov HV_FAST_RNG_DATA_READ_DIAG, %o5
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ta HV_FAST_TRAP
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retl
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stx %o1, [%o4]
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ENDPROC(sun4v_rng_data_read_diag_v2)
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ENTRY(sun4v_rng_data_read)
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mov %o1, %o4
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mov HV_FAST_RNG_DATA_READ, %o5
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ta HV_FAST_TRAP
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retl
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stx %o1, [%o4]
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ENDPROC(sun4v_rng_data_read)
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771
drivers/char/hw_random/n2-drv.c
Normal file
771
drivers/char/hw_random/n2-drv.c
Normal file
File diff suppressed because it is too large
Load Diff
118
drivers/char/hw_random/n2rng.h
Normal file
118
drivers/char/hw_random/n2rng.h
Normal file
@@ -0,0 +1,118 @@
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/* n2rng.h: Niagara2 RNG defines.
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*
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* Copyright (C) 2008 David S. Miller <davem@davemloft.net>
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*/
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#ifndef _N2RNG_H
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#define _N2RNG_H
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#define RNG_CTL_WAIT 0x0000000001fffe00ULL /* Minimum wait time */
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#define RNG_CTL_WAIT_SHIFT 9
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#define RNG_CTL_BYPASS 0x0000000000000100ULL /* VCO voltage source */
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#define RNG_CTL_VCO 0x00000000000000c0ULL /* VCO rate control */
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#define RNG_CTL_VCO_SHIFT 6
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#define RNG_CTL_ASEL 0x0000000000000030ULL /* Analog MUX select */
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#define RNG_CTL_ASEL_SHIFT 4
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#define RNG_CTL_LFSR 0x0000000000000008ULL /* Use LFSR or plain shift */
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#define RNG_CTL_ES3 0x0000000000000004ULL /* Enable entropy source 3 */
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#define RNG_CTL_ES2 0x0000000000000002ULL /* Enable entropy source 2 */
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#define RNG_CTL_ES1 0x0000000000000001ULL /* Enable entropy source 1 */
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#define HV_FAST_RNG_GET_DIAG_CTL 0x130
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#define HV_FAST_RNG_CTL_READ 0x131
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#define HV_FAST_RNG_CTL_WRITE 0x132
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#define HV_FAST_RNG_DATA_READ_DIAG 0x133
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#define HV_FAST_RNG_DATA_READ 0x134
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#define HV_RNG_STATE_UNCONFIGURED 0
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#define HV_RNG_STATE_CONFIGURED 1
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#define HV_RNG_STATE_HEALTHCHECK 2
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#define HV_RNG_STATE_ERROR 3
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#define HV_RNG_NUM_CONTROL 4
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#ifndef __ASSEMBLY__
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extern unsigned long sun4v_rng_get_diag_ctl(void);
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extern unsigned long sun4v_rng_ctl_read_v1(unsigned long ctl_regs_ra,
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unsigned long *state,
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unsigned long *tick_delta);
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extern unsigned long sun4v_rng_ctl_read_v2(unsigned long ctl_regs_ra,
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unsigned long unit,
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unsigned long *state,
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unsigned long *tick_delta,
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unsigned long *watchdog,
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unsigned long *write_status);
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extern unsigned long sun4v_rng_ctl_write_v1(unsigned long ctl_regs_ra,
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unsigned long state,
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unsigned long write_timeout,
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unsigned long *tick_delta);
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extern unsigned long sun4v_rng_ctl_write_v2(unsigned long ctl_regs_ra,
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unsigned long state,
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unsigned long write_timeout,
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unsigned long unit);
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extern unsigned long sun4v_rng_data_read_diag_v1(unsigned long data_ra,
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unsigned long len,
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unsigned long *tick_delta);
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extern unsigned long sun4v_rng_data_read_diag_v2(unsigned long data_ra,
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unsigned long len,
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unsigned long unit,
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unsigned long *tick_delta);
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extern unsigned long sun4v_rng_data_read(unsigned long data_ra,
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unsigned long *tick_delta);
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struct n2rng_unit {
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u64 control[HV_RNG_NUM_CONTROL];
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};
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struct n2rng {
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struct of_device *op;
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unsigned long flags;
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#define N2RNG_FLAG_VF 0x00000001 /* Victoria Falls RNG, else N2 */
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#define N2RNG_FLAG_CONTROL 0x00000002 /* Operating in control domain */
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#define N2RNG_FLAG_READY 0x00000008 /* Ready for hw-rng layer */
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#define N2RNG_FLAG_SHUTDOWN 0x00000010 /* Driver unregistering */
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#define N2RNG_FLAG_BUFFER_VALID 0x00000020 /* u32 buffer holds valid data */
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int num_units;
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struct n2rng_unit *units;
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struct hwrng hwrng;
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u32 buffer;
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/* Registered hypervisor group API major and minor version. */
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unsigned long hvapi_major;
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unsigned long hvapi_minor;
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struct delayed_work work;
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unsigned long hv_state; /* HV_RNG_STATE_foo */
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unsigned long health_check_sec;
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unsigned long accum_cycles;
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unsigned long wd_timeo;
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#define N2RNG_HEALTH_CHECK_SEC_DEFAULT 0
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#define N2RNG_ACCUM_CYCLES_DEFAULT 2048
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#define N2RNG_WD_TIMEO_DEFAULT 0
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u64 scratch_control[HV_RNG_NUM_CONTROL];
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#define SELFTEST_TICKS 38859
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#define SELFTEST_VAL ((u64)0xB8820C7BD387E32C)
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#define SELFTEST_POLY ((u64)0x231DCEE91262B8A3)
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#define SELFTEST_MATCH_GOAL 6
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#define SELFTEST_LOOPS_MAX 40000
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#define SELFTEST_BUFFER_WORDS 8
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u64 test_data;
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u64 test_control[HV_RNG_NUM_CONTROL];
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u64 test_buffer[SELFTEST_BUFFER_WORDS];
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};
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#define N2RNG_BLOCK_LIMIT 60000
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#define N2RNG_BUSY_LIMIT 100
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#define N2RNG_HCHECK_LIMIT 100
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#endif /* !(__ASSEMBLY__) */
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#endif /* _N2RNG_H */
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