mirror of
https://github.com/Dasharo/linux.git
synced 2026-03-06 15:25:10 -08:00
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We have some late breaking reports that a patch series to rework clk
rate range support broke boot on some devices, so I've left that
branch out of this. Hopefully we can get to that next week, or punt on
it and let it bake another cycle. That means we don't really have any
changes to the core framework this time around besides a few typo
fixes. Instead this is all clk driver updates and fixes.
The usual suspects are here (again), with Qualcomm dominating the
diffstat. We look to have gained support for quite a few new Qualcomm
SoCs and Dmitry worked on updating many of the existing Qualcomm
drivers to use clk_parent_data. After that we have MediaTek drivers
getting some much needed updates, in particular to support GPU DVFS.
There are also quite a few Samsung clk driver patches, but that's
mostly because there was a maintainer change and so last release we
missed some of those patches.
Overall things look normal, but I'm slowly reviewing core framework
code nowadays and that shows given the rate range patches had to be
yanked last minute. Let's hope this situation changes soon.
New Drivers:
- Support for Renesas VersaClock7 clock generator family
- Add Spreadtrum UMS512 SoC clk support
- New clock drivers for MediaTek Helio X10 MT6795
- Display clks for Qualcomm SM6115, SM8450
- GPU clks for Qualcomm SC8280XP
- Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers
Deleted Drivers:
- Remove DaVinci DM644x and DM646x clk driver support
Updates:
- Convert Baikal-T1 CCU driver to platform driver
- Split reset support out of primary Baikal-T1 CCU driver
- Add some missing clks required for RPiVid Video Decoder on
RaspberryPi
- Mark PLLC critical on bcm2835
- More devm helpers for fixed rate registration
- Various PXA168 clk driver fixes
- Add resets for MediaTek MT8195 PCIe and USB
- Miscellaneous of_node_put() fixes
- Nuke dt-bindings/clk path (again) by moving headers to
dt-bindings/clock
- Convert gpio-clk-gate binding to YAML
- Various fixes to AMD/Xilinx Zynqmp clk driver
- Graduate AMD/Xilinx "clocking wizard" driver from staging
- Add missing DPI1_HDMI clock in MT8195 VDOSYS1
- Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
- Fix GPU clock topology on MT8195
- Propogate rate changes from GPU clock gate up the tree
- Clock mux notifiers for GPU-related PLLs
- Conversion of more "simple" drivers to mtk_clk_simple_probe()
- Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
- Fixes to previous |struct clk| to |struct clk_hw| conversion on
MediaTek
- Shrink MT8192 clock driver by deduplicating clock parent lists
- Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk'
clocks for i.MX8MP
- Drop unnecessary newline in i.MX8MM dt-bindings
- Add more MU1 and SAI clocks dt-bindings Ids
- Introduce slice busy bit check for i.MX93 composite clock
- Introduce white list bit check for i.MX93 composite clock
- Add new i.MX93 clock gate
- Add MU1 and MU2 clocks to i.MX93 clock provider
- Add SAI IPG clocks to i.MX93 clock provider
- add generic clocks for U(S)ART available on SAMA5D2 SoCs
- reset controller support for Polarfire clocks
- .round_rate and .set rate support for clk-mpfs
- code cleanup for clk-mpfs
- PLL support for PolarFire SoC's Clock Conditioning Circuitry
- Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car
V4H
- Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8
- Add I2C clocks and resets on RZ/V2M
- Document clock support for the RZ/Five SoC
- mux-variant clock using the table variant to select parents
- clock controller for the rv1126 soc
- conversion of rk3128 to yaml and relicensing of the yaml bindings
to gpl2+MIT (following dt-binding guildelines)
- Exynos7885: add FSYS, TREX and MFC clock controllers
- Exynos850: add IS and AUD (audio) clock controllers with bindings
- ExynosAutov9: add FSYS clock controllers with bindings
- ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
controllers, due to duplicated entries. This is an acceptable ABI
break: recently developed/added platform so without legacies, acked
by known users/developers
- ExynosAutov9: add few missing Peric 0/1 gates
- ExynosAutov9: correct register offsets of few Peric 0/1 clocks
- Minor code improvements (use of_device_get_match_data() helper,
code style)
- Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as
he already maintainers that architecture/platform
- Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving
retention issues during suspend of USB on Qualcomm sc7180/sc7280
and SC8280XP
- Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration
- Qualcomm SDM660 SDCC1 moved to floor clk ops
- Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018
was added/fixed
- The Qualcomm MSM8996 CPU clocks are updated with support for ACD
- Support for Qualcomm SDM670 GCC and RPMh clks was added
- Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
num_parents was done for many Qualcomm SoCs
- Support for per-reset defined delay on Qualcomm was introduced"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (283 commits)
clk: qcom: gcc-sm6375: Ensure unsigned long type
clk: qcom: gcc-sm6375: Remove unused variables
clk: qcom: kpss-xcc: convert to parent data API
clk: introduce (devm_)hw_register_mux_parent_data_table API
clk: allow building lan966x as a module
clk: clk-xgene: simplify if-if to if-else
clk: ast2600: BCLK comes from EPLL
clk: clocking-wizard: Depend on HAS_IOMEM
clk: clocking-wizard: Use dev_err_probe() helper
clk: nxp: fix typo in comment
clk: pxa: add a check for the return value of kzalloc()
clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975
dt-bindings: clock: vc5: Add 5P49V6975
clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable
clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe
clk: Renesas versaclock7 ccf device driver
dt-bindings: Renesas versaclock7 device tree bindings
clk: ti: Balance of_node_get() calls for of_find_node_by_name()
clk: imx: scu: fix memleak on platform_device_add() fails
clk: vc5: Use regmap_{set,clear}_bits() where appropriate
...
This commit is contained in:
Linus Torvalds
@@ -23,6 +23,7 @@ properties:
|
||||
- mediatek,mt2701-infracfg
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||||
- mediatek,mt2712-infracfg
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- mediatek,mt6765-infracfg
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- mediatek,mt6795-infracfg
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- mediatek,mt6779-infracfg_ao
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- mediatek,mt6797-infracfg
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- mediatek,mt7622-infracfg
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@@ -60,6 +61,7 @@ if:
|
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enum:
|
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- mediatek,mt2701-infracfg
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- mediatek,mt2712-infracfg
|
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- mediatek,mt6795-infracfg
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- mediatek,mt7622-infracfg
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- mediatek,mt7986-infracfg
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- mediatek,mt8135-infracfg
|
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|
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@@ -25,6 +25,7 @@ properties:
|
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- mediatek,mt2712-mmsys
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- mediatek,mt6765-mmsys
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- mediatek,mt6779-mmsys
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- mediatek,mt6795-mmsys
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- mediatek,mt6797-mmsys
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- mediatek,mt8167-mmsys
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- mediatek,mt8173-mmsys
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|
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@@ -21,6 +21,7 @@ properties:
|
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- mediatek,mt2701-pericfg
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- mediatek,mt2712-pericfg
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- mediatek,mt6765-pericfg
|
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- mediatek,mt6795-pericfg
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- mediatek,mt7622-pericfg
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- mediatek,mt7629-pericfg
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- mediatek,mt8135-pericfg
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|
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@@ -23,7 +23,6 @@ properties:
|
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clocks:
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description:
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Common clock binding for CLK_IN, XTI/REF_CLK
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minItems: 2
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maxItems: 2
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clock-names:
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@@ -1,21 +0,0 @@
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Binding for simple gpio gated clock.
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be "gpio-gate-clock".
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- #clock-cells : from common clock binding; shall be set to 0.
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- enable-gpios : GPIO reference for enabling and disabling the clock.
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Optional properties:
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- clocks: Maximum of one parent clock is supported.
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|
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Example:
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clock {
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compatible = "gpio-gate-clock";
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clocks = <&parentclk>;
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#clock-cells = <0>;
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enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
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};
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42
Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
Normal file
42
Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
Normal file
@@ -0,0 +1,42 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/gpio-gate-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Simple GPIO clock gate
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maintainers:
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- Jyri Sarha <jsarha@ti.com>
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properties:
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compatible:
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const: gpio-gate-clock
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clocks:
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maxItems: 1
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'#clock-cells':
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const: 0
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enable-gpios:
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description: GPIO reference for enabling and disabling the clock.
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maxItems: 1
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required:
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- compatible
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- '#clock-cells'
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- enable-gpios
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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clock {
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compatible = "gpio-gate-clock";
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clocks = <&parentclk>;
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#clock-cells = <0>;
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enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
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};
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@@ -56,6 +56,7 @@ properties:
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- idt,5p49v5935
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- idt,5p49v6901
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- idt,5p49v6965
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- idt,5p49v6975
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reg:
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description: I2C device address
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@@ -108,7 +109,7 @@ patternProperties:
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properties:
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idt,mode:
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description:
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The output drive mode. Values defined in dt-bindings/clk/versaclock.h
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The output drive mode. Values defined in dt-bindings/clock/versaclock.h
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 6
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@@ -134,6 +135,7 @@ allOf:
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enum:
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- idt,5p49v5933
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- idt,5p49v5935
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- idt,5p49v6975
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then:
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# Devices with builtin crystal + optional external input
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properties:
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@@ -151,7 +153,7 @@ additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clk/versaclock.h>
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#include <dt-bindings/clock/versaclock.h>
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/* 25MHz reference crystal */
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ref25: ref25m {
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@@ -34,6 +34,7 @@ properties:
|
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- mediatek,mt2712-apmixedsys
|
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- mediatek,mt6765-apmixedsys
|
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- mediatek,mt6779-apmixedsys
|
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- mediatek,mt6795-apmixedsys
|
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- mediatek,mt7629-apmixedsys
|
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- mediatek,mt8167-apmixedsys
|
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- mediatek,mt8183-apmixedsys
|
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|
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@@ -0,0 +1,66 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Functional Clock Controller for MT6795
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|
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maintainers:
|
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- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
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- Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
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description: |
|
||||
The clock architecture in MediaTek like below
|
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PLLs -->
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dividers -->
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muxes
|
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-->
|
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clock gate
|
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|
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The devices provide clock gate control in different IP blocks.
|
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|
||||
properties:
|
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compatible:
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||||
enum:
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||||
- mediatek,mt6795-mfgcfg
|
||||
- mediatek,mt6795-vdecsys
|
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- mediatek,mt6795-vencsys
|
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|
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reg:
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maxItems: 1
|
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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mfgcfg: clock-controller@13000000 {
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compatible = "mediatek,mt6795-mfgcfg";
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reg = <0 0x13000000 0 0x1000>;
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#clock-cells = <1>;
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};
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vdecsys: clock-controller@16000000 {
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compatible = "mediatek,mt6795-vdecsys";
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reg = <0 0x16000000 0 0x1000>;
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#clock-cells = <1>;
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};
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vencsys: clock-controller@18000000 {
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compatible = "mediatek,mt6795-vencsys";
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reg = <0 0x18000000 0 0x1000>;
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#clock-cells = <1>;
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};
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};
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@@ -0,0 +1,54 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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||||
$id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml#
|
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$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
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title: MediaTek System Clock Controller for MT6795
|
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|
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maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
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description:
|
||||
The Mediatek system clock controller provides various clocks and system
|
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configuration like reset and bus protection on MT6795.
|
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properties:
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compatible:
|
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items:
|
||||
- enum:
|
||||
- mediatek,mt6795-apmixedsys
|
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- mediatek,mt6795-infracfg
|
||||
- mediatek,mt6795-pericfg
|
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- mediatek,mt6795-topckgen
|
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- const: syscon
|
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reg:
|
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maxItems: 1
|
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|
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'#clock-cells':
|
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const: 1
|
||||
|
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'#reset-cells':
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const: 1
|
||||
|
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required:
|
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- compatible
|
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- reg
|
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- '#clock-cells'
|
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|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
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soc {
|
||||
#address-cells = <2>;
|
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#size-cells = <2>;
|
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topckgen: clock-controller@10000000 {
|
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compatible = "mediatek,mt6795-topckgen", "syscon";
|
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
|
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};
|
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@@ -0,0 +1,42 @@
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||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8365-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8365
|
||||
|
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maintainers:
|
||||
- Markus Schneider-Pargmann <msp@baylibre.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8365-apu
|
||||
- mediatek,mt8365-imgsys
|
||||
- mediatek,mt8365-mfgcfg
|
||||
- mediatek,mt8365-vdecsys
|
||||
- mediatek,mt8365-vencsys
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
apu: clock-controller@19020000 {
|
||||
compatible = "mediatek,mt8365-apu", "syscon";
|
||||
reg = <0x19020000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT8365
|
||||
|
||||
maintainers:
|
||||
- Markus Schneider-Pargmann <msp@baylibre.com>
|
||||
|
||||
description:
|
||||
The apmixedsys module provides most of PLLs which generated from SoC 26m.
|
||||
The topckgen provides dividers and muxes which provides the clock source to other IP blocks.
|
||||
The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8365-topckgen
|
||||
- mediatek,mt8365-infracfg
|
||||
- mediatek,mt8365-apmixedsys
|
||||
- mediatek,mt8365-pericfg
|
||||
- mediatek,mt8365-mcucfg
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
topckgen: clock-controller@10000000 {
|
||||
compatible = "mediatek,mt8365-topckgen", "syscon";
|
||||
reg = <0x10000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@@ -33,6 +33,7 @@ properties:
|
||||
- mediatek,mt2712-topckgen
|
||||
- mediatek,mt6765-topckgen
|
||||
- mediatek,mt6779-topckgen
|
||||
- mediatek,mt6795-topckgen
|
||||
- mediatek,mt7629-topckgen
|
||||
- mediatek,mt7986-topckgen
|
||||
- mediatek,mt8167-topckgen
|
||||
|
||||
@@ -0,0 +1,80 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
|
||||
|
||||
maintainers:
|
||||
- Conor Dooley <conor.dooley@microchip.com>
|
||||
|
||||
description: |
|
||||
Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
|
||||
these blocks contains two PLLs and 2 DLLs & are located in the four corners of
|
||||
the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
|
||||
https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: microchip,mpfs-ccc
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: PLL0's control registers
|
||||
- description: PLL1's control registers
|
||||
- description: DLL0's control registers
|
||||
- description: DLL1's control registers
|
||||
|
||||
clocks:
|
||||
description:
|
||||
The CCC PLL's have two input clocks. It is required that even if the input
|
||||
clocks are identical that both are provided.
|
||||
minItems: 2
|
||||
items:
|
||||
- description: PLL0's refclk0
|
||||
- description: PLL0's refclk1
|
||||
- description: PLL1's refclk0
|
||||
- description: PLL1's refclk1
|
||||
- description: DLL0's refclk
|
||||
- description: DLL1's refclk
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: pll0_ref0
|
||||
- const: pll0_ref1
|
||||
- const: pll1_ref0
|
||||
- const: pll1_ref1
|
||||
- const: dll0_ref
|
||||
- const: dll1_ref
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell.
|
||||
See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
|
||||
PolarFire clock IDs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@38100000 {
|
||||
compatible = "microchip,mpfs-ccc";
|
||||
reg = <0x38010000 0x1000>, <0x38020000 0x1000>,
|
||||
<0x39010000 0x1000>, <0x39020000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
|
||||
<&refclk_ccc>, <&refclk_ccc>;
|
||||
clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
|
||||
"dll0_ref", "dll1_ref";
|
||||
};
|
||||
@@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip PolarFire Clock Control Module Binding
|
||||
@@ -40,8 +40,21 @@ properties:
|
||||
const: 1
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
|
||||
for the full list of PolarFire clock IDs.
|
||||
ID in its "clocks" phandle cell.
|
||||
See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
|
||||
PolarFire clock IDs.
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
'#reset-cells':
|
||||
description:
|
||||
The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
|
||||
CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
|
||||
peripheral via the clock ID in its "resets" phandle cell.
|
||||
See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
|
||||
PolarFire clock IDs.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm A53 PLL Binding
|
||||
|
||||
maintainers:
|
||||
- Sivaprakash Murugesan <sivaprak@codeaurora.org>
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description:
|
||||
The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for
|
||||
@@ -17,6 +17,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,ipq6018-a53pll
|
||||
- qcom,ipq8074-a53pll
|
||||
- qcom,msm8916-a53pll
|
||||
- qcom,msm8939-a53pll
|
||||
|
||||
|
||||
@@ -38,6 +38,15 @@ properties:
|
||||
description: child tsens device
|
||||
$ref: /schemas/thermal/qcom-tsens.yaml#
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: cxo
|
||||
- const: pxo
|
||||
- const: pll4
|
||||
|
||||
nvmem-cells:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
@@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8660.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8660
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks and resets on
|
||||
MSM8660
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8660.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8660.h
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,gcc.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-msm8660
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pxo
|
||||
- const: cxo
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
# Example for GCC for MSM8974:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8660";
|
||||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clocks = <&pxo_board>, <&cxo_board>;
|
||||
clock-names = "pxo", "cxo";
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8909
|
||||
|
||||
maintainers:
|
||||
- Stephan Gerhold <stephan@gerhold.net>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8909.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8909.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-msm8909
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO source
|
||||
- description: Sleep clock source
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
- const: dsi0pll
|
||||
- const: dsi0pllbyte
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
gcc: clock-controller@1800000 {
|
||||
compatible = "qcom,gcc-msm8909";
|
||||
reg = <0x01800000 0x80000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clocks = <&xo_board>, <&sleep_clk>, <&dsi0_phy 1>, <&dsi0_phy 0>;
|
||||
clock-names = "xo", "sleep_clk", "dsi0pll", "dsi0pllbyte";
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8916 and MSM8939
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8916 or MSM8939.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8916.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8939.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8916.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8939.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8939
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO source
|
||||
- description: Sleep clock source
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
- description: External MCLK clock
|
||||
- description: External Primary I2S clock
|
||||
- description: External Secondary I2S clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
- const: dsi0pll
|
||||
- const: dsi0pllbyte
|
||||
- const: ext_mclk
|
||||
- const: ext_pri_i2s
|
||||
- const: ext_sec_i2s
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@300000 {
|
||||
compatible = "qcom,gcc-msm8916";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0x300000 0x90000>;
|
||||
};
|
||||
...
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user