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Merge branch 'pm-cpufreq'
* pm-cpufreq: (33 commits) cpufreq: imx6q: Fix imx6sx low frequency support cpufreq: speedstep-lib: make several arrays static, makes code smaller cpufreq: ti: Fix 'of_node_put' being called twice in error handling path cpufreq: dt-platdev: Drop few entries from whitelist cpufreq: dt-platdev: Automatically create cpufreq device with OPP v2 ARM: ux500: don't select CPUFREQ_DT cpufreq: Convert to using %pOF instead of full_name cpufreq: Cap the default transition delay value to 10 ms cpufreq: dbx500: Delete obsolete driver mfd: db8500-prcmu: Get rid of cpufreq dependency cpufreq: enable the DT cpufreq driver on the Ux500 cpufreq: Loongson2: constify platform_device_id cpufreq: dt: Add r8a7796 support to to use generic cpufreq driver cpufreq: remove setting of policy->cpu in policy->cpus during init cpufreq: mediatek: add support of cpufreq to MT7622 SoC cpufreq: mediatek: add cleanups with the more generic naming cpufreq: rcar: Add support for R8A7795 SoC cpufreq: dt: Add rk3328 compatible to use generic cpufreq driver cpufreq: s5pv210: add missing of_node_put() cpufreq: Allow dynamic switching with CPUFREQ_ETERNAL latency ...
This commit is contained in:
Rafael J. Wysocki
@@ -479,14 +479,6 @@ This governor exposes the following tunables:
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# echo `$(($(cat cpuinfo_transition_latency) * 750 / 1000)) > ondemand/sampling_rate
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``min_sampling_rate``
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The minimum value of ``sampling_rate``.
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Equal to 10000 (10 ms) if :c:macro:`CONFIG_NO_HZ_COMMON` and
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:c:data:`tick_nohz_active` are both set or to 20 times the value of
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:c:data:`jiffies` in microseconds otherwise.
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``up_threshold``
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If the estimated CPU load is above this value (in percent), the governor
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will set the frequency to the maximum value allowed for the policy.
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@@ -1,83 +0,0 @@
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Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
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Required properties:
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- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
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- clock-names: Should contain the following:
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"cpu" - The multiplexer for clock input of CPU cluster.
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"intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
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source (usually MAINPLL) when the original CPU PLL is under
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transition and not stable yet.
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Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
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generic clock consumer properties.
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- proc-supply: Regulator for Vproc of CPU cluster.
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Optional properties:
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- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
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needs to do "voltage tracking" to step by step scale up/down Vproc and
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Vsram to fit SoC specific needs. When absent, the voltage scaling
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flow is handled by hardware, hence no software "voltage tracking" is
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needed.
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Example:
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--------
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x000>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&infracfg CLK_INFRA_CA53SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x001>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&infracfg CLK_INFRA_CA53SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&infracfg CLK_INFRA_CA57SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&infracfg CLK_INFRA_CA57SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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};
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&cpu0 {
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proc-supply = <&mt6397_vpca15_reg>;
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};
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&cpu1 {
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proc-supply = <&mt6397_vpca15_reg>;
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};
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&cpu2 {
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proc-supply = <&da9211_vcpu_reg>;
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sram-supply = <&mt6397_vsramca7_reg>;
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};
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&cpu3 {
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proc-supply = <&da9211_vcpu_reg>;
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sram-supply = <&mt6397_vsramca7_reg>;
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};
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247
Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
Normal file
247
Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
Normal file
@@ -0,0 +1,247 @@
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Binding for MediaTek's CPUFreq driver
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=====================================
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Required properties:
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- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
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- clock-names: Should contain the following:
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"cpu" - The multiplexer for clock input of CPU cluster.
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"intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
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source (usually MAINPLL) when the original CPU PLL is under
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transition and not stable yet.
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Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
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generic clock consumer properties.
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- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
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for detail.
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- proc-supply: Regulator for Vproc of CPU cluster.
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Optional properties:
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- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
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needs to do "voltage tracking" to step by step scale up/down Vproc and
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Vsram to fit SoC specific needs. When absent, the voltage scaling
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flow is handled by hardware, hence no software "voltage tracking" is
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needed.
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- #cooling-cells:
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- cooling-min-level:
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- cooling-max-level:
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Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
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for detail.
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Example 1 (MT7623 SoC):
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cpu_opp_table: opp_table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-598000000 {
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opp-hz = /bits/ 64 <598000000>;
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opp-microvolt = <1050000>;
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};
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opp-747500000 {
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opp-hz = /bits/ 64 <747500000>;
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opp-microvolt = <1050000>;
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};
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opp-1040000000 {
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opp-hz = /bits/ 64 <1040000000>;
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opp-microvolt = <1150000>;
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};
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opp-1196000000 {
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opp-hz = /bits/ 64 <1196000000>;
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opp-microvolt = <1200000>;
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};
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <1300000>;
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clocks = <&infracfg CLK_INFRA_CPUSEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>;
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cooling-min-level = <0>;
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cooling-max-level = <7>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x3>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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Example 2 (MT8173 SoC):
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cpu_opp_table_a: opp_table_a {
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compatible = "operating-points-v2";
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opp-shared;
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opp-507000000 {
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opp-hz = /bits/ 64 <507000000>;
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opp-microvolt = <859000>;
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};
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opp-702000000 {
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opp-hz = /bits/ 64 <702000000>;
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opp-microvolt = <908000>;
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};
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opp-1001000000 {
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opp-hz = /bits/ 64 <1001000000>;
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opp-microvolt = <983000>;
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};
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opp-1105000000 {
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opp-hz = /bits/ 64 <1105000000>;
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opp-microvolt = <1009000>;
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};
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opp-1183000000 {
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opp-hz = /bits/ 64 <1183000000>;
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opp-microvolt = <1028000>;
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};
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opp-1404000000 {
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opp-hz = /bits/ 64 <1404000000>;
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opp-microvolt = <1083000>;
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};
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opp-1508000000 {
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opp-hz = /bits/ 64 <1508000000>;
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opp-microvolt = <1109000>;
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};
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opp-1573000000 {
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opp-hz = /bits/ 64 <1573000000>;
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opp-microvolt = <1125000>;
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};
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};
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cpu_opp_table_b: opp_table_b {
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compatible = "operating-points-v2";
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opp-shared;
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opp-507000000 {
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opp-hz = /bits/ 64 <507000000>;
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opp-microvolt = <828000>;
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};
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opp-702000000 {
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opp-hz = /bits/ 64 <702000000>;
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opp-microvolt = <867000>;
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};
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opp-1001000000 {
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opp-hz = /bits/ 64 <1001000000>;
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opp-microvolt = <927000>;
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};
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opp-1209000000 {
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opp-hz = /bits/ 64 <1209000000>;
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opp-microvolt = <968000>;
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};
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opp-1404000000 {
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opp-hz = /bits/ 64 <1007000000>;
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opp-microvolt = <1028000>;
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};
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opp-1612000000 {
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opp-hz = /bits/ 64 <1612000000>;
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opp-microvolt = <1049000>;
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};
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opp-1807000000 {
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opp-hz = /bits/ 64 <1807000000>;
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opp-microvolt = <1089000>;
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};
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opp-1989000000 {
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opp-hz = /bits/ 64 <1989000000>;
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opp-microvolt = <1125000>;
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x000>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&infracfg CLK_INFRA_CA53SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table_a>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x001>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&infracfg CLK_INFRA_CA53SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table_a>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&infracfg CLK_INFRA_CA57SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table_b>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&infracfg CLK_INFRA_CA57SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table_b>;
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};
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&cpu0 {
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proc-supply = <&mt6397_vpca15_reg>;
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};
|
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&cpu1 {
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proc-supply = <&mt6397_vpca15_reg>;
|
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};
|
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&cpu2 {
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proc-supply = <&da9211_vcpu_reg>;
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sram-supply = <&mt6397_vsramca7_reg>;
|
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};
|
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&cpu3 {
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proc-supply = <&da9211_vcpu_reg>;
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sram-supply = <&mt6397_vsramca7_reg>;
|
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};
|
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@@ -13,7 +13,6 @@
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reg = <0>;
|
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clocks = <&clkgen CPU_CLK>;
|
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clock-latency = <1>;
|
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operating-points = <1215000 0 607500 0 405000 0 243000 0 135000 0>;
|
||||
};
|
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|
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cpu1: cpu@1 {
|
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|
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@@ -71,15 +71,6 @@ config ARM_HIGHBANK_CPUFREQ
|
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|
||||
If in doubt, say N.
|
||||
|
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config ARM_DB8500_CPUFREQ
|
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tristate "ST-Ericsson DB8500 cpufreq" if COMPILE_TEST && !ARCH_U8500
|
||||
default ARCH_U8500
|
||||
depends on HAS_IOMEM
|
||||
depends on !CPU_THERMAL || THERMAL
|
||||
help
|
||||
This adds the CPUFreq driver for ST-Ericsson Ux500 (DB8500) SoC
|
||||
series.
|
||||
|
||||
config ARM_IMX6Q_CPUFREQ
|
||||
tristate "Freescale i.MX6 cpufreq support"
|
||||
depends on ARCH_MXC
|
||||
@@ -96,14 +87,13 @@ config ARM_KIRKWOOD_CPUFREQ
|
||||
This adds the CPUFreq driver for Marvell Kirkwood
|
||||
SoCs.
|
||||
|
||||
config ARM_MT8173_CPUFREQ
|
||||
tristate "Mediatek MT8173 CPUFreq support"
|
||||
config ARM_MEDIATEK_CPUFREQ
|
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tristate "CPU Frequency scaling support for MediaTek SoCs"
|
||||
depends on ARCH_MEDIATEK && REGULATOR
|
||||
depends on ARM64 || (ARM_CPU_TOPOLOGY && COMPILE_TEST)
|
||||
depends on !CPU_THERMAL || THERMAL
|
||||
select PM_OPP
|
||||
help
|
||||
This adds the CPUFreq driver support for Mediatek MT8173 SoC.
|
||||
This adds the CPUFreq driver support for MediaTek SoCs.
|
||||
|
||||
config ARM_OMAP2PLUS_CPUFREQ
|
||||
bool "TI OMAP2+"
|
||||
@@ -242,6 +232,11 @@ config ARM_STI_CPUFREQ
|
||||
this config option if you wish to add CPUFreq support for STi based
|
||||
SoCs.
|
||||
|
||||
config ARM_TANGO_CPUFREQ
|
||||
bool
|
||||
depends on CPUFREQ_DT && ARCH_TANGO
|
||||
default y
|
||||
|
||||
config ARM_TEGRA20_CPUFREQ
|
||||
bool "Tegra20 CPUFreq support"
|
||||
depends on ARCH_TEGRA
|
||||
|
||||
@@ -53,12 +53,11 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o
|
||||
|
||||
obj-$(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ) += brcmstb-avs-cpufreq.o
|
||||
obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
|
||||
obj-$(CONFIG_ARM_DB8500_CPUFREQ) += dbx500-cpufreq.o
|
||||
obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
|
||||
obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
|
||||
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
|
||||
obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
|
||||
obj-$(CONFIG_ARM_MT8173_CPUFREQ) += mt8173-cpufreq.o
|
||||
obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o
|
||||
obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
|
||||
obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
|
||||
obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
|
||||
@@ -75,6 +74,7 @@ obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o
|
||||
obj-$(CONFIG_ARM_SCPI_CPUFREQ) += scpi-cpufreq.o
|
||||
obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
|
||||
obj-$(CONFIG_ARM_STI_CPUFREQ) += sti-cpufreq.o
|
||||
obj-$(CONFIG_ARM_TANGO_CPUFREQ) += tango-cpufreq.o
|
||||
obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o
|
||||
obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o
|
||||
obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += tegra186-cpufreq.o
|
||||
|
||||
@@ -483,11 +483,8 @@ static int bL_cpufreq_init(struct cpufreq_policy *policy)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (arm_bL_ops->get_transition_latency)
|
||||
policy->cpuinfo.transition_latency =
|
||||
arm_bL_ops->get_transition_latency(cpu_dev);
|
||||
else
|
||||
policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
|
||||
policy->cpuinfo.transition_latency =
|
||||
arm_bL_ops->get_transition_latency(cpu_dev);
|
||||
|
||||
if (is_bL_switching_enabled())
|
||||
per_cpu(cpu_last_req_freq, policy->cpu) = clk_get_cpu_rate(policy->cpu);
|
||||
@@ -622,7 +619,8 @@ int bL_cpufreq_register(struct cpufreq_arm_bL_ops *ops)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (!ops || !strlen(ops->name) || !ops->init_opp_table) {
|
||||
if (!ops || !strlen(ops->name) || !ops->init_opp_table ||
|
||||
!ops->get_transition_latency) {
|
||||
pr_err("%s: Invalid arm_bL_ops, exiting\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
@@ -172,7 +172,6 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
cpumask_set_cpu(policy->cpu, policy->cpus);
|
||||
cpu->cur_policy = policy;
|
||||
|
||||
/* Set policy->cur to max now. The governors will adjust later. */
|
||||
|
||||
@@ -9,11 +9,16 @@
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "cpufreq-dt.h"
|
||||
|
||||
static const struct of_device_id machines[] __initconst = {
|
||||
/*
|
||||
* Machines for which the cpufreq device is *always* created, mostly used for
|
||||
* platforms using "operating-points" (V1) property.
|
||||
*/
|
||||
static const struct of_device_id whitelist[] __initconst = {
|
||||
{ .compatible = "allwinner,sun4i-a10", },
|
||||
{ .compatible = "allwinner,sun5i-a10s", },
|
||||
{ .compatible = "allwinner,sun5i-a13", },
|
||||
@@ -22,7 +27,6 @@ static const struct of_device_id machines[] __initconst = {
|
||||
{ .compatible = "allwinner,sun6i-a31s", },
|
||||
{ .compatible = "allwinner,sun7i-a20", },
|
||||
{ .compatible = "allwinner,sun8i-a23", },
|
||||
{ .compatible = "allwinner,sun8i-a33", },
|
||||
{ .compatible = "allwinner,sun8i-a83t", },
|
||||
{ .compatible = "allwinner,sun8i-h3", },
|
||||
|
||||
@@ -32,7 +36,6 @@ static const struct of_device_id machines[] __initconst = {
|
||||
{ .compatible = "arm,integrator-cp", },
|
||||
|
||||
{ .compatible = "hisilicon,hi3660", },
|
||||
{ .compatible = "hisilicon,hi6220", },
|
||||
|
||||
{ .compatible = "fsl,imx27", },
|
||||
{ .compatible = "fsl,imx51", },
|
||||
@@ -46,11 +49,8 @@ static const struct of_device_id machines[] __initconst = {
|
||||
{ .compatible = "samsung,exynos3250", },
|
||||
{ .compatible = "samsung,exynos4210", },
|
||||
{ .compatible = "samsung,exynos4212", },
|
||||
{ .compatible = "samsung,exynos4412", },
|
||||
{ .compatible = "samsung,exynos5250", },
|
||||
#ifndef CONFIG_BL_SWITCHER
|
||||
{ .compatible = "samsung,exynos5420", },
|
||||
{ .compatible = "samsung,exynos5433", },
|
||||
{ .compatible = "samsung,exynos5800", },
|
||||
#endif
|
||||
|
||||
@@ -67,6 +67,8 @@ static const struct of_device_id machines[] __initconst = {
|
||||
{ .compatible = "renesas,r8a7792", },
|
||||
{ .compatible = "renesas,r8a7793", },
|
||||
{ .compatible = "renesas,r8a7794", },
|
||||
{ .compatible = "renesas,r8a7795", },
|
||||
{ .compatible = "renesas,r8a7796", },
|
||||
{ .compatible = "renesas,sh73a0", },
|
||||
|
||||
{ .compatible = "rockchip,rk2928", },
|
||||
@@ -76,17 +78,17 @@ static const struct of_device_id machines[] __initconst = {
|
||||
{ .compatible = "rockchip,rk3188", },
|
||||
{ .compatible = "rockchip,rk3228", },
|
||||
{ .compatible = "rockchip,rk3288", },
|
||||
{ .compatible = "rockchip,rk3328", },
|
||||
{ .compatible = "rockchip,rk3366", },
|
||||
{ .compatible = "rockchip,rk3368", },
|
||||
{ .compatible = "rockchip,rk3399", },
|
||||
|
||||
{ .compatible = "sigma,tango4" },
|
||||
|
||||
{ .compatible = "socionext,uniphier-pro5", },
|
||||
{ .compatible = "socionext,uniphier-pxs2", },
|
||||
{ .compatible = "socionext,uniphier-ld6b", },
|
||||
{ .compatible = "socionext,uniphier-ld11", },
|
||||
{ .compatible = "socionext,uniphier-ld20", },
|
||||
|
||||
{ .compatible = "st-ericsson,u8500", },
|
||||
{ .compatible = "st-ericsson,u8540", },
|
||||
{ .compatible = "st-ericsson,u9500", },
|
||||
{ .compatible = "st-ericsson,u9540", },
|
||||
|
||||
{ .compatible = "ti,omap2", },
|
||||
{ .compatible = "ti,omap3", },
|
||||
@@ -94,27 +96,56 @@ static const struct of_device_id machines[] __initconst = {
|
||||
{ .compatible = "ti,omap5", },
|
||||
|
||||
{ .compatible = "xlnx,zynq-7000", },
|
||||
|
||||
{ .compatible = "zte,zx296718", },
|
||||
{ .compatible = "xlnx,zynqmp", },
|
||||
|
||||
{ }
|
||||
};
|
||||
|
||||
/*
|
||||
* Machines for which the cpufreq device is *not* created, mostly used for
|
||||
* platforms using "operating-points-v2" property.
|
||||
*/
|
||||
static const struct of_device_id blacklist[] __initconst = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static bool __init cpu0_node_has_opp_v2_prop(void)
|
||||
{
|
||||
struct device_node *np = of_cpu_device_node_get(0);
|
||||
bool ret = false;
|
||||
|
||||
if (of_get_property(np, "operating-points-v2", NULL))
|
||||
ret = true;
|
||||
|
||||
of_node_put(np);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init cpufreq_dt_platdev_init(void)
|
||||
{
|
||||
struct device_node *np = of_find_node_by_path("/");
|
||||
const struct of_device_id *match;
|
||||
const void *data = NULL;
|
||||
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
|
||||
match = of_match_node(machines, np);
|
||||
of_node_put(np);
|
||||
if (!match)
|
||||
return -ENODEV;
|
||||
match = of_match_node(whitelist, np);
|
||||
if (match) {
|
||||
data = match->data;
|
||||
goto create_pdev;
|
||||
}
|
||||
|
||||
if (cpu0_node_has_opp_v2_prop() && !of_match_node(blacklist, np))
|
||||
goto create_pdev;
|
||||
|
||||
of_node_put(np);
|
||||
return -ENODEV;
|
||||
|
||||
create_pdev:
|
||||
of_node_put(np);
|
||||
return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt",
|
||||
-1, match->data,
|
||||
-1, data,
|
||||
sizeof(struct cpufreq_dt_platform_data)));
|
||||
}
|
||||
device_initcall(cpufreq_dt_platdev_init);
|
||||
|
||||
@@ -357,7 +357,6 @@ static int nforce2_cpu_init(struct cpufreq_policy *policy)
|
||||
/* cpuinfo and default policy values */
|
||||
policy->min = policy->cpuinfo.min_freq = min_fsb * fid * 100;
|
||||
policy->max = policy->cpuinfo.max_freq = max_fsb * fid * 100;
|
||||
policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -369,6 +368,7 @@ static int nforce2_cpu_exit(struct cpufreq_policy *policy)
|
||||
|
||||
static struct cpufreq_driver nforce2_driver = {
|
||||
.name = "nforce2",
|
||||
.flags = CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
|
||||
.verify = nforce2_verify,
|
||||
.target = nforce2_target,
|
||||
.get = nforce2_get,
|
||||
|
||||
@@ -524,6 +524,32 @@ unsigned int cpufreq_driver_resolve_freq(struct cpufreq_policy *policy,
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cpufreq_driver_resolve_freq);
|
||||
|
||||
unsigned int cpufreq_policy_transition_delay_us(struct cpufreq_policy *policy)
|
||||
{
|
||||
unsigned int latency;
|
||||
|
||||
if (policy->transition_delay_us)
|
||||
return policy->transition_delay_us;
|
||||
|
||||
latency = policy->cpuinfo.transition_latency / NSEC_PER_USEC;
|
||||
if (latency) {
|
||||
/*
|
||||
* For platforms that can change the frequency very fast (< 10
|
||||
* us), the above formula gives a decent transition delay. But
|
||||
* for platforms where transition_latency is in milliseconds, it
|
||||
* ends up giving unrealistic values.
|
||||
*
|
||||
* Cap the default transition delay to 10 ms, which seems to be
|
||||
* a reasonable amount of time after which we should reevaluate
|
||||
* the frequency.
|
||||
*/
|
||||
return min(latency * LATENCY_MULTIPLIER, (unsigned int)10000);
|
||||
}
|
||||
|
||||
return LATENCY_MULTIPLIER;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cpufreq_policy_transition_delay_us);
|
||||
|
||||
/*********************************************************************
|
||||
* SYSFS INTERFACE *
|
||||
*********************************************************************/
|
||||
@@ -1988,13 +2014,13 @@ static int cpufreq_init_governor(struct cpufreq_policy *policy)
|
||||
if (!policy->governor)
|
||||
return -EINVAL;
|
||||
|
||||
if (policy->governor->max_transition_latency &&
|
||||
policy->cpuinfo.transition_latency >
|
||||
policy->governor->max_transition_latency) {
|
||||
/* Platform doesn't want dynamic frequency switching ? */
|
||||
if (policy->governor->dynamic_switching &&
|
||||
cpufreq_driver->flags & CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING) {
|
||||
struct cpufreq_governor *gov = cpufreq_fallback_governor();
|
||||
|
||||
if (gov) {
|
||||
pr_warn("%s governor failed, too long transition latency of HW, fallback to %s governor\n",
|
||||
pr_warn("Can't use %s governor as dynamic switching is disallowed. Fallback to %s governor\n",
|
||||
policy->governor->name, gov->name);
|
||||
policy->governor = gov;
|
||||
} else {
|
||||
|
||||
@@ -246,7 +246,6 @@ gov_show_one_common(sampling_rate);
|
||||
gov_show_one_common(sampling_down_factor);
|
||||
gov_show_one_common(up_threshold);
|
||||
gov_show_one_common(ignore_nice_load);
|
||||
gov_show_one_common(min_sampling_rate);
|
||||
gov_show_one(cs, down_threshold);
|
||||
gov_show_one(cs, freq_step);
|
||||
|
||||
@@ -254,12 +253,10 @@ gov_attr_rw(sampling_rate);
|
||||
gov_attr_rw(sampling_down_factor);
|
||||
gov_attr_rw(up_threshold);
|
||||
gov_attr_rw(ignore_nice_load);
|
||||
gov_attr_ro(min_sampling_rate);
|
||||
gov_attr_rw(down_threshold);
|
||||
gov_attr_rw(freq_step);
|
||||
|
||||
static struct attribute *cs_attributes[] = {
|
||||
&min_sampling_rate.attr,
|
||||
&sampling_rate.attr,
|
||||
&sampling_down_factor.attr,
|
||||
&up_threshold.attr,
|
||||
@@ -297,10 +294,7 @@ static int cs_init(struct dbs_data *dbs_data)
|
||||
dbs_data->up_threshold = DEF_FREQUENCY_UP_THRESHOLD;
|
||||
dbs_data->sampling_down_factor = DEF_SAMPLING_DOWN_FACTOR;
|
||||
dbs_data->ignore_nice_load = 0;
|
||||
|
||||
dbs_data->tuners = tuners;
|
||||
dbs_data->min_sampling_rate = MIN_SAMPLING_RATE_RATIO *
|
||||
jiffies_to_usecs(10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -47,14 +47,11 @@ ssize_t store_sampling_rate(struct gov_attr_set *attr_set, const char *buf,
|
||||
{
|
||||
struct dbs_data *dbs_data = to_dbs_data(attr_set);
|
||||
struct policy_dbs_info *policy_dbs;
|
||||
unsigned int rate;
|
||||
int ret;
|
||||
ret = sscanf(buf, "%u", &rate);
|
||||
ret = sscanf(buf, "%u", &dbs_data->sampling_rate);
|
||||
if (ret != 1)
|
||||
return -EINVAL;
|
||||
|
||||
dbs_data->sampling_rate = max(rate, dbs_data->min_sampling_rate);
|
||||
|
||||
/*
|
||||
* We are operating under dbs_data->mutex and so the list and its
|
||||
* entries can't be freed concurrently.
|
||||
@@ -392,7 +389,6 @@ int cpufreq_dbs_governor_init(struct cpufreq_policy *policy)
|
||||
struct dbs_governor *gov = dbs_governor_of(policy);
|
||||
struct dbs_data *dbs_data;
|
||||
struct policy_dbs_info *policy_dbs;
|
||||
unsigned int latency;
|
||||
int ret = 0;
|
||||
|
||||
/* State should be equivalent to EXIT */
|
||||
@@ -431,16 +427,7 @@ int cpufreq_dbs_governor_init(struct cpufreq_policy *policy)
|
||||
if (ret)
|
||||
goto free_policy_dbs_info;
|
||||
|
||||
/* policy latency is in ns. Convert it to us first */
|
||||
latency = policy->cpuinfo.transition_latency / 1000;
|
||||
if (latency == 0)
|
||||
latency = 1;
|
||||
|
||||
/* Bring kernel and HW constraints together */
|
||||
dbs_data->min_sampling_rate = max(dbs_data->min_sampling_rate,
|
||||
MIN_LATENCY_MULTIPLIER * latency);
|
||||
dbs_data->sampling_rate = max(dbs_data->min_sampling_rate,
|
||||
LATENCY_MULTIPLIER * latency);
|
||||
dbs_data->sampling_rate = cpufreq_policy_transition_delay_us(policy);
|
||||
|
||||
if (!have_governor_per_policy())
|
||||
gov->gdbs_data = dbs_data;
|
||||
|
||||
@@ -41,7 +41,6 @@ enum {OD_NORMAL_SAMPLE, OD_SUB_SAMPLE};
|
||||
struct dbs_data {
|
||||
struct gov_attr_set attr_set;
|
||||
void *tuners;
|
||||
unsigned int min_sampling_rate;
|
||||
unsigned int ignore_nice_load;
|
||||
unsigned int sampling_rate;
|
||||
unsigned int sampling_down_factor;
|
||||
@@ -160,7 +159,7 @@ void cpufreq_dbs_governor_limits(struct cpufreq_policy *policy);
|
||||
#define CPUFREQ_DBS_GOVERNOR_INITIALIZER(_name_) \
|
||||
{ \
|
||||
.name = _name_, \
|
||||
.max_transition_latency = TRANSITION_LATENCY_LIMIT, \
|
||||
.dynamic_switching = true, \
|
||||
.owner = THIS_MODULE, \
|
||||
.init = cpufreq_dbs_governor_init, \
|
||||
.exit = cpufreq_dbs_governor_exit, \
|
||||
|
||||
@@ -319,7 +319,6 @@ gov_show_one_common(sampling_rate);
|
||||
gov_show_one_common(up_threshold);
|
||||
gov_show_one_common(sampling_down_factor);
|
||||
gov_show_one_common(ignore_nice_load);
|
||||
gov_show_one_common(min_sampling_rate);
|
||||
gov_show_one_common(io_is_busy);
|
||||
gov_show_one(od, powersave_bias);
|
||||
|
||||
@@ -329,10 +328,8 @@ gov_attr_rw(up_threshold);
|
||||
gov_attr_rw(sampling_down_factor);
|
||||
gov_attr_rw(ignore_nice_load);
|
||||
gov_attr_rw(powersave_bias);
|
||||
gov_attr_ro(min_sampling_rate);
|
||||
|
||||
static struct attribute *od_attributes[] = {
|
||||
&min_sampling_rate.attr,
|
||||
&sampling_rate.attr,
|
||||
&up_threshold.attr,
|
||||
&sampling_down_factor.attr,
|
||||
@@ -373,17 +370,8 @@ static int od_init(struct dbs_data *dbs_data)
|
||||
if (idle_time != -1ULL) {
|
||||
/* Idle micro accounting is supported. Use finer thresholds */
|
||||
dbs_data->up_threshold = MICRO_FREQUENCY_UP_THRESHOLD;
|
||||
/*
|
||||
* In nohz/micro accounting case we set the minimum frequency
|
||||
* not depending on HZ, but fixed (very low).
|
||||
*/
|
||||
dbs_data->min_sampling_rate = MICRO_FREQUENCY_MIN_SAMPLE_RATE;
|
||||
} else {
|
||||
dbs_data->up_threshold = DEF_FREQUENCY_UP_THRESHOLD;
|
||||
|
||||
/* For correct statistics, we need 10 ticks for each measure */
|
||||
dbs_data->min_sampling_rate = MIN_SAMPLING_RATE_RATIO *
|
||||
jiffies_to_usecs(10);
|
||||
}
|
||||
|
||||
dbs_data->sampling_down_factor = DEF_SAMPLING_DOWN_FACTOR;
|
||||
|
||||
@@ -1,103 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2009
|
||||
* Copyright (C) ST-Ericsson SA 2010-2012
|
||||
*
|
||||
* License Terms: GNU General Public License v2
|
||||
* Author: Sundar Iyer <sundar.iyer@stericsson.com>
|
||||
* Author: Martin Persson <martin.persson@stericsson.com>
|
||||
* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/cpu_cooling.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
static struct cpufreq_frequency_table *freq_table;
|
||||
static struct clk *armss_clk;
|
||||
static struct thermal_cooling_device *cdev;
|
||||
|
||||
static int dbx500_cpufreq_target(struct cpufreq_policy *policy,
|
||||
unsigned int index)
|
||||
{
|
||||
/* update armss clk frequency */
|
||||
return clk_set_rate(armss_clk, freq_table[index].frequency * 1000);
|
||||
}
|
||||
|
||||
static int dbx500_cpufreq_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
policy->clk = armss_clk;
|
||||
return cpufreq_generic_init(policy, freq_table, 20 * 1000);
|
||||
}
|
||||
|
||||
static int dbx500_cpufreq_exit(struct cpufreq_policy *policy)
|
||||
{
|
||||
if (!IS_ERR(cdev))
|
||||
cpufreq_cooling_unregister(cdev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dbx500_cpufreq_ready(struct cpufreq_policy *policy)
|
||||
{
|
||||
cdev = cpufreq_cooling_register(policy);
|
||||
if (IS_ERR(cdev))
|
||||
pr_err("Failed to register cooling device %ld\n", PTR_ERR(cdev));
|
||||
else
|
||||
pr_info("Cooling device registered: %s\n", cdev->type);
|
||||
}
|
||||
|
||||
static struct cpufreq_driver dbx500_cpufreq_driver = {
|
||||
.flags = CPUFREQ_STICKY | CPUFREQ_CONST_LOOPS |
|
||||
CPUFREQ_NEED_INITIAL_FREQ_CHECK,
|
||||
.verify = cpufreq_generic_frequency_table_verify,
|
||||
.target_index = dbx500_cpufreq_target,
|
||||
.get = cpufreq_generic_get,
|
||||
.init = dbx500_cpufreq_init,
|
||||
.exit = dbx500_cpufreq_exit,
|
||||
.ready = dbx500_cpufreq_ready,
|
||||
.name = "DBX500",
|
||||
.attr = cpufreq_generic_attr,
|
||||
};
|
||||
|
||||
static int dbx500_cpufreq_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct cpufreq_frequency_table *pos;
|
||||
|
||||
freq_table = dev_get_platdata(&pdev->dev);
|
||||
if (!freq_table) {
|
||||
pr_err("dbx500-cpufreq: Failed to fetch cpufreq table\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
armss_clk = clk_get(&pdev->dev, "armss");
|
||||
if (IS_ERR(armss_clk)) {
|
||||
pr_err("dbx500-cpufreq: Failed to get armss clk\n");
|
||||
return PTR_ERR(armss_clk);
|
||||
}
|
||||
|
||||
pr_info("dbx500-cpufreq: Available frequencies:\n");
|
||||
cpufreq_for_each_entry(pos, freq_table)
|
||||
pr_info(" %d Mhz\n", pos->frequency / 1000);
|
||||
|
||||
return cpufreq_register_driver(&dbx500_cpufreq_driver);
|
||||
}
|
||||
|
||||
static struct platform_driver dbx500_cpufreq_plat_driver = {
|
||||
.driver = {
|
||||
.name = "cpufreq-ux500",
|
||||
},
|
||||
.probe = dbx500_cpufreq_probe,
|
||||
};
|
||||
|
||||
static int __init dbx500_cpufreq_register(void)
|
||||
{
|
||||
return platform_driver_register(&dbx500_cpufreq_plat_driver);
|
||||
}
|
||||
device_initcall(dbx500_cpufreq_register);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("cpufreq driver for DBX500");
|
||||
@@ -165,9 +165,6 @@ static int elanfreq_cpu_init(struct cpufreq_policy *policy)
|
||||
if (pos->frequency > max_freq)
|
||||
pos->frequency = CPUFREQ_ENTRY_INVALID;
|
||||
|
||||
/* cpuinfo and default policy values */
|
||||
policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
|
||||
|
||||
return cpufreq_table_validate_and_show(policy, elanfreq_table);
|
||||
}
|
||||
|
||||
@@ -196,6 +193,7 @@ __setup("elanfreq=", elanfreq_setup);
|
||||
|
||||
static struct cpufreq_driver elanfreq_driver = {
|
||||
.get = elanfreq_get_cpu_frequency,
|
||||
.flags = CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
|
||||
.verify = cpufreq_generic_frequency_table_verify,
|
||||
.target_index = elanfreq_target,
|
||||
.init = elanfreq_cpu_init,
|
||||
|
||||
@@ -428,7 +428,6 @@ static int cpufreq_gx_cpu_init(struct cpufreq_policy *policy)
|
||||
policy->max = maxfreq;
|
||||
policy->cpuinfo.min_freq = maxfreq / max_duration;
|
||||
policy->cpuinfo.max_freq = maxfreq;
|
||||
policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -438,6 +437,7 @@ static int cpufreq_gx_cpu_init(struct cpufreq_policy *policy)
|
||||
* MediaGX/Geode GX initialize cpufreq driver
|
||||
*/
|
||||
static struct cpufreq_driver gx_suspmod_driver = {
|
||||
.flags = CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
|
||||
.get = gx_get_cpuspeed,
|
||||
.verify = cpufreq_gx_verify,
|
||||
.target = cpufreq_gx_target,
|
||||
|
||||
@@ -47,6 +47,7 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
|
||||
struct dev_pm_opp *opp;
|
||||
unsigned long freq_hz, volt, volt_old;
|
||||
unsigned int old_freq, new_freq;
|
||||
bool pll1_sys_temp_enabled = false;
|
||||
int ret;
|
||||
|
||||
new_freq = freq_table[index].frequency;
|
||||
@@ -124,6 +125,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
|
||||
if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
|
||||
clk_set_rate(pll1_sys_clk, new_freq * 1000);
|
||||
clk_set_parent(pll1_sw_clk, pll1_sys_clk);
|
||||
} else {
|
||||
/* pll1_sys needs to be enabled for divider rate change to work. */
|
||||
pll1_sys_temp_enabled = true;
|
||||
clk_prepare_enable(pll1_sys_clk);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -135,6 +140,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* PLL1 is only needed until after ARM-PODF is set. */
|
||||
if (pll1_sys_temp_enabled)
|
||||
clk_disable_unprepare(pll1_sys_clk);
|
||||
|
||||
/* scaling down? scale voltage after frequency */
|
||||
if (new_freq < old_freq) {
|
||||
ret = regulator_set_voltage_tol(arm_reg, volt, 0);
|
||||
|
||||
@@ -2132,7 +2132,6 @@ static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
|
||||
policy->cpuinfo.max_freq *= cpu->pstate.scaling;
|
||||
|
||||
intel_pstate_init_acpi_perf_limits(policy);
|
||||
cpumask_set_cpu(policy->cpu, policy->cpus);
|
||||
|
||||
policy->fast_switch_possible = true;
|
||||
|
||||
@@ -2146,7 +2145,6 @@ static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
|
||||
if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
|
||||
policy->policy = CPUFREQ_POLICY_PERFORMANCE;
|
||||
else
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user