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KVM: ia64: Add header files for kvm/ia64
kvm_minstate.h : Marcos about Min save routines. lapic.h: apic structure definition. vcpu.h : routions related to vcpu virtualization. vti.h : Some macros or routines for VT support on Itanium. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
This commit is contained in:
Xiantao Zhang
committed by
Avi Kivity
Avi Kivity
parent
b024b79322
commit
a4f500381a
273
arch/ia64/kvm/kvm_minstate.h
Normal file
273
arch/ia64/kvm/kvm_minstate.h
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@@ -0,0 +1,273 @@
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/*
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* kvm_minstate.h: min save macros
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* Copyright (c) 2007, Intel Corporation.
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*
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* Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
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* Xiantao Zhang (xiantao.zhang@intel.com)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include <asm/asmmacro.h>
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#include <asm/types.h>
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#include <asm/kregs.h>
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#include "asm-offsets.h"
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#define KVM_MINSTATE_START_SAVE_MIN \
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mov ar.rsc = 0;/* set enforced lazy mode, pl 0, little-endian, loadrs=0 */\
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;; \
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mov.m r28 = ar.rnat; \
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addl r22 = VMM_RBS_OFFSET,r1; /* compute base of RBS */ \
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;; \
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lfetch.fault.excl.nt1 [r22]; \
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addl r1 = IA64_STK_OFFSET-VMM_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
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mov r23 = ar.bspstore; /* save ar.bspstore */ \
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;; \
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mov ar.bspstore = r22; /* switch to kernel RBS */\
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;; \
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mov r18 = ar.bsp; \
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mov ar.rsc = 0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */
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#define KVM_MINSTATE_END_SAVE_MIN \
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bsw.1; /* switch back to bank 1 (must be last in insn group) */\
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;;
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#define PAL_VSA_SYNC_READ \
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/* begin to call pal vps sync_read */ \
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add r25 = VMM_VPD_BASE_OFFSET, r21; \
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adds r20 = VMM_VCPU_VSA_BASE_OFFSET, r21; /* entry point */ \
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;; \
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ld8 r25 = [r25]; /* read vpd base */ \
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ld8 r20 = [r20]; \
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;; \
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add r20 = PAL_VPS_SYNC_READ,r20; \
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;; \
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{ .mii; \
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nop 0x0; \
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mov r24 = ip; \
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mov b0 = r20; \
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;; \
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}; \
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{ .mmb; \
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add r24 = 0x20, r24; \
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nop 0x0; \
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br.cond.sptk b0; /* call the service */ \
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;; \
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};
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#define KVM_MINSTATE_GET_CURRENT(reg) mov reg=r21
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/*
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* KVM_DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
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* the minimum state necessary that allows us to turn psr.ic back
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* on.
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*
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* Assumed state upon entry:
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* psr.ic: off
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* r31: contains saved predicates (pr)
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*
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* Upon exit, the state is as follows:
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* psr.ic: off
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* r2 = points to &pt_regs.r16
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* r8 = contents of ar.ccv
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* r9 = contents of ar.csd
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* r10 = contents of ar.ssd
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* r11 = FPSR_DEFAULT
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* r12 = kernel sp (kernel virtual address)
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* r13 = points to current task_struct (kernel virtual address)
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* p15 = TRUE if psr.i is set in cr.ipsr
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* predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
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* preserved
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*
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* Note that psr.ic is NOT turned on by this macro. This is so that
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* we can pass interruption state as arguments to a handler.
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*/
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#define PT(f) (VMM_PT_REGS_##f##_OFFSET)
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#define KVM_DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \
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KVM_MINSTATE_GET_CURRENT(r16); /* M (or M;;I) */ \
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mov r27 = ar.rsc; /* M */ \
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mov r20 = r1; /* A */ \
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mov r25 = ar.unat; /* M */ \
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mov r29 = cr.ipsr; /* M */ \
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mov r26 = ar.pfs; /* I */ \
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mov r18 = cr.isr; \
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COVER; /* B;; (or nothing) */ \
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;; \
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tbit.z p0,p15 = r29,IA64_PSR_I_BIT; \
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mov r1 = r16; \
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/* mov r21=r16; */ \
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/* switch from user to kernel RBS: */ \
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;; \
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invala; /* M */ \
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SAVE_IFS; \
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;; \
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KVM_MINSTATE_START_SAVE_MIN \
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adds r17 = 2*L1_CACHE_BYTES,r1;/* cache-line size */ \
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adds r16 = PT(CR_IPSR),r1; \
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;; \
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lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \
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st8 [r16] = r29; /* save cr.ipsr */ \
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;; \
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lfetch.fault.excl.nt1 [r17]; \
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tbit.nz p15,p0 = r29,IA64_PSR_I_BIT; \
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mov r29 = b0 \
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;; \
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adds r16 = PT(R8),r1; /* initialize first base pointer */\
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adds r17 = PT(R9),r1; /* initialize second base pointer */\
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;; \
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.mem.offset 0,0; st8.spill [r16] = r8,16; \
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.mem.offset 8,0; st8.spill [r17] = r9,16; \
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;; \
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.mem.offset 0,0; st8.spill [r16] = r10,24; \
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.mem.offset 8,0; st8.spill [r17] = r11,24; \
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;; \
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mov r9 = cr.iip; /* M */ \
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mov r10 = ar.fpsr; /* M */ \
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;; \
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st8 [r16] = r9,16; /* save cr.iip */ \
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st8 [r17] = r30,16; /* save cr.ifs */ \
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sub r18 = r18,r22; /* r18=RSE.ndirty*8 */ \
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;; \
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st8 [r16] = r25,16; /* save ar.unat */ \
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st8 [r17] = r26,16; /* save ar.pfs */ \
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shl r18 = r18,16; /* calu ar.rsc used for "loadrs" */\
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;; \
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st8 [r16] = r27,16; /* save ar.rsc */ \
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st8 [r17] = r28,16; /* save ar.rnat */ \
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;; /* avoid RAW on r16 & r17 */ \
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st8 [r16] = r23,16; /* save ar.bspstore */ \
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st8 [r17] = r31,16; /* save predicates */ \
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;; \
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st8 [r16] = r29,16; /* save b0 */ \
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st8 [r17] = r18,16; /* save ar.rsc value for "loadrs" */\
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;; \
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.mem.offset 0,0; st8.spill [r16] = r20,16;/* save original r1 */ \
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.mem.offset 8,0; st8.spill [r17] = r12,16; \
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adds r12 = -16,r1; /* switch to kernel memory stack */ \
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;; \
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.mem.offset 0,0; st8.spill [r16] = r13,16; \
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.mem.offset 8,0; st8.spill [r17] = r10,16; /* save ar.fpsr */\
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mov r13 = r21; /* establish `current' */ \
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;; \
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.mem.offset 0,0; st8.spill [r16] = r15,16; \
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.mem.offset 8,0; st8.spill [r17] = r14,16; \
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;; \
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.mem.offset 0,0; st8.spill [r16] = r2,16; \
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.mem.offset 8,0; st8.spill [r17] = r3,16; \
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adds r2 = VMM_PT_REGS_R16_OFFSET,r1; \
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;; \
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adds r16 = VMM_VCPU_IIPA_OFFSET,r13; \
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adds r17 = VMM_VCPU_ISR_OFFSET,r13; \
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mov r26 = cr.iipa; \
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mov r27 = cr.isr; \
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;; \
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st8 [r16] = r26; \
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st8 [r17] = r27; \
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;; \
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EXTRA; \
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mov r8 = ar.ccv; \
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mov r9 = ar.csd; \
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mov r10 = ar.ssd; \
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movl r11 = FPSR_DEFAULT; /* L-unit */ \
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adds r17 = VMM_VCPU_GP_OFFSET,r13; \
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;; \
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ld8 r1 = [r17];/* establish kernel global pointer */ \
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;; \
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PAL_VSA_SYNC_READ \
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KVM_MINSTATE_END_SAVE_MIN
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/*
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* SAVE_REST saves the remainder of pt_regs (with psr.ic on).
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*
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* Assumed state upon entry:
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* psr.ic: on
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* r2: points to &pt_regs.f6
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* r3: points to &pt_regs.f7
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* r8: contents of ar.ccv
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* r9: contents of ar.csd
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* r10: contents of ar.ssd
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* r11: FPSR_DEFAULT
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*
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* Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
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*/
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#define KVM_SAVE_REST \
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.mem.offset 0,0; st8.spill [r2] = r16,16; \
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.mem.offset 8,0; st8.spill [r3] = r17,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r18,16; \
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.mem.offset 8,0; st8.spill [r3] = r19,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r20,16; \
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.mem.offset 8,0; st8.spill [r3] = r21,16; \
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mov r18=b6; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r22,16; \
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.mem.offset 8,0; st8.spill [r3] = r23,16; \
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mov r19 = b7; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r24,16; \
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.mem.offset 8,0; st8.spill [r3] = r25,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r26,16; \
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.mem.offset 8,0; st8.spill [r3] = r27,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r28,16; \
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.mem.offset 8,0; st8.spill [r3] = r29,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r30,16; \
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.mem.offset 8,0; st8.spill [r3] = r31,32; \
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;; \
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mov ar.fpsr = r11; \
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st8 [r2] = r8,8; \
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adds r24 = PT(B6)-PT(F7),r3; \
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adds r25 = PT(B7)-PT(F7),r3; \
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;; \
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st8 [r24] = r18,16; /* b6 */ \
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st8 [r25] = r19,16; /* b7 */ \
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adds r2 = PT(R4)-PT(F6),r2; \
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adds r3 = PT(R5)-PT(F7),r3; \
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;; \
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st8 [r24] = r9; /* ar.csd */ \
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st8 [r25] = r10; /* ar.ssd */ \
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;; \
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mov r18 = ar.unat; \
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adds r19 = PT(EML_UNAT)-PT(R4),r2; \
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;; \
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st8 [r19] = r18; /* eml_unat */ \
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#define KVM_SAVE_EXTRA \
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.mem.offset 0,0; st8.spill [r2] = r4,16; \
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.mem.offset 8,0; st8.spill [r3] = r5,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r6,16; \
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.mem.offset 8,0; st8.spill [r3] = r7; \
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;; \
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mov r26 = ar.unat; \
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;; \
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st8 [r2] = r26;/* eml_unat */ \
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#define KVM_SAVE_MIN_WITH_COVER KVM_DO_SAVE_MIN(cover, mov r30 = cr.ifs,)
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#define KVM_SAVE_MIN_WITH_COVER_R19 KVM_DO_SAVE_MIN(cover, mov r30 = cr.ifs, mov r15 = r19)
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#define KVM_SAVE_MIN KVM_DO_SAVE_MIN( , mov r30 = r0, )
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25
arch/ia64/kvm/lapic.h
Normal file
25
arch/ia64/kvm/lapic.h
Normal file
@@ -0,0 +1,25 @@
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#ifndef __KVM_IA64_LAPIC_H
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#define __KVM_IA64_LAPIC_H
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#include <linux/kvm_host.h>
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/*
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* vlsapic
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*/
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struct kvm_lapic{
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struct kvm_vcpu *vcpu;
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uint64_t insvc[4];
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uint64_t vhpi;
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uint8_t xtp;
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uint8_t pal_init_pending;
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uint8_t pad[2];
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};
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int kvm_create_lapic(struct kvm_vcpu *vcpu);
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void kvm_free_lapic(struct kvm_vcpu *vcpu);
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int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
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int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
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int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig);
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#endif
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93
arch/ia64/kvm/misc.h
Normal file
93
arch/ia64/kvm/misc.h
Normal file
@@ -0,0 +1,93 @@
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#ifndef __KVM_IA64_MISC_H
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#define __KVM_IA64_MISC_H
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#include <linux/kvm_host.h>
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/*
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* misc.h
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* Copyright (C) 2007, Intel Corporation.
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* Xiantao Zhang (xiantao.zhang@intel.com)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
|
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* version 2, as published by the Free Software Foundation.
|
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
|
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
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*
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*/
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/*
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*Return p2m base address at host side!
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*/
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static inline uint64_t *kvm_host_get_pmt(struct kvm *kvm)
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{
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return (uint64_t *)(kvm->arch.vm_base + KVM_P2M_OFS);
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}
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static inline void kvm_set_pmt_entry(struct kvm *kvm, gfn_t gfn,
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u64 paddr, u64 mem_flags)
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{
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uint64_t *pmt_base = kvm_host_get_pmt(kvm);
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unsigned long pte;
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pte = PAGE_ALIGN(paddr) | mem_flags;
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pmt_base[gfn] = pte;
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}
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/*Function for translating host address to guest address*/
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static inline void *to_guest(struct kvm *kvm, void *addr)
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{
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return (void *)((unsigned long)(addr) - kvm->arch.vm_base +
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KVM_VM_DATA_BASE);
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}
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/*Function for translating guest address to host address*/
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static inline void *to_host(struct kvm *kvm, void *addr)
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{
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return (void *)((unsigned long)addr - KVM_VM_DATA_BASE
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+ kvm->arch.vm_base);
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}
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/* Get host context of the vcpu */
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static inline union context *kvm_get_host_context(struct kvm_vcpu *vcpu)
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{
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union context *ctx = &vcpu->arch.host;
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return to_guest(vcpu->kvm, ctx);
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}
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/* Get guest context of the vcpu */
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static inline union context *kvm_get_guest_context(struct kvm_vcpu *vcpu)
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{
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union context *ctx = &vcpu->arch.guest;
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return to_guest(vcpu->kvm, ctx);
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}
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/* kvm get exit data from gvmm! */
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static inline struct exit_ctl_data *kvm_get_exit_data(struct kvm_vcpu *vcpu)
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{
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return &vcpu->arch.exit_data;
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}
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/*kvm get vcpu ioreq for kvm module!*/
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static inline struct kvm_mmio_req *kvm_get_vcpu_ioreq(struct kvm_vcpu *vcpu)
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{
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struct exit_ctl_data *p_ctl_data;
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if (vcpu) {
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p_ctl_data = kvm_get_exit_data(vcpu);
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if (p_ctl_data->exit_reason == EXIT_REASON_MMIO_INSTRUCTION)
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return &p_ctl_data->u.ioreq;
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}
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return NULL;
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}
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#endif
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740
arch/ia64/kvm/vcpu.h
Normal file
740
arch/ia64/kvm/vcpu.h
Normal file
File diff suppressed because it is too large
Load Diff
290
arch/ia64/kvm/vti.h
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290
arch/ia64/kvm/vti.h
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/*
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* vti.h: prototype for generial vt related interface
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* Copyright (c) 2004, Intel Corporation.
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*
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* Xuefei Xu (Anthony Xu) (anthony.xu@intel.com)
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* Fred Yang (fred.yang@intel.com)
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* Kun Tian (Kevin Tian) (kevin.tian@intel.com)
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*
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* Copyright (c) 2007, Intel Corporation.
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* Zhang xiantao <xiantao.zhang@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*/
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#ifndef _KVM_VT_I_H
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#define _KVM_VT_I_H
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#ifndef __ASSEMBLY__
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#include <asm/page.h>
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#include <linux/kvm_host.h>
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/* define itr.i and itr.d in ia64_itr function */
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#define ITR 0x01
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#define DTR 0x02
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#define IaDTR 0x03
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#define IA64_TR_VMM 6 /*itr6, dtr6 : maps vmm code, vmbuffer*/
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#define IA64_TR_VM_DATA 7 /*dtr7 : maps current vm data*/
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#define RR6 (6UL<<61)
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#define RR7 (7UL<<61)
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/* config_options in pal_vp_init_env */
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#define VP_INITIALIZE 1UL
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#define VP_FR_PMC 1UL<<1
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#define VP_OPCODE 1UL<<8
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#define VP_CAUSE 1UL<<9
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#define VP_FW_ACC 1UL<<63
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/* init vp env with initializing vm_buffer */
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#define VP_INIT_ENV_INITALIZE (VP_INITIALIZE | VP_FR_PMC |\
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VP_OPCODE | VP_CAUSE | VP_FW_ACC)
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/* init vp env without initializing vm_buffer */
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#define VP_INIT_ENV VP_FR_PMC | VP_OPCODE | VP_CAUSE | VP_FW_ACC
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#define PAL_VP_CREATE 265
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/* Stacked Virt. Initializes a new VPD for the operation of
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* a new virtual processor in the virtual environment.
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*/
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#define PAL_VP_ENV_INFO 266
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/*Stacked Virt. Returns the parameters needed to enter a virtual environment.*/
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#define PAL_VP_EXIT_ENV 267
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/*Stacked Virt. Allows a logical processor to exit a virtual environment.*/
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#define PAL_VP_INIT_ENV 268
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/*Stacked Virt. Allows a logical processor to enter a virtual environment.*/
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#define PAL_VP_REGISTER 269
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/*Stacked Virt. Register a different host IVT for the virtual processor.*/
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#define PAL_VP_RESUME 270
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/* Renamed from PAL_VP_RESUME */
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#define PAL_VP_RESTORE 270
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/*Stacked Virt. Resumes virtual processor operation on the logical processor.*/
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#define PAL_VP_SUSPEND 271
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/* Renamed from PAL_VP_SUSPEND */
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#define PAL_VP_SAVE 271
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/* Stacked Virt. Suspends operation for the specified virtual processor on
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* the logical processor.
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*/
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#define PAL_VP_TERMINATE 272
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/* Stacked Virt. Terminates operation for the specified virtual processor.*/
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union vac {
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unsigned long value;
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struct {
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int a_int:1;
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int a_from_int_cr:1;
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int a_to_int_cr:1;
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int a_from_psr:1;
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int a_from_cpuid:1;
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int a_cover:1;
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int a_bsw:1;
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long reserved:57;
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};
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};
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union vdc {
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unsigned long value;
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struct {
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int d_vmsw:1;
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int d_extint:1;
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int d_ibr_dbr:1;
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int d_pmc:1;
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int d_to_pmd:1;
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int d_itm:1;
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long reserved:58;
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};
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};
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struct vpd {
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union vac vac;
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union vdc vdc;
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unsigned long virt_env_vaddr;
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unsigned long reserved1[29];
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unsigned long vhpi;
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unsigned long reserved2[95];
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unsigned long vgr[16];
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unsigned long vbgr[16];
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unsigned long vnat;
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unsigned long vbnat;
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unsigned long vcpuid[5];
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unsigned long reserved3[11];
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unsigned long vpsr;
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unsigned long vpr;
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unsigned long reserved4[76];
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union {
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unsigned long vcr[128];
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struct {
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unsigned long dcr;
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unsigned long itm;
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unsigned long iva;
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unsigned long rsv1[5];
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unsigned long pta;
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unsigned long rsv2[7];
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unsigned long ipsr;
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unsigned long isr;
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unsigned long rsv3;
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unsigned long iip;
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unsigned long ifa;
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unsigned long itir;
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unsigned long iipa;
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unsigned long ifs;
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unsigned long iim;
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unsigned long iha;
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unsigned long rsv4[38];
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unsigned long lid;
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unsigned long ivr;
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unsigned long tpr;
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unsigned long eoi;
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unsigned long irr[4];
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unsigned long itv;
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unsigned long pmv;
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unsigned long cmcv;
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unsigned long rsv5[5];
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unsigned long lrr0;
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unsigned long lrr1;
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unsigned long rsv6[46];
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};
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};
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unsigned long reserved5[128];
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unsigned long reserved6[3456];
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unsigned long vmm_avail[128];
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unsigned long reserved7[4096];
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};
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#define PAL_PROC_VM_BIT (1UL << 40)
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#define PAL_PROC_VMSW_BIT (1UL << 54)
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static inline s64 ia64_pal_vp_env_info(u64 *buffer_size,
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u64 *vp_env_info)
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{
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struct ia64_pal_retval iprv;
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PAL_CALL_STK(iprv, PAL_VP_ENV_INFO, 0, 0, 0);
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*buffer_size = iprv.v0;
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*vp_env_info = iprv.v1;
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return iprv.status;
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}
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static inline s64 ia64_pal_vp_exit_env(u64 iva)
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{
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struct ia64_pal_retval iprv;
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PAL_CALL_STK(iprv, PAL_VP_EXIT_ENV, (u64)iva, 0, 0);
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return iprv.status;
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}
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static inline s64 ia64_pal_vp_init_env(u64 config_options, u64 pbase_addr,
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u64 vbase_addr, u64 *vsa_base)
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{
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struct ia64_pal_retval iprv;
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PAL_CALL_STK(iprv, PAL_VP_INIT_ENV, config_options, pbase_addr,
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vbase_addr);
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*vsa_base = iprv.v0;
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return iprv.status;
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}
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static inline s64 ia64_pal_vp_restore(u64 *vpd, u64 pal_proc_vector)
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{
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struct ia64_pal_retval iprv;
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PAL_CALL_STK(iprv, PAL_VP_RESTORE, (u64)vpd, pal_proc_vector, 0);
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return iprv.status;
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}
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static inline s64 ia64_pal_vp_save(u64 *vpd, u64 pal_proc_vector)
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{
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struct ia64_pal_retval iprv;
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PAL_CALL_STK(iprv, PAL_VP_SAVE, (u64)vpd, pal_proc_vector, 0);
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return iprv.status;
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}
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#endif
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/*VPD field offset*/
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#define VPD_VAC_START_OFFSET 0
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#define VPD_VDC_START_OFFSET 8
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#define VPD_VHPI_START_OFFSET 256
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#define VPD_VGR_START_OFFSET 1024
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#define VPD_VBGR_START_OFFSET 1152
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#define VPD_VNAT_START_OFFSET 1280
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#define VPD_VBNAT_START_OFFSET 1288
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#define VPD_VCPUID_START_OFFSET 1296
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#define VPD_VPSR_START_OFFSET 1424
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#define VPD_VPR_START_OFFSET 1432
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#define VPD_VRSE_CFLE_START_OFFSET 1440
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#define VPD_VCR_START_OFFSET 2048
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#define VPD_VTPR_START_OFFSET 2576
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#define VPD_VRR_START_OFFSET 3072
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#define VPD_VMM_VAIL_START_OFFSET 31744
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/*Virtualization faults*/
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#define EVENT_MOV_TO_AR 1
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#define EVENT_MOV_TO_AR_IMM 2
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#define EVENT_MOV_FROM_AR 3
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#define EVENT_MOV_TO_CR 4
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#define EVENT_MOV_FROM_CR 5
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#define EVENT_MOV_TO_PSR 6
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#define EVENT_MOV_FROM_PSR 7
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#define EVENT_ITC_D 8
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#define EVENT_ITC_I 9
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#define EVENT_MOV_TO_RR 10
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#define EVENT_MOV_TO_DBR 11
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#define EVENT_MOV_TO_IBR 12
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#define EVENT_MOV_TO_PKR 13
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#define EVENT_MOV_TO_PMC 14
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#define EVENT_MOV_TO_PMD 15
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#define EVENT_ITR_D 16
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#define EVENT_ITR_I 17
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#define EVENT_MOV_FROM_RR 18
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#define EVENT_MOV_FROM_DBR 19
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#define EVENT_MOV_FROM_IBR 20
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#define EVENT_MOV_FROM_PKR 21
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#define EVENT_MOV_FROM_PMC 22
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#define EVENT_MOV_FROM_CPUID 23
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#define EVENT_SSM 24
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#define EVENT_RSM 25
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#define EVENT_PTC_L 26
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#define EVENT_PTC_G 27
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#define EVENT_PTC_GA 28
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#define EVENT_PTR_D 29
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#define EVENT_PTR_I 30
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#define EVENT_THASH 31
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#define EVENT_TTAG 32
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#define EVENT_TPA 33
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#define EVENT_TAK 34
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#define EVENT_PTC_E 35
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#define EVENT_COVER 36
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#define EVENT_RFI 37
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#define EVENT_BSW_0 38
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#define EVENT_BSW_1 39
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#define EVENT_VMSW 40
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/**PAL virtual services offsets */
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#define PAL_VPS_RESUME_NORMAL 0x0000
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#define PAL_VPS_RESUME_HANDLER 0x0400
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#define PAL_VPS_SYNC_READ 0x0800
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#define PAL_VPS_SYNC_WRITE 0x0c00
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#define PAL_VPS_SET_PENDING_INTERRUPT 0x1000
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#define PAL_VPS_THASH 0x1400
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#define PAL_VPS_TTAG 0x1800
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#define PAL_VPS_RESTORE 0x1c00
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#define PAL_VPS_SAVE 0x2000
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#endif/* _VT_I_H*/
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Reference in New Issue
Block a user