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Merge tag 'pinctrl-v6.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Browse Source 
Pull pin control updates from Linus Walleij:
 "Core changes:

   - Add support for "input-schmitt-microvolt" property, as used in the
     Sophgo SoC

  New drivers:

   - Mobileye EyeQ5 pin controller, I think this is an automotive SoC

   - Rockchip rk3576 pin control support

   - Sophgo CV1800 series pin controllers: CV1800B, CV1812H and SG2000

  Improvements:

   - Gradual improvements to Renesas, Samsung, Qualcomm, Nuvoton and a
     few other drivers"

* tag 'pinctrl-v6.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (67 commits)
  pinctrl: intel: Constify struct intel_pinctrl parameter
  pinctrl: Remove redundant null pointer checks in pinctrl_remove_device_debugfs()
  pinctrl: baytrail: Drop duplicate return statement
  pinctrl: intel: Inline intel_gpio_community_irq_handler()
  dt-bindings: pinctrl: qcom: add missing type to GPIO hogs
  pinctrl: madera: Simplify with dev_err_probe()
  pinctrl: k210: Use devm_clk_get_enabled() helpers
  pinctrl: Join split messages and remove double whitespace
  pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call outside of switch cases
  pinctrl: renesas: rzg2l: Introduce single macro for digital noise filter configuration
  pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more suitable API
  pinctrl: mvebu: Fix devinit_dove_pinctrl_probe function
  pinctrl: sunxi: Use devm_clk_get_enabled() helpers
  pinctrl: sophgo: cv18xx: fix missed __iomem type identifier
  pinctrl: stmfx: Use string_choices API instead of ternary operator
  pinctrl: nomadik: Use kmemdup_array instead of kmemdup for multiple allocation
  pinctrl: intel: Introduce for_each_intel_gpio_group() helper et al.
  pinctrl: intel: Constify intel_get_community() returned object
  pinctrl: intel: Implement high impedance support
  pinctrl: intel: Add __intel_gpio_get_direction() helper
  ...
This commit is contained in:
Linus Torvalds
2024-09-23 13:15:23 -07:00
parent 5f153b6330 264c13114b
commit 962ad08780
84 changed files with 6002 additions and 1275 deletions
Download Patch File Download Diff File Expand all files Collapse all files

242
Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml
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@@ -1,242 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mobileye,eyeq5-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mobileye EyeQ5 pin controller
description: >
The EyeQ5 pin controller handles the two pin banks of the system. It belongs
to a system-controller block called OLB.
Pin control is about bias (pull-down, pull-up), drive strength and muxing. Pin
muxing supports two functions for each pin: first is GPIO, second is
pin-dependent.
Pins and groups are bijective.
maintainers:
- Grégory Clement <gregory.clement@bootlin.com>
- Théo Lebrun <theo.lebrun@bootlin.com>
- Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
$ref: pinctrl.yaml#
properties:
compatible:
enum:
- mobileye,eyeq5-pinctrl
reg:
maxItems: 1
patternProperties:
"-pins?$":
type: object
description: Pin muxing configuration.
$ref: pinmux-node.yaml#
additionalProperties: false
properties:
pins: true
function:
enum: [gpio,
# Bank A
timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0,
spi1, refclk0,
# Bank B
timer3, timer4, timer6, uart2, can2, spi2, spi3, mclk0]
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength: true
required:
- pins
- function
allOf:
- if:
properties:
function:
const: gpio
then:
properties:
pins:
items: # PA0 - PA28, PB0 - PB22
pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$'
- if:
properties:
function:
const: timer0
then:
properties:
pins:
items:
enum: [PA0, PA1]
- if:
properties:
function:
const: timer1
then:
properties:
pins:
items:
enum: [PA2, PA3]
- if:
properties:
function:
const: timer2
then:
properties:
pins:
items:
enum: [PA4, PA5]
- if:
properties:
function:
const: timer5
then:
properties:
pins:
items:
enum: [PA6, PA7, PA8, PA9]
- if:
properties:
function:
const: uart0
then:
properties:
pins:
items:
enum: [PA10, PA11]
- if:
properties:
function:
const: uart1
then:
properties:
pins:
items:
enum: [PA12, PA13]
- if:
properties:
function:
const: can0
then:
properties:
pins:
items:
enum: [PA14, PA15]
- if:
properties:
function:
const: can1
then:
properties:
pins:
items:
enum: [PA16, PA17]
- if:
properties:
function:
const: spi0
then:
properties:
pins:
items:
enum: [PA18, PA19, PA20, PA21, PA22]
- if:
properties:
function:
const: spi1
then:
properties:
pins:
items:
enum: [PA23, PA24, PA25, PA26, PA27]
- if:
properties:
function:
const: refclk0
then:
properties:
pins:
items:
enum: [PA28]
- if:
properties:
function:
const: timer3
then:
properties:
pins:
items:
enum: [PB0, PB1]
- if:
properties:
function:
const: timer4
then:
properties:
pins:
items:
enum: [PB2, PB3]
- if:
properties:
function:
const: timer6
then:
properties:
pins:
items:
enum: [PB4, PB5, PB6, PB7]
- if:
properties:
function:
const: uart2
then:
properties:
pins:
items:
enum: [PB8, PB9]
- if:
properties:
function:
const: can2
then:
properties:
pins:
items:
enum: [PB10, PB11]
- if:
properties:
function:
const: spi2
then:
properties:
pins:
items:
enum: [PB12, PB13, PB14, PB15, PB16]
- if:
properties:
function:
const: spi3
then:
properties:
pins:
items:
enum: [PB17, PB18, PB19, PB20, PB21]
- if:
properties:
function:
const: mclk0
then:
properties:
pins:
items:
enum: [PB22]
required:
- compatible
- reg
additionalProperties: false

70
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
View File

@@ -71,51 +71,49 @@ patternProperties:
One or more groups of pins to mux to a certain function
items:
enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,
smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,
spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,
wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,
hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,
bu4b, bu5, bu5b, bu6, gpo187 ]
smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15,
smb16, smb17, smb18, smb19, smb20, smb21, smb22, smb23,
smb23b, smb4d, smb14, smb5, smb4, smb3, spi0cs1, spi0cs2,
spi0cs3, spi1cs0, spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c,
smb3b, bmcuart0a, uart1, jtag2, bmcuart1, uart2, sg1mdio,
bmcuart0b, r1err, r1md, r1oen, r2oen, rmii3, r3oen, smb3d,
fanin0, fanin1, fanin2, fanin3, fanin4, fanin5, fanin6,
fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13,
fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md,
r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b, smb1c,
smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4, pwm5,
pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp, mmccd,
mmcrst, clkout, serirq, scipme, smi, smb6, smb6b, smb6c,
smb6d, smb7, smb7b, smb7c, smb7d, spi1, faninx, r1, spi3,
spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c,
smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13,
spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b, bu6, gpo187 ]
function:
description:
The function that a group of pins is muxed to
enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, smb5b,
smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15, smb16,
smb17, smb18, smb19, smb20, smb21, smb22, smb23, smb23b, smb4d,
smb14, smb5, smb4, smb3, spi0cs1, spi0cs2, spi0cs3, spi1cs0,
spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a,
uart1, jtag2, bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md,
r1oen, r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2,
fanin3, fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,
smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,
spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,
wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,
hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,
bu4b, bu5, bu5b, bu6, gpo187 ]
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, scipme, smi,
smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c, smb7d, spi1,
faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi,
smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2,
smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2,
hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b,
bu6, gpo187 ]
dependencies:
groups: [ function ]

3
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
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@@ -96,6 +96,9 @@ properties:
type: boolean
description: disable schmitt-trigger mode
input-schmitt-microvolt:
description: threshold strength for schmitt-trigger
input-debounce:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: Takes the debounce time in usec as argument or 0 to disable

95
Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
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@@ -1,95 +0,0 @@
Qualcomm APQ8064 TLMM block
Required properties:
- compatible: "qcom,apq8064-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt
Optional properties:
- gpio-reserved-ranges: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength,
output-low, output-high.
Non-empty subnodes must specify the 'pins' property.
Valid values for pins are:
gpio0-gpio89
Valid values for function are:
cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, gp_clk_0b, gp_clk_1a,
gp_clk_1b, gp_clk_2a, gp_clk_2b, gpio, gsbi1, gsbi2, gsbi3, gsbi4,
gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold
Example:
msmgpio: pinctrl@800000 {
compatible = "qcom,apq8064-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 16 0x4>;
pinctrl-names = "default";
pinctrl-0 = <&gsbi5_uart_default>;
gpio-ranges = <&msmgpio 0 0 90>;
gsbi5_uart_default: gsbi5_uart_default {
mux {
pins = "gpio51", "gpio52";
function = "gsbi5";
};
tx {
pins = "gpio51";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio52";
drive-strength = <2>;
bias-pull-up;
};
};
};

110
Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.yaml Normal file
View File

@@ -0,0 +1,110 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,apq8064-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. APQ8064 TLMM block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Top Level Mode Multiplexer pin controller in Qualcomm APQ8064 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,apq8064-pinctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges: true
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-apq8064-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-apq8064-tlmm-state"
additionalProperties: false
$defs:
qcom-apq8064-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-8][0-9])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc3_clk, sdc3_cmd, sdc3_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a,
gp_clk_0b, gp_clk_1a, gp_clk_1b, gp_clk_2a, gp_clk_2b,
gpio, gsbi1, gsbi2, gsbi3, gsbi4, gsbi4_cam_i2c,
gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3,
gsbi6, gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3,
gsbi7, gsbi7_spi_cs1, gsbi7_spi_cs2, gsbi7_spi_cs3,
gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, riva_wlan,
sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic,
ps_hold ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@800000 {
compatible = "qcom,apq8064-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 90>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
uart-state {
rx-pins {
pins = "gpio52";
function = "gsbi5";
bias-pull-up;
};
tx-pins {
pins = "gpio51";
function = "gsbi5";
bias-disable;
};
};
};

188
Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt
View File

@@ -1,188 +0,0 @@
Qualcomm APQ8084 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
MSM8960 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,apq8084-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio0-gpio146,
sdc1_clk,
sdc1_cmd,
sdc1_data
sdc2_clk,
sdc2_cmd,
sdc2_data
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3,
blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8,
blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2,
cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i
gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio,
hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic,
ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst,
pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1,
tsif2, uim, uim_batt_alarm
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@fd510000 {
compatible = "qcom,apq8084-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 147>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
uart2: uart2-default {
mux {
pins = "gpio4", "gpio5";
function = "blsp_uart2";
};
tx {
pins = "gpio4";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio5";
drive-strength = <2>;
bias-pull-up;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,apq8084-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. APQ8084 TLMM block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Top Level Mode Multiplexer pin controller in Qualcomm APQ8084 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,apq8084-pinctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges: true
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-apq8084-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-apq8084-tlmm-state"
additionalProperties: false
$defs:
qcom-apq8084-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-6])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3,
blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,
blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6,
blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2,
blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6,
blsp_uart7, blsp_uart8, blsp_uart9, blsp_uart10,
blsp_uart11, blsp_uart12, blsp_uim1, blsp_uim2,
blsp_uim3, blsp_uim4, blsp_uim5, blsp_uim6, blsp_uim7,
blsp_uim8, blsp_uim9, blsp_uim10, blsp_uim11,
blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3,
cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
cci_timer0, cci_timer1, cci_timer2, cci_timer3,
cci_timer4, edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3,
gcc_obt, gcc_vtt, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2,
gp0_clk, gp1_clk, gpio, hdmi_cec, hdmi_ddc, hdmi_dtest,
hdmi_hpd, hdmi_rcv, hsic, ldo_en, ldo_update,
mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst, pci_e1,
pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s,
tsif1, tsif2, uim, uim_batt_alarm ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@fd510000 {
compatible = "qcom,apq8084-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 147>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
uart-state {
rx-pins {
pins = "gpio5";
function = "blsp_uart2";
bias-pull-up;
};
tx-pins {
pins = "gpio4";
function = "blsp_uart2";
bias-disable;
};
};
};

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Qualcomm Atheros IPQ4019 TLMM block
This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
Required properties:
- compatible: "qcom,ipq4019-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt
Optional properties:
- gpio-reserved-ranges: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,
drive-strength.
Non-empty subnodes must specify the 'pins' property.
Note that not all properties are valid for all pins.
Valid values for qcom,pins are:
gpio0-gpio99
Supports mux, bias and drive-strength
Valid values for qcom,function are:
aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0,
blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11,
mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
smart2, smart3, tm, wifi0, wifi1
Example:
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq4019-pinctrl";
reg = <0x1000000 0x300000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 100>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq4019-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. IPQ4019 TLMM block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Top Level Mode Multiplexer pin controller in Qualcomm IPQ4019 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,ipq4019-pinctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges: true
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-ipq4019-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-ipq4019-tlmm-state"
additionalProperties: false
"-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog
$defs:
qcom-ipq4019-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|[1-9][0-9])$"
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0,
blsp_spi1, blsp_uart0, blsp_uart1, chip_rst, gpio,
i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
jtag, led0, led1, led2, led3, led4, led5, led6, led7,
led8, led9, led10, led11, mdc, mdio, pcie, pmu,
prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
smart2, smart3, tm, wifi0, wifi1 ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq4019-pinctrl";
reg = <0x01000000 0x300000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 100>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
uart-state {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};

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Qualcomm IPQ8064 TLMM block
Required properties:
- compatible: "qcom,ipq8064-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt
Optional properties:
- gpio-reserved-ranges: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength,
output-low, output-high.
Non-empty subnodes must specify the 'pins' property.
Valid values for qcom,pins are:
gpio0-gpio68
Supports mux, bias, and drive-strength
sdc3_clk, sdc3_cmd, sdc3_data
Supports bias and drive-strength
Valid values for function are:
mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold
Example:
pinmux: pinctrl@800000 {
compatible = "qcom,ipq8064-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinmux 0 0 69>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 32 0x4>;
pinctrl-names = "default";
pinctrl-0 = <&gsbi5_uart_default>;
gsbi5_uart_default: gsbi5_uart_default {
mux {
pins = "gpio18", "gpio19";
function = "gsbi5";
};
tx {
pins = "gpio18";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio19";
drive-strength = <2>;
bias-pull-up;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8064-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. IPQ8064 TLMM block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Top Level Mode Multiplexer pin controller in Qualcomm IPQ8064 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,ipq8064-pinctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges: true
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-ipq8064-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-ipq8064-tlmm-state"
additionalProperties: false
$defs:
qcom-ipq8064-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-5][0-9]|6[0-8])$"
- enum: [ sdc3_clk, sdc3_cmd, sdc3_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@800000 {
compatible = "qcom,ipq8064-pinctrl";
reg = <0x00800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 69>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
uart-state {
rx-pins {
pins = "gpio19";
function = "gsbi5";
bias-pull-up;
};
tx-pins {
pins = "gpio18";
function = "gsbi5";
bias-disable;
};
};
};

1
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@@ -425,6 +425,7 @@ patternProperties:
additionalProperties: false
"-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog

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@@ -43,6 +43,7 @@ patternProperties:
additionalProperties: false
"-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog

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Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
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@@ -25,6 +25,7 @@ properties:
- renesas,pfc-r8a7745 # RZ/G1E
- renesas,pfc-r8a77470 # RZ/G1C
- renesas,pfc-r8a774a1 # RZ/G2M
- renesas,pfc-r8a774a3 # RZ/G2M v3.0
- renesas,pfc-r8a774b1 # RZ/G2N
- renesas,pfc-r8a774c0 # RZ/G2E
- renesas,pfc-r8a774e1 # RZ/G2H

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Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
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@@ -45,6 +45,7 @@ properties:
- rockchip,rk3368-pinctrl
- rockchip,rk3399-pinctrl
- rockchip,rk3568-pinctrl
- rockchip,rk3576-pinctrl
- rockchip,rk3588-pinctrl
- rockchip,rv1108-pinctrl
- rockchip,rv1126-pinctrl

122
Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml Normal file
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@@ -0,0 +1,122 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/sophgo,cv1800-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo CV1800 Pin Controller
maintainers:
- Inochi Amaoto <inochiama@outlook.com>
properties:
compatible:
enum:
- sophgo,cv1800b-pinctrl
- sophgo,cv1812h-pinctrl
- sophgo,sg2000-pinctrl
- sophgo,sg2002-pinctrl
reg:
items:
- description: pinctrl for system domain
- description: pinctrl for rtc domain
reg-names:
items:
- const: sys
- const: rtc
resets:
maxItems: 1
patternProperties:
'-cfg$':
type: object
description:
A pinctrl node should contain at least one subnode representing the
pinctrl groups available on the machine.
additionalProperties: false
patternProperties:
'-pins$':
type: object
description: |
Each subnode will list the pins it needs, and how they should
be configured, with regard to muxer configuration, bias, input
enable/disable, input schmitt trigger, slew-rate, drive strength
and bus hold state. In addition, all pins in the same subnode
should have the same power domain. For configuration detail,
refer to https://github.com/sophgo/sophgo-doc/.
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
properties:
pinmux:
description: |
The list of GPIOs and their mux settings that properties in the
node apply to. This should be set using the GPIOMUX or GPIOMUX2
macro.
bias-pull-up:
type: boolean
bias-pull-down:
type: boolean
drive-strength-microamp:
description: typical current when output high level.
input-schmitt-microvolt:
description: typical threshold for schmitt trigger.
power-source:
description: power supplies at X mV.
enum: [ 1800, 3300 ]
slew-rate:
description: slew rate for output buffer (0 is fast, 1 is slow)
enum: [ 0, 1 ]
bias-bus-hold: true
required:
- pinmux
- power-source
additionalProperties: false
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
pinctrl@3001000 {
compatible = "sophgo,cv1800b-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
uart0_cfg: uart0-cfg {
uart0-pins {
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
<PINMUX(PIN_UART0_RX, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
input-schmitt-microvolt = <0>;
power-source = <3300>;
slew-rate = <0>;
};
};
};
...

16
drivers/pinctrl/Kconfig
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@@ -213,6 +213,21 @@ config PINCTRL_EQUILIBRIUM
desired pin functions, configure GPIO attributes for LGM SoC pins.
Pin muxing and pin config settings are retrieved from device tree.
config PINCTRL_EYEQ5
bool "Mobileye EyeQ5 pinctrl driver"
depends on OF
depends on MACH_EYEQ5 || COMPILE_TEST
select PINMUX
select GENERIC_PINCONF
select AUXILIARY_BUS
default MACH_EYEQ5
help
Pin controller driver for the Mobileye EyeQ5 platform. It does both
pin config & pin muxing. It does not handle GPIO.
Pin muxing supports two functions for each pin: first is GPIO, second
is pin-dependent. Pin config is about bias & drive strength.
config PINCTRL_GEMINI
bool
depends on ARCH_GEMINI
@@ -583,6 +598,7 @@ source "drivers/pinctrl/qcom/Kconfig"
source "drivers/pinctrl/realtek/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/sophgo/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/sprd/Kconfig"
source "drivers/pinctrl/starfive/Kconfig"

2
drivers/pinctrl/Makefile
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@@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o
obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o
obj-$(CONFIG_PINCTRL_EYEQ5) += pinctrl-eyeq5.o
obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o
obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o
@@ -73,6 +74,7 @@ obj-y += qcom/
obj-$(CONFIG_ARCH_REALTEK) += realtek/
obj-$(CONFIG_PINCTRL_RENESAS) += renesas/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-y += sophgo/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_SOC_STARFIVE) += starfive/

1
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View File

@@ -1280,6 +1280,7 @@ static const struct of_device_id bcm2835_pinctrl_match[] = {
},
{}
};
MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match);
static int bcm2835_pinctrl_probe(struct platform_device *pdev)
{

9
drivers/pinctrl/cirrus/pinctrl-madera-core.c
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@@ -1063,12 +1063,9 @@ static int madera_pin_probe(struct platform_device *pdev)
if (pdata->gpio_configs) {
ret = pinctrl_register_mappings(pdata->gpio_configs,
pdata->n_gpio_configs);
if (ret) {
dev_err(priv->dev,
"Failed to register pdata mappings (%d)\n",
ret);
return ret;
}
if (ret)
return dev_err_probe(priv->dev, ret,
"Failed to register pdata mappings\n");
}
ret = pinctrl_enable(priv->pctl);

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