Merge tag 'mips_4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips

Pull MIPS updates from James Hogan:
 "These are the main MIPS changes for 4.17. Rough overview:

   (1) generic platform: Add support for Microsemi Ocelot SoCs

   (2) crypto: Add CRC32 and CRC32C HW acceleration module

   (3) Various cleanups and misc improvements

  More detailed summary:

  Miscellaneous:
   - hang more efficiently on halt/powerdown/restart
   - pm-cps: Block system suspend when a JTAG probe is present
   - expand make help text for generic defconfigs
   - refactor handling of legacy defconfigs
   - determine the entry point from the ELF file header to fix microMIPS
     for certain toolchains
   - introduce isa-rev.h for MIPS_ISA_REV and use to simplify other code

  Minor cleanups:
   - DTS: boston/ci20: Unit name cleanups and correction
   - kdump: Make the default for PHYSICAL_START always 64-bit
   - constify gpio_led in Alchemy, AR7, and TXX9
   - silence a couple of W=1 warnings
   - remove duplicate includes

  Platform support:
  Generic platform:
   - add support for Microsemi Ocelot
   - dt-bindings: Add vendor prefix for Microsemi Corporation
   - dt-bindings: Add bindings for Microsemi SoCs
   - add ocelot SoC & PCB123 board DTS files
   - MAINTAINERS: Add entry for Microsemi MIPS SoCs
   - enable crc32-mips on r6 configs

  ath79:
   - fix AR724X_PLL_REG_PCIE_CONFIG offset

  BCM47xx:
   - firmware: Use mac_pton() for MAC address parsing
   - add Luxul XAP1500/XWR1750 WiFi LEDs
   - use standard reset button for Luxul XWR-1750

  BMIPS:
   - enable CONFIG_BRCMSTB_PM in bmips_stb_defconfig for build coverage
   - add STB PM, wake-up timer, watchdog DT nodes

  Octeon:
   - drop '.' after newlines in printk calls

  ralink:
   - pci-mt7621: Enable PCIe on MT7688"

* tag 'mips_4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (37 commits)
  MIPS: BCM47XX: Use standard reset button for Luxul XWR-1750
  MIPS: BCM47XX: Add Luxul XAP1500/XWR1750 WiFi LEDs
  MIPS: Make the default for PHYSICAL_START always 64-bit
  MIPS: Use the entry point from the ELF file header
  MAINTAINERS: Add entry for Microsemi MIPS SoCs
  MIPS: generic: Add support for Microsemi Ocelot
  MIPS: mscc: Add ocelot PCB123 device tree
  MIPS: mscc: Add ocelot dtsi
  dt-bindings: mips: Add bindings for Microsemi SoCs
  dt-bindings: Add vendor prefix for Microsemi Corporation
  MIPS: ath79: Fix AR724X_PLL_REG_PCIE_CONFIG offset
  MIPS: pci-mt7620: Enable PCIe on MT7688
  MIPS: pm-cps: Block system suspend when a JTAG probe is present
  MIPS: VDSO: Replace __mips_isa_rev with MIPS_ISA_REV
  MIPS: BPF: Replace __mips_isa_rev with MIPS_ISA_REV
  MIPS: cpu-features.h: Replace __mips_isa_rev with MIPS_ISA_REV
  MIPS: Introduce isa-rev.h to define MIPS_ISA_REV
  MIPS: Hang more efficiently on halt/powerdown/restart
  FIRMWARE: bcm47xx_nvram: Replace mac address parsing
  MIPS: BMIPS: Add Broadcom STB watchdog nodes
  ...
This commit is contained in:
Linus Torvalds
2018-04-10 11:39:22 -07:00
59 changed files with 1381 additions and 84 deletions

View File

@@ -0,0 +1,43 @@
* Microsemi MIPS CPUs
Boards with a SoC of the Microsemi MIPS family shall have the following
properties:
Required properties:
- compatible: "mscc,ocelot"
* Other peripherals:
o CPU chip regs:
The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
functionalities: chip ID, general purpose register for software use, reset
controller, hardware status and configuration, efuses.
Required properties:
- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
- reg : Should contain registers location and length
Example:
syscon@71070000 {
compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
reg = <0x71070000 0x1c>;
};
o CPU system control:
The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
endianness, CPU bus control, CPU status.
Required properties:
- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
- reg : Should contain registers location and length
Example:
syscon@70000000 {
compatible = "mscc,ocelot-cpu-syscon", "syscon";
reg = <0x70000000 0x2c>;
};

View File

@@ -225,6 +225,7 @@ motorola Motorola, Inc.
moxa Moxa Inc.
mpl MPL AG
mqmaker mqmaker Inc.
mscc Microsemi Corporation
msi Micro-Star International Co. Ltd.
mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
multi-inno Multi-Inno Technology Co.,Ltd

View File

@@ -9230,6 +9230,15 @@ S: Maintained
F: drivers/usb/misc/usb251xb.c
F: Documentation/devicetree/bindings/usb/usb251xb.txt
MICROSEMI MIPS SOCS
M: Alexandre Belloni <alexandre.belloni@bootlin.com>
L: linux-mips@linux-mips.org
S: Maintained
F: arch/mips/generic/board-ocelot.c
F: arch/mips/configs/generic/board-ocelot.config
F: arch/mips/boot/dts/mscc/
F: Documentation/devicetree/bindings/mips/mscc.txt
MICROSEMI SMART ARRAY SMARTPQI DRIVER (smartpqi)
M: Don Brace <don.brace@microsemi.com>
L: esc.storagedev@microsemi.com

View File

@@ -2029,6 +2029,7 @@ config CPU_MIPSR6
select CPU_HAS_RIXI
select HAVE_ARCH_BITREVERSE
select MIPS_ASID_BITS_VARIABLE
select MIPS_CRC_SUPPORT
select MIPS_SPRAM
config EVA
@@ -2502,6 +2503,9 @@ config MIPS_ASID_BITS
config MIPS_ASID_BITS_VARIABLE
bool
config MIPS_CRC_SUPPORT
bool
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
@@ -2850,8 +2854,7 @@ config CRASH_DUMP
config PHYSICAL_START
hex "Physical address where the kernel is loaded"
default "0xffffffff84000000" if 64BIT
default "0x84000000" if 32BIT
default "0xffffffff84000000"
depends on CRASH_DUMP
help
This gives the CKSEG0 or KSEG0 address where the kernel is loaded.

View File

@@ -222,6 +222,8 @@ xpa-cflags-y := $(mips-cflags)
xpa-cflags-$(micromips-ase) += -mmicromips -Wa$(comma)-fatal-warnings
toolchain-xpa := $(call cc-option-yn,$(xpa-cflags-y) -mxpa)
cflags-$(toolchain-xpa) += -DTOOLCHAIN_SUPPORTS_XPA
toolchain-crc := $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mcrc)
cflags-$(toolchain-crc) += -DTOOLCHAIN_SUPPORTS_CRC
#
# Firmware support
@@ -249,20 +251,12 @@ ifdef CONFIG_PHYSICAL_START
load-y = $(CONFIG_PHYSICAL_START)
endif
entry-noisa-y = 0x$(shell $(NM) vmlinux 2>/dev/null \
| grep "\bkernel_entry\b" | cut -f1 -d \ )
ifdef CONFIG_CPU_MICROMIPS
#
# Set the ISA bit, since the kernel_entry symbol in the ELF will have it
# clear which would lead to images containing addresses which bootloaders may
# jump to as MIPS32 code.
#
entry-y = $(patsubst %0,%1,$(patsubst %2,%3,$(patsubst %4,%5, \
$(patsubst %6,%7,$(patsubst %8,%9,$(patsubst %a,%b, \
$(patsubst %c,%d,$(patsubst %e,%f,$(entry-noisa-y)))))))))
else
entry-y = $(entry-noisa-y)
endif
# Sign-extend the entry point to 64 bits if retrieved as a 32-bit number.
entry-y = $(shell $(OBJDUMP) -f vmlinux 2>/dev/null \
| sed -n '/^start address / { \
s/^.* //; \
s/0x\([0-7].......\)$$/0x00000000\1/; \
s/0x\(........\)$$/0xffffffff\1/; p }')
cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
drivers-$(CONFIG_PCI) += arch/mips/pci/
@@ -330,6 +324,7 @@ libs-y += arch/mips/math-emu/
# See arch/mips/Kbuild for content of core part of the kernel
core-y += arch/mips/
drivers-$(CONFIG_MIPS_CRC_SUPPORT) += arch/mips/crypto/
drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/
# suspend and hibernation support
@@ -473,6 +468,21 @@ define archhelp
echo
echo ' {micro32,32,64}{r1,r2,r6}{el,}_defconfig <BOARDS="list of boards">'
echo
echo ' Where BOARDS is some subset of the following:'
for board in $(sort $(BOARDS)); do echo " $${board}"; done
echo
echo ' Specifically the following generic default configurations are'
echo ' supported:'
echo
$(foreach cfg,$(generic_defconfigs),
printf " %-24s - Build generic kernel for $(call describe_generic_defconfig,$(cfg))\n" $(cfg);)
echo
echo ' The following legacy default configurations have been converted to'
echo ' generic and can still be used:'
echo
$(foreach cfg,$(sort $(legacy_defconfigs)),
printf " %-24s - Build $($(cfg)-y)\n" $(cfg);)
echo
echo ' Otherwise, the following default configurations are available:'
endef
@@ -507,6 +517,10 @@ endef
$(eval $(call gen_generic_defconfigs,32 64,r1 r2 r6,eb el))
$(eval $(call gen_generic_defconfigs,micro32,r2,eb el))
define describe_generic_defconfig
$(subst 32r,MIPS32 r,$(subst 64r,MIPS64 r,$(subst el, little endian,$(patsubst %_defconfig,%,$(1)))))
endef
.PHONY: $(generic_defconfigs)
$(generic_defconfigs):
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh \
@@ -543,14 +557,18 @@ generic_defconfig:
# now that the boards have been converted to use the generic kernel they are
# wrappers around the generic rules above.
#
.PHONY: sead3_defconfig
sead3_defconfig:
$(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=sead-3
legacy_defconfigs += ocelot_defconfig
ocelot_defconfig-y := 32r2el_defconfig BOARDS=ocelot
.PHONY: sead3micro_defconfig
sead3micro_defconfig:
$(Q)$(MAKE) -f $(srctree)/Makefile micro32r2el_defconfig BOARDS=sead-3
legacy_defconfigs += sead3_defconfig
sead3_defconfig-y := 32r2el_defconfig BOARDS=sead-3
.PHONY: xilfpga_defconfig
xilfpga_defconfig:
$(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=xilfpga
legacy_defconfigs += sead3micro_defconfig
sead3micro_defconfig-y := micro32r2el_defconfig BOARDS=sead-3
legacy_defconfigs += xilfpga_defconfig
xilfpga_defconfig-y := 32r2el_defconfig BOARDS=xilfpga
.PHONY: $(legacy_defconfigs)
$(legacy_defconfigs):
$(Q)$(MAKE) -f $(srctree)/Makefile $($@-y)

View File

@@ -190,7 +190,7 @@ static struct platform_device gpr_mtd_device = {
/*
* LEDs
*/
static struct gpio_led gpr_gpio_leds[] = {
static const struct gpio_led gpr_gpio_leds[] = {
{ /* green */
.name = "gpr:green",
.gpio = 4,

View File

@@ -145,7 +145,7 @@ static struct platform_device mtx1_wdt = {
.resource = mtx1_wdt_res,
};
static struct gpio_led default_leds[] = {
static const struct gpio_led default_leds[] = {
{
.name = "mtx1:green",
.gpio = 211,

View File

@@ -346,7 +346,7 @@ static struct platform_device ar7_udc = {
/*****************************************************************************
* LEDs
****************************************************************************/
static struct gpio_led default_leds[] = {
static const struct gpio_led default_leds[] = {
{
.name = "status",
.gpio = 8,
@@ -354,12 +354,12 @@ static struct gpio_led default_leds[] = {
},
};
static struct gpio_led titan_leds[] = {
static const struct gpio_led titan_leds[] = {
{ .name = "status", .gpio = 8, .active_low = 1, },
{ .name = "wifi", .gpio = 13, .active_low = 1, },
};
static struct gpio_led dsl502t_leds[] = {
static const struct gpio_led dsl502t_leds[] = {
{
.name = "status",
.gpio = 9,
@@ -377,7 +377,7 @@ static struct gpio_led dsl502t_leds[] = {
},
};
static struct gpio_led dg834g_leds[] = {
static const struct gpio_led dg834g_leds[] = {
{
.name = "ppp",
.gpio = 6,
@@ -406,7 +406,7 @@ static struct gpio_led dg834g_leds[] = {
},
};
static struct gpio_led fb_sl_leds[] = {
static const struct gpio_led fb_sl_leds[] = {
{
.name = "1",
.gpio = 7,
@@ -433,7 +433,7 @@ static struct gpio_led fb_sl_leds[] = {
},
};
static struct gpio_led fb_fon_leds[] = {
static const struct gpio_led fb_fon_leds[] = {
{
.name = "1",
.gpio = 8,
@@ -459,7 +459,7 @@ static struct gpio_led fb_fon_leds[] = {
},
};
static struct gpio_led gt701_leds[] = {
static const struct gpio_led gt701_leds[] = {
{
.name = "inet:green",
.gpio = 13,

View File

@@ -355,7 +355,7 @@ bcm47xx_buttons_luxul_xwr_600_v1[] = {
static const struct gpio_keys_button
bcm47xx_buttons_luxul_xwr_1750_v1[] = {
BCM47XX_GPIO_KEY(14, BTN_TASK),
BCM47XX_GPIO_KEY(14, KEY_RESTART),
};
/* Microsoft */

View File

@@ -408,6 +408,12 @@ bcm47xx_leds_luxul_xap_1500_v1[] __initconst = {
BCM47XX_GPIO_LED_TRIGGER(13, "green", "status", 1, "timer"),
};
static const struct gpio_led
bcm47xx_leds_luxul_xap1500_v1_extra[] __initconst = {
BCM47XX_GPIO_LED(44, "green", "5ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
BCM47XX_GPIO_LED(76, "green", "2ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
};
static const struct gpio_led
bcm47xx_leds_luxul_xbr_4400_v1[] __initconst = {
BCM47XX_GPIO_LED(12, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
@@ -435,6 +441,11 @@ bcm47xx_leds_luxul_xwr_1750_v1[] __initconst = {
BCM47XX_GPIO_LED(15, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
};
static const struct gpio_led
bcm47xx_leds_luxul_xwr1750_v1_extra[] __initconst = {
BCM47XX_GPIO_LED(76, "green", "2ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
};
/* Microsoft */
static const struct gpio_led
@@ -528,6 +539,12 @@ static struct gpio_led_platform_data bcm47xx_leds_pdata;
bcm47xx_leds_pdata.num_leds = ARRAY_SIZE(dev_leds); \
} while (0)
static struct gpio_led_platform_data bcm47xx_leds_pdata_extra __initdata = {};
#define bcm47xx_set_pdata_extra(dev_leds) do { \
bcm47xx_leds_pdata_extra.leds = dev_leds; \
bcm47xx_leds_pdata_extra.num_leds = ARRAY_SIZE(dev_leds); \
} while (0)
void __init bcm47xx_leds_register(void)
{
enum bcm47xx_board board = bcm47xx_board_get();
@@ -705,6 +722,7 @@ void __init bcm47xx_leds_register(void)
break;
case BCM47XX_BOARD_LUXUL_XAP_1500_V1:
bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_1500_v1);
bcm47xx_set_pdata_extra(bcm47xx_leds_luxul_xap1500_v1_extra);
break;
case BCM47XX_BOARD_LUXUL_XBR_4400_V1:
bcm47xx_set_pdata(bcm47xx_leds_luxul_xbr_4400_v1);
@@ -717,6 +735,7 @@ void __init bcm47xx_leds_register(void)
break;
case BCM47XX_BOARD_LUXUL_XWR_1750_V1:
bcm47xx_set_pdata(bcm47xx_leds_luxul_xwr_1750_v1);
bcm47xx_set_pdata_extra(bcm47xx_leds_luxul_xwr1750_v1_extra);
break;
case BCM47XX_BOARD_MICROSOFT_MN700:
@@ -760,4 +779,6 @@ void __init bcm47xx_leds_register(void)
}
gpio_led_register_device(-1, &bcm47xx_leds_pdata);
if (bcm47xx_leds_pdata_extra.num_leds)
gpio_led_register_device(0, &bcm47xx_leds_pdata_extra);
}

View File

@@ -4,6 +4,7 @@ subdir-y += cavium-octeon
subdir-y += img
subdir-y += ingenic
subdir-y += lantiq
subdir-y += mscc
subdir-y += mti
subdir-y += netlogic
subdir-y += ni

View File

@@ -198,6 +198,13 @@
status = "disabled";
};
watchdog: watchdog@4067e8 {
clocks = <&upg_clk>;
compatible = "brcm,bcm7038-wdt";
reg = <0x4067e8 0x14>;
status = "disabled";
};
upg_gio: gpio@406700 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406700 0x80>;

View File

@@ -233,6 +233,13 @@
status = "disabled";
};
watchdog: watchdog@4067e8 {
clocks = <&upg_clk>;
compatible = "brcm,bcm7038-wdt";
reg = <0x4067e8 0x14>;
status = "disabled";
};
aon_pm_l2_intc: interrupt-controller@408440 {
compatible = "brcm,l2-intc";
reg = <0x408440 0x30>;
@@ -243,6 +250,17 @@
brcm,irq-can-wake;
};
aon_ctrl: syscon@408000 {
compatible = "brcm,brcmstb-aon-ctrl";
reg = <0x408000 0x100>, <0x408200 0x200>;
reg-names = "aon-ctrl", "aon-sram";
};
timers: timer@4067c0 {
compatible = "brcm,brcmstb-timers";
reg = <0x4067c0 0x40>;
};
upg_gio: gpio@406700 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406700 0x60>;
@@ -483,5 +501,49 @@
interrupt-names = "mspi_done";
status = "disabled";
};
waketimer: waketimer@408e80 {
compatible = "brcm,brcmstb-waketimer";
reg = <0x408e80 0x14>;
interrupts = <0x3>;
interrupt-parent = <&aon_pm_l2_intc>;
interrupt-names = "timer";
clocks = <&upg_clk>;
status = "disabled";
};
};
memory_controllers {
compatible = "simple-bus";
ranges = <0x0 0x103b0000 0xa000>;
#address-cells = <1>;
#size-cells = <1>;
memory-controller@0 {
compatible = "brcm,brcmstb-memc", "simple-bus";
ranges = <0x0 0x0 0xa000>;
#address-cells = <1>;
#size-cells = <1>;
memc-arb@1000 {
compatible = "brcm,brcmstb-memc-arb";
reg = <0x1000 0x248>;
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};
ddr-phy@6000 {
compatible = "brcm,brcmstb-ddr-phy";
reg = <0x6000 0xc8>;
};
shimphy@8000 {
compatible = "brcm,brcmstb-ddr-shimphy";
reg = <0x8000 0x13c>;
};
};
};
};

View File

@@ -217,6 +217,13 @@
status = "disabled";
};
watchdog: watchdog@4066a8 {
clocks = <&upg_clk>;
compatible = "brcm,bcm7038-wdt";
reg = <0x4066a8 0x14>;
status = "disabled";
};
aon_pm_l2_intc: interrupt-controller@408240 {
compatible = "brcm,l2-intc";
reg = <0x408240 0x30>;
@@ -362,5 +369,15 @@
interrupt-names = "mspi_done";
status = "disabled";
};
waketimer: waketimer@408e80 {
compatible = "brcm,brcmstb-waketimer";
reg = <0x408e80 0x14>;
interrupts = <0x3>;
interrupt-parent = <&aon_pm_l2_intc>;
interrupt-names = "timer";
clocks = <&upg_clk>;
status = "disabled";
};
};
};

View File

@@ -209,6 +209,13 @@
status = "disabled";
};
watchdog: watchdog@4066a8 {
clocks = <&upg_clk>;
compatible = "brcm,bcm7038-wdt";
reg = <0x4066a8 0x14>;
status = "disabled";
};
aon_pm_l2_intc: interrupt-controller@408440 {
compatible = "brcm,l2-intc";
reg = <0x408440 0x30>;
@@ -219,6 +226,17 @@
brcm,irq-can-wake;
};
aon_ctrl: syscon@408000 {
compatible = "brcm,brcmstb-aon-ctrl";
reg = <0x408000 0x100>, <0x408200 0x200>;
reg-names = "aon-ctrl", "aon-sram";
};
timers: timer@406680 {
compatible = "brcm,brcmstb-timers";
reg = <0x406680 0x40>;
};
upg_gio: gpio@406500 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406500 0xa0>;
@@ -402,5 +420,49 @@
interrupt-names = "mspi_done";
status = "disabled";
};
waketimer: waketimer@408e80 {
compatible = "brcm,brcmstb-waketimer";
reg = <0x408e80 0x14>;
interrupts = <0x3>;
interrupt-parent = <&aon_pm_l2_intc>;
interrupt-names = "timer";
clocks = <&upg_clk>;
status = "disabled";
};
};
memory_controllers {
compatible = "simple-bus";
ranges = <0x0 0x103b0000 0xa000>;
#address-cells = <1>;
#size-cells = <1>;
memory-controller@0 {
compatible = "brcm,brcmstb-memc", "simple-bus";
ranges = <0x0 0x0 0xa000>;
#address-cells = <1>;
#size-cells = <1>;
memc-arb@1000 {
compatible = "brcm,brcmstb-memc-arb";
reg = <0x1000 0x248>;
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};
ddr-phy@6000 {
compatible = "brcm,brcmstb-ddr-phy";
reg = <0x6000 0xc8>;
};
shimphy@8000 {
compatible = "brcm,brcmstb-ddr-shimphy";
reg = <0x8000 0x13c>;
};
};
};
};

View File

@@ -205,6 +205,13 @@
status = "disabled";
};
watchdog: watchdog@4066a8 {
clocks = <&upg_clk>;
compatible = "brcm,bcm7038-wdt";
reg = <0x4066a8 0x14>;
status = "disabled";
};
aon_pm_l2_intc: interrupt-controller@408440 {
compatible = "brcm,l2-intc";
reg = <0x408440 0x30>;
@@ -215,6 +222,17 @@
brcm,irq-can-wake;
};
aon_ctrl: syscon@408000 {
compatible = "brcm,brcmstb-aon-ctrl";
reg = <0x408000 0x100>, <0x408200 0x200>;
reg-names = "aon-ctrl", "aon-sram";
};
timers: timer@406680 {
compatible = "brcm,brcmstb-timers";
reg = <0x406680 0x40>;
};
upg_gio: gpio@406500 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406500 0xa0>;
@@ -398,5 +416,49 @@
interrupt-names = "mspi_done";
status = "disabled";
};
waketimer: waketimer@408e80 {
compatible = "brcm,brcmstb-waketimer";
reg = <0x408e80 0x14>;
interrupts = <0x3>;
interrupt-parent = <&aon_pm_l2_intc>;
interrupt-names = "timer";
clocks = <&upg_clk>;
status = "disabled";
};
};
memory_controllers {
compatible = "simple-bus";
ranges = <0x0 0x103b0000 0xa000>;
#address-cells = <1>;
#size-cells = <1>;
memory-controller@0 {
compatible = "brcm,brcmstb-memc", "simple-bus";
ranges = <0x0 0x0 0xa000>;
#address-cells = <1>;
#size-cells = <1>;
memc-arb@1000 {
compatible = "brcm,brcmstb-memc-arb";
reg = <0x1000 0x248>;
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};
ddr-phy@6000 {
compatible = "brcm,brcmstb-ddr-phy";
reg = <0x6000 0xc8>;
};
shimphy@8000 {
compatible = "brcm,brcmstb-ddr-shimphy";
reg = <0x8000 0x13c>;
};
};
};
};

View File

@@ -214,6 +214,13 @@
status = "disabled";
};
watchdog: watchdog@4067e8 {
clocks = <&upg_clk>;
compatible = "brcm,bcm7038-wdt";
reg = <0x4067e8 0x14>;
status = "disabled";
};
upg_gio: gpio@406700 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406700 0x80>;

View File

@@ -232,6 +232,13 @@
status = "disabled";
};
watchdog: watchdog@4067e8 {
clocks = <&upg_clk>;
compatible = "brcm,bcm7038-wdt";
reg = <0x4067e8 0x14>;
status = "disabled";
};
aon_pm_l2_intc: interrupt-controller@408440 {
compatible = "brcm,l2-intc";
reg = <0x408440 0x30>;
@@ -242,6 +249,17 @@
brcm,irq-can-wake;
};
aon_ctrl: syscon@408000 {
compatible = "brcm,brcmstb-aon-ctrl";
reg = <0x408000 0x100>, <0x408200 0x200>;
reg-names = "aon-ctrl", "aon-sram";
};
timers: timer@4067c0 {
compatible = "brcm,brcmstb-timers";
reg = <0x4067c0 0x40>;
};
upg_gio: gpio@406700 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406700 0x80>;
@@ -494,5 +512,76 @@
interrupt-names = "mspi_done";
status = "disabled";
};
waketimer: waketimer@409580 {
compatible = "brcm,brcmstb-waketimer";
reg = <0x409580 0x14>;
interrupts = <0x3>;
interrupt-parent = <&aon_pm_l2_intc>;
interrupt-names = "timer";
clocks = <&upg_clk>;
status = "disabled";
};
};
memory_controllers {
compatible = "simple-bus";
ranges = <0x0 0x103b0000 0x1a000>;
#address-cells = <1>;
#size-cells = <1>;
memory-controller@0 {
compatible = "brcm,brcmstb-memc", "simple-bus";
ranges = <0x0 0x0 0xa000>;
#address-cells = <1>;
#size-cells = <1>;
memc-arb@1000 {
compatible = "brcm,brcmstb-memc-arb";
reg = <0x1000 0x248>;
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};
ddr-phy@6000 {
compatible = "brcm,brcmstb-ddr-phy";
reg = <0x6000 0xc8>;
};
shimphy@8000 {
compatible = "brcm,brcmstb-ddr-shimphy";
reg = <0x8000 0x13c>;
};
};
memory-controller@1 {
compatible = "brcm,brcmstb-memc", "simple-bus";
ranges = <0x0 0x10000 0xa000>;
#address-cells = <1>;
#size-cells = <1>;
memc-arb@1000 {
compatible = "brcm,brcmstb-memc-arb";
reg = <0x1000 0x248>;
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};
ddr-phy@6000 {
compatible = "brcm,brcmstb-ddr-phy";
reg = <0x6000 0xc8>;
};
shimphy@8000 {
compatible = "brcm,brcmstb-ddr-shimphy";
reg = <0x8000 0x13c>;
};
};
};
};

View File

@@ -247,6 +247,13 @@
status = "disabled";
};
watchdog: watchdog@4067e8 {
clocks = <&upg_clk>;
compatible = "brcm,bcm7038-wdt";
reg = <0x4067e8 0x14>;
status = "disabled";
};
aon_pm_l2_intc: interrupt-controller@408440 {
compatible = "brcm,l2-intc";
reg = <0x408440 0x30>;
@@ -257,6 +264,17 @@
brcm,irq-can-wake;
};
aon_ctrl: syscon@408000 {
compatible = "brcm,brcmstb-aon-ctrl";
reg = <0x408000 0x100>, <0x408200 0x200>;
reg-names = "aon-ctrl", "aon-sram";
};
timers: timer@4067c0 {
compatible = "brcm,brcmstb-timers";
reg = <0x4067c0 0x40>;
};
upg_gio: gpio@406700 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406700 0x80>;
@@ -509,5 +527,76 @@
interrupt-names = "mspi_done";
status = "disabled";
};
waketimer: waketimer@409580 {
compatible = "brcm,brcmstb-waketimer";
reg = <0x409580 0x14>;
interrupts = <0x3>;
interrupt-parent = <&aon_pm_l2_intc>;
interrupt-names = "timer";
clocks = <&upg_clk>;
status = "disabled";
};
};
memory_controllers {
compatible = "simple-bus";
ranges = <0x0 0x103b0000 0x1a000>;
#address-cells = <1>;
#size-cells = <1>;
memory-controller@0 {
compatible = "brcm,brcmstb-memc", "simple-bus";
ranges = <0x0 0x0 0xa000>;
#address-cells = <1>;
#size-cells = <1>;
memc-arb@1000 {
compatible = "brcm,brcmstb-memc-arb";
reg = <0x1000 0x248>;
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};
ddr-phy@6000 {
compatible = "brcm,brcmstb-ddr-phy";
reg = <0x6000 0xc8>;
};
shimphy@8000 {
compatible = "brcm,brcmstb-ddr-shimphy";
reg = <0x8000 0x13c>;
};
};
memory-controller@1 {
compatible = "brcm,brcmstb-memc", "simple-bus";
ranges = <0x0 0x10000 0xa000>;
#address-cells = <1>;
#size-cells = <1>;
memc-arb@1000 {
compatible = "brcm,brcmstb-memc-arb";
reg = <0x1000 0x248>;
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};
ddr-phy@6000 {
compatible = "brcm,brcmstb-ddr-phy";
reg = <0x6000 0xc8>;
};
shimphy@8000 {
compatible = "brcm,brcmstb-ddr-shimphy";
reg = <0x8000 0x13c>;
};
};
};
};

View File

@@ -50,6 +50,10 @@
status = "okay";
};
&watchdog {
status = "okay";
};
/* FIXME: USB is wonky; disable it for now */
&ehci0 {
status = "disabled";

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