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dt-bindings: display: Convert fsl,imx-fb.txt to dt-schema
Compared to the txt description this adds clocks and clock-names to match reality. Note that fsl,imx-lcdc was picked as the new name as this is the actual hardware's name. There will be a new binding implementing the saner drm concept that is supposed to supersede this legacy fb binding Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221129180414.2729091-1-u.kleine-koenig@pengutronix.de Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Uwe Kleine-König
committed by
Rob Herring
Rob Herring
parent
7621aabdae
commit
93266da240
@@ -1,57 +0,0 @@
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Freescale imx21 Framebuffer
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This framebuffer driver supports devices imx1, imx21, imx25, and imx27.
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Required properties:
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- compatible : "fsl,<chip>-fb", chip should be imx1 or imx21
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- reg : Should contain 1 register ranges(address and length)
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- interrupts : One interrupt of the fb dev
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Required nodes:
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- display: Phandle to a display node as described in
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Documentation/devicetree/bindings/display/panel/display-timing.txt
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Additional, the display node has to define properties:
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- bits-per-pixel: Bits per pixel
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- fsl,pcr: LCDC PCR value
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A display node may optionally define
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- fsl,aus-mode: boolean to enable AUS mode (only for imx21)
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Optional properties:
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- lcd-supply: Regulator for LCD supply voltage.
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- fsl,dmacr: DMA Control Register value. This is optional. By default, the
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register is not modified as recommended by the datasheet.
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- fsl,lpccr: Contrast Control Register value. This property provides the
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default value for the contrast control register.
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If that property is omitted, the register is zeroed.
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- fsl,lscr1: LCDC Sharp Configuration Register value.
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Example:
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imxfb: fb@10021000 {
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compatible = "fsl,imx21-fb";
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interrupts = <61>;
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reg = <0x10021000 0x1000>;
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display = <&display0>;
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};
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...
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display0: display0 {
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model = "Primeview-PD050VL1";
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bits-per-pixel = <16>;
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fsl,pcr = <0xf0c88080>; /* non-standard but required */
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display-timings {
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native-mode = <&timing_disp0>;
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timing_disp0: 640x480 {
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hactive = <640>;
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vactive = <480>;
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hback-porch = <112>;
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hfront-porch = <36>;
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hsync-len = <32>;
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vback-porch = <33>;
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vfront-porch = <33>;
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vsync-len = <2>;
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clock-frequency = <25000000>;
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};
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};
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};
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102
Documentation/devicetree/bindings/display/imx/fsl,imx-lcdc.yaml
Normal file
102
Documentation/devicetree/bindings/display/imx/fsl,imx-lcdc.yaml
Normal file
@@ -0,0 +1,102 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX LCD Controller, found on i.MX1, i.MX21, i.MX25 and i.MX27
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maintainers:
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- Sascha Hauer <s.hauer@pengutronix.de>
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- Pengutronix Kernel Team <kernel@pengutronix.de>
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,imx1-fb
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- fsl,imx21-fb
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- items:
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- enum:
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- fsl,imx25-fb
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- fsl,imx27-fb
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- const: fsl,imx21-fb
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: ipg
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- const: ahb
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- const: per
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display:
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$ref: /schemas/types.yaml#/definitions/phandle
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interrupts:
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maxItems: 1
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reg:
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maxItems: 1
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lcd-supply:
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description:
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Regulator for LCD supply voltage.
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fsl,dmacr:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Override value for DMA Control Register
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fsl,lpccr:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Contrast Control Register value.
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fsl,lscr1:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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LCDC Sharp Configuration Register value.
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required:
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- compatible
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- clocks
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- clock-names
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- display
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- interrupts
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- reg
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additionalProperties: false
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examples:
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- |
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imxfb: fb@10021000 {
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compatible = "fsl,imx21-fb";
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interrupts = <61>;
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reg = <0x10021000 0x1000>;
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display = <&display0>;
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clocks = <&clks 103>, <&clks 49>, <&clks 66>;
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clock-names = "ipg", "ahb", "per";
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};
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display0: display0 {
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model = "Primeview-PD050VL1";
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bits-per-pixel = <16>;
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fsl,pcr = <0xf0c88080>; /* non-standard but required */
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display-timings {
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native-mode = <&timing_disp0>;
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timing_disp0: timing0 {
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hactive = <640>;
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vactive = <480>;
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hback-porch = <112>;
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hfront-porch = <36>;
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hsync-len = <32>;
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vback-porch = <33>;
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vfront-porch = <33>;
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vsync-len = <2>;
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clock-frequency = <25000000>;
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};
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};
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};
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