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ptp: clockmatrix: use rsmu driver to access i2c/spi bus

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rsmu (Renesas Synchronization Management Unit ) driver is located in
drivers/mfd and responsible for creating multiple devices including
clockmatrix phc, which will then use the exposed regmap and mutex
handle to access i2c/spi bus.

Signed-off-by: Min Li <min.li.xe@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Min Li
2021-09-24 15:01:32 -04:00
committed by David S. Miller
parent b69c99463d
commit 930dfa5631
4 changed files with 467 additions and 1248 deletions
Download Patch File Download Diff File Expand all files Collapse all files

783
drivers/ptp/idt8a340_reg.h
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File diff suppressed because it is too large Load Diff

784
drivers/ptp/ptp_clockmatrix.c
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File diff suppressed because it is too large Load Diff

117
drivers/ptp/ptp_clockmatrix.h
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@@ -9,8 +9,8 @@
#define PTP_IDTCLOCKMATRIX_H
#include <linux/ktime.h>
#include "idt8a340_reg.h"
#include <linux/mfd/idt8a340_reg.h>
#include <linux/regmap.h>
#define FW_FILENAME "idtcm.bin"
#define MAX_TOD (4)
@@ -44,7 +44,6 @@
#define DEFAULT_TOD2_PTP_PLL (2)
#define DEFAULT_TOD3_PTP_PLL (3)
#define POST_SM_RESET_DELAY_MS (3000)
#define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED (150000)
#define PHASE_PULL_IN_THRESHOLD_NS (15000)
#define TOD_WRITE_OVERHEAD_COUNT_MAX (2)
@@ -64,6 +63,11 @@
* Return register address based on passed in firmware version
*/
#define IDTCM_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER))
enum fw_version {
V_DEFAULT = 0,
V487 = 1,
V520 = 2,
};
/* PTP PLL Mode */
enum ptp_pll_mode {
@@ -74,94 +78,6 @@ enum ptp_pll_mode {
PTP_PLL_MODE_MAX = PTP_PLL_MODE_UNSUPPORTED,
};
/* Values of DPLL_N.DPLL_MODE.PLL_MODE */
enum pll_mode {
PLL_MODE_MIN = 0,
PLL_MODE_PLL = PLL_MODE_MIN,
PLL_MODE_WRITE_PHASE = 1,
PLL_MODE_WRITE_FREQUENCY = 2,
PLL_MODE_GPIO_INC_DEC = 3,
PLL_MODE_SYNTHESIS = 4,
PLL_MODE_PHASE_MEASUREMENT = 5,
PLL_MODE_DISABLED = 6,
PLL_MODE_MAX = PLL_MODE_DISABLED,
};
/* Values of DPLL_CTRL_n.DPLL_MANU_REF_CFG.MANUAL_REFERENCE */
enum manual_reference {
MANU_REF_MIN = 0,
MANU_REF_CLK0 = MANU_REF_MIN,
MANU_REF_CLK1,
MANU_REF_CLK2,
MANU_REF_CLK3,
MANU_REF_CLK4,
MANU_REF_CLK5,
MANU_REF_CLK6,
MANU_REF_CLK7,
MANU_REF_CLK8,
MANU_REF_CLK9,
MANU_REF_CLK10,
MANU_REF_CLK11,
MANU_REF_CLK12,
MANU_REF_CLK13,
MANU_REF_CLK14,
MANU_REF_CLK15,
MANU_REF_WRITE_PHASE,
MANU_REF_WRITE_FREQUENCY,
MANU_REF_XO_DPLL,
MANU_REF_MAX = MANU_REF_XO_DPLL,
};
enum hw_tod_write_trig_sel {
HW_TOD_WR_TRIG_SEL_MIN = 0,
HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN,
HW_TOD_WR_TRIG_SEL_RESERVED = 1,
HW_TOD_WR_TRIG_SEL_TOD_PPS = 2,
HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3,
HW_TOD_WR_TRIG_SEL_PWM_PPS = 4,
HW_TOD_WR_TRIG_SEL_GPIO = 5,
HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6,
WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC,
};
/* 4.8.7 only */
enum scsr_tod_write_trig_sel {
SCSR_TOD_WR_TRIG_SEL_DISABLE = 0,
SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1,
SCSR_TOD_WR_TRIG_SEL_REFCLK = 2,
SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3,
SCSR_TOD_WR_TRIG_SEL_TODPPS = 4,
SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5,
SCSR_TOD_WR_TRIG_SEL_GPIO = 6,
SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO,
};
/* 4.8.7 only */
enum scsr_tod_write_type_sel {
SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0,
SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1,
SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2,
SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS,
};
/* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */
enum dpll_state {
DPLL_STATE_MIN = 0,
DPLL_STATE_FREERUN = DPLL_STATE_MIN,
DPLL_STATE_LOCKACQ = 1,
DPLL_STATE_LOCKREC = 2,
DPLL_STATE_LOCKED = 3,
DPLL_STATE_HOLDOVER = 4,
DPLL_STATE_OPEN_LOOP = 5,
DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP,
};
enum fw_version {
V_DEFAULT = 0,
V487 = 1,
V520 = 2,
};
struct idtcm;
struct idtcm_channel {
@@ -185,25 +101,32 @@ struct idtcm_channel {
s32 offset_ns, u32 max_ffo_ppb);
s32 current_freq_scaled_ppm;
bool phase_pull_in;
u32 dco_delay;
/* last input trigger for extts */
u8 refn;
u8 pll;
u16 output_mask;
};
struct idtcm {
struct idtcm_channel channel[MAX_TOD];
struct i2c_client *client;
u8 page_offset;
struct device *dev;
u8 tod_mask;
char version[16];
enum fw_version fw_ver;
/* Polls for external time stamps */
u8 extts_mask;
struct delayed_work extts_work;
/* Remember the ptp channel to report extts */
struct idtcm_channel *event_channel[MAX_TOD];
/* Mutex to protect operations from being interrupted */
struct mutex *lock;
struct device *mfd;
struct regmap *regmap;
/* Overhead calculation for adjtime */
u8 calculate_overhead_flag;
s64 tod_write_overhead_ns;
ktime_t start_time;
/* Protects I2C read/modify/write registers from concurrent access */
struct mutex reg_lock;
};
struct idtcm_fwrc {

31
include/linux/mfd/idt8a340_reg.h
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@@ -506,6 +506,10 @@
#define STATE_MODE_SHIFT (0)
#define STATE_MODE_MASK (0x7)
/* Bit definitions for the DPLL_MANU_REF_CFG register */
#define MANUAL_REFERENCE_SHIFT (0)
#define MANUAL_REFERENCE_MASK (0x1f)
/* Bit definitions for the GPIO_CFG_GBL register */
#define SUPPLY_MODE_SHIFT (0)
#define SUPPLY_MODE_MASK (0x3)
@@ -654,7 +658,7 @@
/* Values of DPLL_N.DPLL_MODE.PLL_MODE */
enum pll_mode {
PLL_MODE_MIN = 0,
PLL_MODE_NORMAL = PLL_MODE_MIN,
PLL_MODE_PLL = PLL_MODE_MIN,
PLL_MODE_WRITE_PHASE = 1,
PLL_MODE_WRITE_FREQUENCY = 2,
PLL_MODE_GPIO_INC_DEC = 3,
@@ -664,6 +668,31 @@ enum pll_mode {
PLL_MODE_MAX = PLL_MODE_DISABLED,
};
/* Values of DPLL_CTRL_n.DPLL_MANU_REF_CFG.MANUAL_REFERENCE */
enum manual_reference {
MANU_REF_MIN = 0,
MANU_REF_CLK0 = MANU_REF_MIN,
MANU_REF_CLK1,
MANU_REF_CLK2,
MANU_REF_CLK3,
MANU_REF_CLK4,
MANU_REF_CLK5,
MANU_REF_CLK6,
MANU_REF_CLK7,
MANU_REF_CLK8,
MANU_REF_CLK9,
MANU_REF_CLK10,
MANU_REF_CLK11,
MANU_REF_CLK12,
MANU_REF_CLK13,
MANU_REF_CLK14,
MANU_REF_CLK15,
MANU_REF_WRITE_PHASE,
MANU_REF_WRITE_FREQUENCY,
MANU_REF_XO_DPLL,
MANU_REF_MAX = MANU_REF_XO_DPLL,
};
enum hw_tod_write_trig_sel {
HW_TOD_WR_TRIG_SEL_MIN = 0,
HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN,