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Merge branch 'sh/stable-updates'

Browse Source
This commit is contained in:
Paul Mundt
2010-02-05 12:16:39 +09:00
parent 9ad62ec4f7 2c940db250
commit 8e04221029
109 changed files with 1203 additions and 532 deletions
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4
Documentation/fault-injection/fault-injection.txt
View File

@@ -143,8 +143,8 @@ o provide a way to configure fault attributes
failslab, fail_page_alloc, and fail_make_request use this way.
Helper functions:
init_fault_attr_entries(entries, attr, name);
void cleanup_fault_attr_entries(entries);
init_fault_attr_dentries(entries, attr, name);
void cleanup_fault_attr_dentries(entries);
- module parameters

1
arch/arm/Kconfig
View File

@@ -702,6 +702,7 @@ config ARCH_OMAP
select ARCH_HAS_CPUFREQ
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select ARCH_HAS_HOLES_MEMORYMODEL
help
Support for TI's OMAP platform (OMAP1 and OMAP2).

2
arch/arm/Makefile
View File

@@ -94,7 +94,7 @@ CFLAGS_ABI +=-funwind-tables
endif
ifeq ($(CONFIG_THUMB2_KERNEL),y)
AFLAGS_AUTOIT :=$(call as-option,-Wa$(comma)-mimplicit-it=thumb,-Wa$(comma)-mauto-it)
AFLAGS_AUTOIT :=$(call as-option,-Wa$(comma)-mimplicit-it=always,-Wa$(comma)-mauto-it)
AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)
CFLAGS_THUMB2 :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)
AFLAGS_THUMB2 :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb

58
arch/arm/mach-mx25/clock.c
View File

@@ -119,6 +119,11 @@ static unsigned long get_rate_nfc(struct clk *clk)
return get_rate_per(8);
}
static unsigned long get_rate_gpt(struct clk *clk)
{
return get_rate_per(5);
}
static unsigned long get_rate_otg(struct clk *clk)
{
return 48000000; /* FIXME */
@@ -144,7 +149,7 @@ static void clk_cgcr_disable(struct clk *clk)
__raw_writel(reg, clk->enable_reg);
}
#define DEFINE_CLOCK(name, i, er, es, gr, sr) \
#define DEFINE_CLOCK(name, i, er, es, gr, sr, s) \
static struct clk name = { \
.id = i, \
.enable_reg = CRM_BASE + er, \
@@ -153,27 +158,30 @@ static void clk_cgcr_disable(struct clk *clk)
.set_rate = sr, \
.enable = clk_cgcr_enable, \
.disable = clk_cgcr_disable, \
.secondary = s, \
}
DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_ipg, NULL);
DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL);
DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL);
DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL);
DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL);
DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL);
DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL);
DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL);
DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL);
DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL);
DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL);
DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL);
DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL);
DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL);
DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL);
DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL);
DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL);
DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL);
DEFINE_CLOCK(fec_clk, 0, CCM_CGCR0, 23, get_rate_ipg, NULL);
DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL);
DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk);
DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk);
DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL, NULL);
DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL);
DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL);
DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
#define _REGISTER_CLOCK(d, n, c) \
{ \
@@ -208,13 +216,21 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("fec.0", NULL, fec_clk)
};
int __init mx25_clocks_init(unsigned long fref)
int __init mx25_clocks_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(lookups); i++)
clkdev_add(&lookups[i]);
/* Turn off all clocks except the ones we need to survive, namely:
* EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
* SCC
*/
__raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
__raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
__raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
return 0;

2
arch/arm/mach-mx25/mx25pdk.c
View File

@@ -91,7 +91,7 @@ static void __init mx25pdk_init(void)
static void __init mx25pdk_timer_init(void)
{
mx25_clocks_init(26000000);
mx25_clocks_init();
}
static struct sys_timer mx25pdk_timer = {

4
arch/arm/mach-mx3/mx31ads.c
View File

@@ -173,6 +173,7 @@ static void expio_unmask_irq(u32 irq)
}
static struct irq_chip expio_irq_chip = {
.name = "EXPIO(CPLD)",
.ack = expio_ack_irq,
.mask = expio_mask_irq,
.unmask = expio_unmask_irq,
@@ -302,6 +303,7 @@ static struct regulator_init_data ldo1_data = {
.min_uV = 2800000,
.max_uV = 2800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
},
};
@@ -322,6 +324,7 @@ static struct regulator_init_data ldo2_data = {
.min_uV = 3300000,
.max_uV = 3300000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
},
.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
@@ -459,6 +462,7 @@ static int mx31_wm8350_init(struct wm8350 *wm8350)
static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
.init = mx31_wm8350_init,
.irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
};
#endif

5
arch/arm/mach-omap2/gpmc.c
View File

@@ -505,7 +505,7 @@ static void __init gpmc_mem_init(void)
void __init gpmc_init(void)
{
u32 l;
char *ck;
char *ck = NULL;
if (cpu_is_omap24xx()) {
ck = "core_l3_ck";
@@ -521,6 +521,9 @@ void __init gpmc_init(void)
l = OMAP44XX_GPMC_BASE;
}
if (WARN_ON(!ck))
return;
gpmc_l3_clk = clk_get(NULL, ck);
if (IS_ERR(gpmc_l3_clk)) {
printk(KERN_ERR "Could not get GPMC clock %s\n", ck);

4
arch/arm/mach-omap2/irq.c
View File

@@ -194,7 +194,7 @@ void __init omap_init_irq(void)
int i;
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
unsigned long base;
unsigned long base = 0;
struct omap_irq_bank *bank = irq_banks + i;
if (cpu_is_omap24xx())
@@ -202,6 +202,8 @@ void __init omap_init_irq(void)
else if (cpu_is_omap34xx())
base = OMAP34XX_IC_BASE;
BUG_ON(!base);
/* Static mapping, never released */
bank->base_reg = ioremap(base, SZ_4K);
if (!bank->base_reg) {

10
arch/arm/mach-omap2/mux.c
View File

@@ -486,7 +486,7 @@ int __init omap_mux_init_signal(char *muxname, int val)
static inline void omap_mux_decode(struct seq_file *s, u16 val)
{
char *flags[OMAP_MUX_MAX_NR_FLAGS];
char mode[14];
char mode[sizeof("OMAP_MUX_MODE") + 1];
int i = -1;
sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
@@ -553,6 +553,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
if (!m0_name)
continue;
/* REVISIT: Needs to be updated if mode0 names get longer */
for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
if (m0_name[i] == '\0') {
m0_def[i] = m0_name[i];
@@ -968,6 +969,13 @@ static void __init omap_mux_init_list(struct omap_mux *superset)
}
#endif
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)
if (!superset->muxnames || !superset->muxnames[0]) {
superset++;
continue;
}
#endif
entry = omap_mux_list_add(superset);
if (!entry) {
printk(KERN_ERR "mux: Could not add entry\n");

47
arch/arm/mach-omap2/mux34xx.c
View File

@@ -649,6 +649,53 @@ static struct omap_mux __initdata omap3_muxmodes[] = {
_OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
"uart3_tx_irtx", NULL, NULL, NULL,
"gpio_166", NULL, NULL, "safe_mode"),
/* Only on 3630, see omap36xx_cbp_subset for the signals */
_OMAP3_MUXENTRY(GPMC_A11, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MREAD, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SREAD, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(GPMC_A11, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};

11
arch/arm/mach-omap2/serial.c
View File

@@ -36,7 +36,13 @@
#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
#define UART_OMAP_WER 0x17 /* Wake-up enable register */
#define DEFAULT_TIMEOUT (5 * HZ)
/*
* NOTE: By default the serial timeout is disabled as it causes lost characters
* over the serial ports. This means that the UART clocks will stay on until
* disabled via sysfs. This also causes that any deeper omap sleep states are
* blocked.
*/
#define DEFAULT_TIMEOUT 0
struct omap_uart_state {
int num;
@@ -422,7 +428,8 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
uart->timeout = DEFAULT_TIMEOUT;
setup_timer(&uart->timer, omap_uart_idle_timer,
(unsigned long) uart);
mod_timer(&uart->timer, jiffies + uart->timeout);
if (uart->timeout)
mod_timer(&uart->timer, jiffies + uart->timeout);
omap_uart_smart_idle_enable(uart, 0);
if (cpu_is_omap34xx()) {

4
arch/arm/mach-realview/realview_pbx.c
View File

@@ -334,8 +334,8 @@ static void realview_pbx_reset(char mode)
* in the system FPGA
*/
__raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
__raw_writel(0x0000, reset_ctrl);
__raw_writel(0x0004, reset_ctrl);
__raw_writel(0x00F0, reset_ctrl);
__raw_writel(0x00F4, reset_ctrl);
}
static void __init realview_pbx_init(void)

2
arch/arm/mm/proc-arm6_7.S
View File

@@ -41,7 +41,7 @@ ENTRY(cpu_arm7_dcache_clean_area)
ENTRY(cpu_arm7_data_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
ldr r8, [r0] @ read arm instruction
ldr r8, [r2] @ read arm instruction
tst r8, #1 << 20 @ L = 0 -> write?
orreq r1, r1, #1 << 11 @ yes.
and r7, r8, #15 << 24

137
arch/arm/plat-mxc/audmux-v2.c
View File

@@ -23,6 +23,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <mach/audmux.h>
#include <mach/hardware.h>
@@ -32,6 +33,140 @@ static void __iomem *audmux_base;
#define MXC_AUDMUX_V2_PTCR(x) ((x) * 8)
#define MXC_AUDMUX_V2_PDCR(x) ((x) * 8 + 4)
#ifdef CONFIG_DEBUG_FS
static struct dentry *audmux_debugfs_root;
static int audmux_open_file(struct inode *inode, struct file *file)
{
file->private_data = inode->i_private;
return 0;
}
/* There is an annoying discontinuity in the SSI numbering with regard
* to the Linux number of the devices */
static const char *audmux_port_string(int port)
{
switch (port) {
case MX31_AUDMUX_PORT1_SSI0:
return "imx-ssi.0";
case MX31_AUDMUX_PORT2_SSI1:
return "imx-ssi.1";
case MX31_AUDMUX_PORT3_SSI_PINS_3:
return "SSI3";
case MX31_AUDMUX_PORT4_SSI_PINS_4:
return "SSI4";
case MX31_AUDMUX_PORT5_SSI_PINS_5:
return "SSI5";
case MX31_AUDMUX_PORT6_SSI_PINS_6:
return "SSI6";
default:
return "UNKNOWN";
}
}
static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos)
{
ssize_t ret;
char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
int port = (int)file->private_data;
u32 pdcr, ptcr;
if (!buf)
return -ENOMEM;
if (audmux_clk)
clk_enable(audmux_clk);
ptcr = readl(audmux_base + MXC_AUDMUX_V2_PTCR(port));
pdcr = readl(audmux_base + MXC_AUDMUX_V2_PDCR(port));
if (audmux_clk)
clk_disable(audmux_clk);
ret = snprintf(buf, PAGE_SIZE, "PDCR: %08x\nPTCR: %08x\n",
pdcr, ptcr);
if (ptcr & MXC_AUDMUX_V2_PTCR_TFSDIR)
ret += snprintf(buf + ret, PAGE_SIZE - ret,
"TxFS output from %s, ",
audmux_port_string((ptcr >> 27) & 0x7));
else
ret += snprintf(buf + ret, PAGE_SIZE - ret,
"TxFS input, ");
if (ptcr & MXC_AUDMUX_V2_PTCR_TCLKDIR)
ret += snprintf(buf + ret, PAGE_SIZE - ret,
"TxClk output from %s",
audmux_port_string((ptcr >> 22) & 0x7));
else
ret += snprintf(buf + ret, PAGE_SIZE - ret,
"TxClk input");
ret += snprintf(buf + ret, PAGE_SIZE - ret, "\n");
if (ptcr & MXC_AUDMUX_V2_PTCR_SYN) {
ret += snprintf(buf + ret, PAGE_SIZE - ret,
"Port is symmetric");
} else {
if (ptcr & MXC_AUDMUX_V2_PTCR_RFSDIR)
ret += snprintf(buf + ret, PAGE_SIZE - ret,
"RxFS output from %s, ",
audmux_port_string((ptcr >> 17) & 0x7));
else
ret += snprintf(buf + ret, PAGE_SIZE - ret,
"RxFS input, ");
if (ptcr & MXC_AUDMUX_V2_PTCR_RCLKDIR)
ret += snprintf(buf + ret, PAGE_SIZE - ret,
"RxClk output from %s",
audmux_port_string((ptcr >> 12) & 0x7));
else
ret += snprintf(buf + ret, PAGE_SIZE - ret,
"RxClk input");
}
ret += snprintf(buf + ret, PAGE_SIZE - ret,
"\nData received from %s\n",
audmux_port_string((pdcr >> 13) & 0x7));
ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
kfree(buf);
return ret;
}
static const struct file_operations audmux_debugfs_fops = {
.open = audmux_open_file,
.read = audmux_read_file,
};
static void audmux_debugfs_init(void)
{
int i;
char buf[20];
audmux_debugfs_root = debugfs_create_dir("audmux", NULL);
if (!audmux_debugfs_root) {
pr_warning("Failed to create AUDMUX debugfs root\n");
return;
}
for (i = 1; i < 8; i++) {
snprintf(buf, sizeof(buf), "ssi%d", i);
if (!debugfs_create_file(buf, 0444, audmux_debugfs_root,
(void *)i, &audmux_debugfs_fops))
pr_warning("Failed to create AUDMUX port %d debugfs file\n",
i);
}
}
#else
static inline void audmux_debugfs_init(void)
{
}
#endif
int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
unsigned int pdcr)
{
@@ -68,6 +203,8 @@ static int mxc_audmux_v2_init(void)
if (cpu_is_mx31() || cpu_is_mx35())
audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
audmux_debugfs_init();
return 0;
}

2
arch/arm/plat-mxc/include/mach/board-mx31lite.h
View File

@@ -25,7 +25,7 @@
#ifndef __ASSEMBLY__
enum mx31lilly_boards {
enum mx31lite_boards {
MX31LITE_NOBOARD = 0,
MX31LITE_DB = 1,
};

2
arch/arm/plat-mxc/include/mach/common.h
View File

@@ -32,7 +32,7 @@ extern void mxc91231_init_irq(void);
extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
extern int mx1_clocks_init(unsigned long fref);
extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
extern int mx25_clocks_init(unsigned long fref);
extern int mx25_clocks_init(void);
extern int mx27_clocks_init(unsigned long fref);
extern int mx31_clocks_init(unsigned long fref);
extern int mx35_clocks_init(void);

2
arch/arm/plat-mxc/include/mach/iomux-mx35.h
View File

@@ -671,7 +671,7 @@
#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4 0, NO_PAD_CTRL)
#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL)
#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL)

5
arch/arm/plat-mxc/include/mach/irqs.h
View File

@@ -37,7 +37,12 @@
* within sensible limits.
*/
#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
#define MXC_BOARD_IRQS 80
#else
#define MXC_BOARD_IRQS 16
#endif
#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)

4
arch/arm/plat-omap/clock.c
View File

@@ -391,7 +391,7 @@ static struct dentry *clk_debugfs_root;
static int clk_debugfs_register_one(struct clk *c)
{
int err;
struct dentry *d, *child;
struct dentry *d, *child, *child_tmp;
struct clk *pa = c->parent;
char s[255];
char *p = s;
@@ -423,7 +423,7 @@ static int clk_debugfs_register_one(struct clk *c)
err_out:
d = c->dent;
list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
debugfs_remove(child);
debugfs_remove(c->dent);
return err;

4
arch/arm/plat-omap/gpio.c
View File

@@ -750,6 +750,7 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
}
#endif
#ifdef CONFIG_ARCH_OMAP1
/*
* This only applies to chips that can't do both rising and falling edge
* detection at once. For all other chips, this function is a noop.
@@ -760,11 +761,9 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
u32 l = 0;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
reg += OMAP_MPUIO_GPIO_INT_EDGE;
break;
#endif
#ifdef CONFIG_ARCH_OMAP15XX
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_INT_CONTROL;
@@ -787,6 +786,7 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
__raw_writel(l, reg);
}
#endif
static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
{

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