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https://github.com/Dasharo/linux.git
synced 2026-03-06 15:25:10 -08:00
Merge tag 'soundwire-6.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire
Pull soundwire updates from Vinod Koul: - SoundWire multi lane support to use multiple lanes if supported - Stream handling of DEPREPARED state - AMD wake register programming for power off mode * tag 'soundwire-6.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire: soundwire: amd: clear wake enable register for power off mode soundwire: generic_bandwidth_allocation: count the bandwidth of active streams only SoundWire: pass stream to compute_params() soundwire: generic_bandwidth_allocation: add lane in sdw_group_params soundwire: generic_bandwidth_allocation: select data lane soundwire: generic_bandwidth_allocation: check required freq accurately soundwire: generic_bandwidth_allocation: correct clk_freq check in sdw_select_row_col Soundwire: generic_bandwidth_allocation: set frame shape on fly Soundwire: stream: program BUSCLOCK_SCALE Soundwire: add sdw_slave_get_scale_index helper soundwire: generic_bandwidth_allocation: skip DEPREPARED streams soundwire: stream: set DEPREPARED state earlier soundwire: add lane_used_bandwidth in struct sdw_bus soundwire: mipi_disco: read lane mapping properties from ACPI soundwire: add lane field in sdw_port_runtime soundwire: bus: Move irq mapping cleanup into devres
This commit is contained in:
@@ -384,7 +384,7 @@ static u32 amd_sdw_read_ping_status(struct sdw_bus *bus)
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return slave_stat;
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}
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static int amd_sdw_compute_params(struct sdw_bus *bus)
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static int amd_sdw_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream)
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{
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struct sdw_transport_data t_data = {0};
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struct sdw_master_runtime *m_rt;
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@@ -410,7 +410,7 @@ static int amd_sdw_compute_params(struct sdw_bus *bus)
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sdw_fill_xport_params(&p_rt->transport_params, p_rt->num,
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false, SDW_BLK_GRP_CNT_1, sample_int,
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port_bo, port_bo >> 8, hstart, hstop,
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SDW_BLK_PKG_PER_PORT, 0x0);
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SDW_BLK_PKG_PER_PORT, p_rt->lane);
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sdw_fill_port_params(&p_rt->port_params,
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p_rt->num, bps,
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@@ -1190,6 +1190,7 @@ static int __maybe_unused amd_resume_runtime(struct device *dev)
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if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {
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return amd_sdw_clock_stop_exit(amd_manager);
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} else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
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writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));
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val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
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if (val) {
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val |= AMD_SDW_CLK_RESUME_REQ;
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@@ -813,6 +813,16 @@ void sdw_extract_slave_id(struct sdw_bus *bus,
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}
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EXPORT_SYMBOL(sdw_extract_slave_id);
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bool is_clock_scaling_supported_by_slave(struct sdw_slave *slave)
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{
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/*
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* Dynamic scaling is a defined by SDCA. However, some devices expose the class ID but
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* can't support dynamic scaling. We might need a quirk to handle such devices.
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*/
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return slave->id.class_id;
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}
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EXPORT_SYMBOL(is_clock_scaling_supported_by_slave);
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static int sdw_program_device_num(struct sdw_bus *bus, bool *programmed)
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{
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u8 buf[SDW_NUM_DEV_ID_REGISTERS] = {0};
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@@ -1276,23 +1286,12 @@ int sdw_configure_dpn_intr(struct sdw_slave *slave,
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return ret;
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}
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static int sdw_slave_set_frequency(struct sdw_slave *slave)
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int sdw_slave_get_scale_index(struct sdw_slave *slave, u8 *base)
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{
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u32 mclk_freq = slave->bus->prop.mclk_freq;
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u32 curr_freq = slave->bus->params.curr_dr_freq >> 1;
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unsigned int scale;
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u8 scale_index;
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u8 base;
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int ret;
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/*
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* frequency base and scale registers are required for SDCA
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* devices. They may also be used for 1.2+/non-SDCA devices.
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* Driver can set the property, we will need a DisCo property
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* to discover this case from platform firmware.
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*/
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if (!slave->id.class_id && !slave->prop.clock_reg_supported)
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return 0;
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if (!mclk_freq) {
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dev_err(&slave->dev,
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@@ -1311,19 +1310,19 @@ static int sdw_slave_set_frequency(struct sdw_slave *slave)
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*/
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if (!(19200000 % mclk_freq)) {
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mclk_freq = 19200000;
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base = SDW_SCP_BASE_CLOCK_19200000_HZ;
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*base = SDW_SCP_BASE_CLOCK_19200000_HZ;
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} else if (!(22579200 % mclk_freq)) {
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mclk_freq = 22579200;
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base = SDW_SCP_BASE_CLOCK_22579200_HZ;
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*base = SDW_SCP_BASE_CLOCK_22579200_HZ;
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} else if (!(24576000 % mclk_freq)) {
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mclk_freq = 24576000;
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base = SDW_SCP_BASE_CLOCK_24576000_HZ;
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*base = SDW_SCP_BASE_CLOCK_24576000_HZ;
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} else if (!(32000000 % mclk_freq)) {
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mclk_freq = 32000000;
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base = SDW_SCP_BASE_CLOCK_32000000_HZ;
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*base = SDW_SCP_BASE_CLOCK_32000000_HZ;
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} else if (!(96000000 % mclk_freq)) {
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mclk_freq = 24000000;
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base = SDW_SCP_BASE_CLOCK_24000000_HZ;
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*base = SDW_SCP_BASE_CLOCK_24000000_HZ;
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} else {
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dev_err(&slave->dev,
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"Unsupported clock base, mclk %d\n",
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@@ -1354,6 +1353,34 @@ static int sdw_slave_set_frequency(struct sdw_slave *slave)
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}
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scale_index++;
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dev_dbg(&slave->dev,
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"Configured bus base %d, scale %d, mclk %d, curr_freq %d\n",
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*base, scale_index, mclk_freq, curr_freq);
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return scale_index;
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}
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EXPORT_SYMBOL(sdw_slave_get_scale_index);
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static int sdw_slave_set_frequency(struct sdw_slave *slave)
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{
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int scale_index;
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u8 base;
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int ret;
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/*
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* frequency base and scale registers are required for SDCA
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* devices. They may also be used for 1.2+/non-SDCA devices.
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* Driver can set the property directly, for now there's no
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* DisCo property to discover support for the scaling registers
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* from platform firmware.
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*/
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if (!slave->id.class_id && !slave->prop.clock_reg_supported)
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return 0;
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scale_index = sdw_slave_get_scale_index(slave, &base);
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if (scale_index < 0)
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return scale_index;
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ret = sdw_write_no_pm(slave, SDW_SCP_BUS_CLOCK_BASE, base);
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if (ret < 0) {
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dev_err(&slave->dev,
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@@ -1373,10 +1400,6 @@ static int sdw_slave_set_frequency(struct sdw_slave *slave)
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dev_err(&slave->dev,
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"SDW_SCP_BUSCLOCK_SCALE_B1 write failed:%d\n", ret);
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dev_dbg(&slave->dev,
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"Configured bus base %d, scale %d, mclk %d, curr_freq %d\n",
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base, scale_index, mclk_freq, curr_freq);
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return ret;
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}
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@@ -90,6 +90,7 @@ int sdw_find_col_index(int col);
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* @transport_params: Transport parameters
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* @port_params: Port parameters
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* @port_node: List node for Master or Slave port_list
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* @lane: Which lane is used
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*
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* SoundWire spec has no mention of ports for Master interface but the
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* concept is logically extended.
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@@ -100,6 +101,7 @@ struct sdw_port_runtime {
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struct sdw_transport_params transport_params;
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struct sdw_port_params port_params;
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struct list_head port_node;
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unsigned int lane;
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};
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/**
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@@ -149,6 +151,7 @@ struct sdw_transport_data {
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int hstop;
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int block_offset;
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int sub_block_offset;
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unsigned int lane;
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};
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struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
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@@ -167,9 +167,6 @@ static int sdw_drv_remove(struct device *dev)
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slave->probed = false;
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if (slave->prop.use_domain_irq)
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sdw_irq_dispose_mapping(slave);
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mutex_unlock(&slave->sdw_dev_lock);
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if (drv->remove)
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File diff suppressed because it is too large
Load Diff
@@ -46,14 +46,18 @@ void sdw_irq_delete(struct sdw_bus *bus)
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irq_domain_remove(bus->domain);
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}
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static void sdw_irq_dispose_mapping(void *data)
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{
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struct sdw_slave *slave = data;
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irq_dispose_mapping(irq_find_mapping(slave->bus->domain, slave->dev_num));
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}
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void sdw_irq_create_mapping(struct sdw_slave *slave)
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{
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slave->irq = irq_create_mapping(slave->bus->domain, slave->dev_num);
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if (!slave->irq)
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dev_warn(&slave->dev, "Failed to map IRQ\n");
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}
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void sdw_irq_dispose_mapping(struct sdw_slave *slave)
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{
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irq_dispose_mapping(irq_find_mapping(slave->bus->domain, slave->dev_num));
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devm_add_action_or_reset(&slave->dev, sdw_irq_dispose_mapping, slave);
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}
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@@ -16,7 +16,6 @@ int sdw_irq_create(struct sdw_bus *bus,
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struct fwnode_handle *fwnode);
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void sdw_irq_delete(struct sdw_bus *bus);
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void sdw_irq_create_mapping(struct sdw_slave *slave);
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void sdw_irq_dispose_mapping(struct sdw_slave *slave);
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#else /* CONFIG_IRQ_DOMAIN */
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@@ -34,10 +33,6 @@ static inline void sdw_irq_create_mapping(struct sdw_slave *slave)
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{
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}
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static inline void sdw_irq_dispose_mapping(struct sdw_slave *slave)
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{
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}
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#endif /* CONFIG_IRQ_DOMAIN */
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#endif /* __SDW_IRQ_H */
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@@ -366,6 +366,44 @@ static int sdw_slave_read_dpn(struct sdw_slave *slave,
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return 0;
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}
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/*
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* In MIPI DisCo spec for SoundWire, lane mapping for a slave device is done with
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* mipi-sdw-lane-x-mapping properties, where x is 1..7, and the values for those
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* properties are mipi-sdw-manager-lane-x or mipi-sdw-peripheral-link-y, where x
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* is an integer between 1 to 7 if the lane is connected to a manager lane, y is a
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* character between A to E if the lane is connected to another peripheral lane.
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*/
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int sdw_slave_read_lane_mapping(struct sdw_slave *slave)
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{
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struct sdw_slave_prop *prop = &slave->prop;
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struct device *dev = &slave->dev;
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char prop_name[30];
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const char *prop_val;
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size_t len;
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int ret, i;
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u8 lane;
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for (i = 0; i < SDW_MAX_LANES; i++) {
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snprintf(prop_name, sizeof(prop_name), "mipi-sdw-lane-%d-mapping", i);
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ret = device_property_read_string(dev, prop_name, &prop_val);
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if (ret)
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continue;
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len = strlen(prop_val);
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if (len < 1)
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return -EINVAL;
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/* The last character is enough to identify the connection */
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ret = kstrtou8(&prop_val[len - 1], 10, &lane);
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if (ret)
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return ret;
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if (in_range(lane, 1, SDW_MAX_LANES - 1))
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prop->lane_maps[i] = lane;
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}
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return 0;
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}
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EXPORT_SYMBOL(sdw_slave_read_lane_mapping);
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/**
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* sdw_slave_read_prop() - Read Slave properties
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* @slave: SDW Slave
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@@ -486,6 +524,6 @@ int sdw_slave_read_prop(struct sdw_slave *slave)
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sdw_slave_read_dpn(slave, prop->sink_dpn_prop, nval,
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prop->sink_ports, "sink");
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return 0;
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return sdw_slave_read_lane_mapping(slave);
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}
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EXPORT_SYMBOL(sdw_slave_read_prop);
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@@ -1072,7 +1072,7 @@ static const struct sdw_master_ops qcom_swrm_ops = {
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.pre_bank_switch = qcom_swrm_pre_bank_switch,
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};
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static int qcom_swrm_compute_params(struct sdw_bus *bus)
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static int qcom_swrm_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream)
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{
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struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
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struct sdw_master_runtime *m_rt;
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@@ -629,8 +629,44 @@ static int sdw_notify_config(struct sdw_master_runtime *m_rt)
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static int sdw_program_params(struct sdw_bus *bus, bool prepare)
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{
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struct sdw_master_runtime *m_rt;
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struct sdw_slave *slave;
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int ret = 0;
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u32 addr1;
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/* Check if all Peripherals comply with SDCA */
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list_for_each_entry(slave, &bus->slaves, node) {
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if (!slave->dev_num_sticky)
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continue;
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if (!is_clock_scaling_supported_by_slave(slave)) {
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dev_dbg(&slave->dev, "The Peripheral doesn't comply with SDCA\n");
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goto manager_runtime;
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}
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}
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if (bus->params.next_bank)
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addr1 = SDW_SCP_BUSCLOCK_SCALE_B1;
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else
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addr1 = SDW_SCP_BUSCLOCK_SCALE_B0;
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/* Program SDW_SCP_BUSCLOCK_SCALE if all Peripherals comply with SDCA */
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list_for_each_entry(slave, &bus->slaves, node) {
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int scale_index;
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u8 base;
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if (!slave->dev_num_sticky)
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continue;
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scale_index = sdw_slave_get_scale_index(slave, &base);
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if (scale_index < 0)
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return scale_index;
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ret = sdw_write_no_pm(slave, addr1, scale_index);
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if (ret < 0) {
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dev_err(&slave->dev, "SDW_SCP_BUSCLOCK_SCALE register write failed\n");
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return ret;
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}
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}
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manager_runtime:
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list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
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/*
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@@ -1383,7 +1419,7 @@ static int _sdw_prepare_stream(struct sdw_stream_runtime *stream,
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/* Compute params */
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if (bus->compute_params) {
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ret = bus->compute_params(bus);
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ret = bus->compute_params(bus, stream);
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if (ret < 0) {
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dev_err(bus->dev, "Compute params failed: %d\n",
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ret);
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@@ -1642,9 +1678,19 @@ EXPORT_SYMBOL(sdw_disable_stream);
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static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
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{
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struct sdw_master_runtime *m_rt;
|
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struct sdw_port_runtime *p_rt;
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unsigned int multi_lane_bandwidth;
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unsigned int bandwidth;
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struct sdw_bus *bus;
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int state = stream->state;
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int ret = 0;
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/*
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* first mark the state as DEPREPARED so that it is not taken into account
|
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* for bit allocation
|
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*/
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stream->state = SDW_STREAM_DEPREPARED;
|
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list_for_each_entry(m_rt, &stream->master_list, stream_node) {
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bus = m_rt->bus;
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/* De-prepare port(s) */
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@@ -1652,19 +1698,34 @@ static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
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if (ret < 0) {
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dev_err(bus->dev,
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"De-prepare port(s) failed: %d\n", ret);
|
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stream->state = state;
|
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return ret;
|
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}
|
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|
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multi_lane_bandwidth = 0;
|
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|
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list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
|
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if (!p_rt->lane)
|
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continue;
|
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|
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bandwidth = m_rt->stream->params.rate * hweight32(p_rt->ch_mask) *
|
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m_rt->stream->params.bps;
|
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multi_lane_bandwidth += bandwidth;
|
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bus->lane_used_bandwidth[p_rt->lane] -= bandwidth;
|
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if (!bus->lane_used_bandwidth[p_rt->lane])
|
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p_rt->lane = 0;
|
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}
|
||||
/* TODO: Update this during Device-Device support */
|
||||
bus->params.bandwidth -= m_rt->stream->params.rate *
|
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m_rt->ch_count * m_rt->stream->params.bps;
|
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bandwidth = m_rt->stream->params.rate * m_rt->ch_count * m_rt->stream->params.bps;
|
||||
bus->params.bandwidth -= bandwidth - multi_lane_bandwidth;
|
||||
|
||||
/* Compute params */
|
||||
if (bus->compute_params) {
|
||||
ret = bus->compute_params(bus);
|
||||
ret = bus->compute_params(bus, stream);
|
||||
if (ret < 0) {
|
||||
dev_err(bus->dev, "Compute params failed: %d\n",
|
||||
ret);
|
||||
stream->state = state;
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
@@ -1673,11 +1734,11 @@ static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
|
||||
ret = sdw_program_params(bus, false);
|
||||
if (ret < 0) {
|
||||
dev_err(bus->dev, "%s: Program params failed: %d\n", __func__, ret);
|
||||
stream->state = state;
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
stream->state = SDW_STREAM_DEPREPARED;
|
||||
return do_bank_switch(stream);
|
||||
}
|
||||
|
||||
|
||||
@@ -54,6 +54,8 @@ struct sdw_slave;
|
||||
#define SDW_MAX_PORTS 15
|
||||
#define SDW_VALID_PORT_RANGE(n) ((n) < SDW_MAX_PORTS && (n) >= 1)
|
||||
|
||||
#define SDW_MAX_LANES 8
|
||||
|
||||
enum {
|
||||
SDW_PORT_DIRN_SINK = 0,
|
||||
SDW_PORT_DIRN_SOURCE,
|
||||
@@ -356,6 +358,7 @@ struct sdw_dpn_prop {
|
||||
* and masks are supported
|
||||
* @commit_register_supported: is PCP_Commit register supported
|
||||
* @scp_int1_mask: SCP_INT1_MASK desired settings
|
||||
* @lane_maps: Lane mapping for the slave, only valid if lane_control_support is set
|
||||
* @clock_reg_supported: the Peripheral implements the clock base and scale
|
||||
* registers introduced with the SoundWire 1.2 specification. SDCA devices
|
||||
* do not need to set this boolean property as the registers are required.
|
||||
@@ -385,6 +388,7 @@ struct sdw_slave_prop {
|
||||
u32 sdca_interrupt_register_list;
|
||||
u8 commit_register_supported;
|
||||
u8 scp_int1_mask;
|
||||
u8 lane_maps[SDW_MAX_LANES];
|
||||
bool clock_reg_supported;
|
||||
bool use_domain_irq;
|
||||
};
|
||||
@@ -450,6 +454,7 @@ struct sdw_master_prop {
|
||||
|
||||
int sdw_master_read_prop(struct sdw_bus *bus);
|
||||
int sdw_slave_read_prop(struct sdw_slave *slave);
|
||||
int sdw_slave_read_lane_mapping(struct sdw_slave *slave);
|
||||
|
||||
/*
|
||||
* SDW Slave Structures and APIs
|
||||
@@ -850,77 +855,6 @@ struct sdw_master_ops {
|
||||
int dev_num);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sdw_bus - SoundWire bus
|
||||
* @dev: Shortcut to &bus->md->dev to avoid changing the entire code.
|
||||
* @md: Master device
|
||||
* @bus_lock_key: bus lock key associated to @bus_lock
|
||||
* @bus_lock: bus lock
|
||||
* @slaves: list of Slaves on this bus
|
||||
* @msg_lock_key: message lock key associated to @msg_lock
|
||||
* @msg_lock: message lock
|
||||
* @m_rt_list: List of Master instance of all stream(s) running on Bus. This
|
||||
* is used to compute and program bus bandwidth, clock, frame shape,
|
||||
* transport and port parameters
|
||||
* @defer_msg: Defer message
|
||||
* @params: Current bus parameters
|
||||
* @stream_refcount: number of streams currently using this bus
|
||||
* @ops: Master callback ops
|
||||
* @port_ops: Master port callback ops
|
||||
* @prop: Master properties
|
||||
* @vendor_specific_prop: pointer to non-standard properties
|
||||
* @hw_sync_min_links: Number of links used by a stream above which
|
||||
* hardware-based synchronization is required. This value is only
|
||||
* meaningful if multi_link is set. If set to 1, hardware-based
|
||||
* synchronization will be used even if a stream only uses a single
|
||||
* SoundWire segment.
|
||||
* @controller_id: system-unique controller ID. If set to -1, the bus @id will be used.
|
||||
* @link_id: Link id number, can be 0 to N, unique for each Controller
|
||||
* @id: bus system-wide unique id
|
||||
* @compute_params: points to Bus resource management implementation
|
||||
* @assigned: Bitmap for Slave device numbers.
|
||||
* Bit set implies used number, bit clear implies unused number.
|
||||
* @clk_stop_timeout: Clock stop timeout computed
|
||||
* @bank_switch_timeout: Bank switch timeout computed
|
||||
* @domain: IRQ domain
|
||||
* @irq_chip: IRQ chip
|
||||
* @debugfs: Bus debugfs (optional)
|
||||
* @multi_link: Store bus property that indicates if multi links
|
||||
* are supported. This flag is populated by drivers after reading
|
||||
* appropriate firmware (ACPI/DT).
|
||||
*/
|
||||
struct sdw_bus {
|
||||
struct device *dev;
|
||||
struct sdw_master_device *md;
|
||||
struct lock_class_key bus_lock_key;
|
||||
struct mutex bus_lock;
|
||||
struct list_head slaves;
|
||||
struct lock_class_key msg_lock_key;
|
||||
struct mutex msg_lock;
|
||||
struct list_head m_rt_list;
|
||||
struct sdw_defer defer_msg;
|
||||
struct sdw_bus_params params;
|
||||
int stream_refcount;
|
||||
const struct sdw_master_ops *ops;
|
||||
const struct sdw_master_port_ops *port_ops;
|
||||
struct sdw_master_prop prop;
|
||||
void *vendor_specific_prop;
|
||||
int hw_sync_min_links;
|
||||
int controller_id;
|
||||
unsigned int link_id;
|
||||
int id;
|
||||
int (*compute_params)(struct sdw_bus *bus);
|
||||
DECLARE_BITMAP(assigned, SDW_MAX_DEVICES);
|
||||
unsigned int clk_stop_timeout;
|
||||
u32 bank_switch_timeout;
|
||||
struct irq_chip irq_chip;
|
||||
struct irq_domain *domain;
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
struct dentry *debugfs;
|
||||
#endif
|
||||
bool multi_link;
|
||||
};
|
||||
|
||||
int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent,
|
||||
struct fwnode_handle *fwnode);
|
||||
void sdw_bus_master_delete(struct sdw_bus *bus);
|
||||
@@ -1010,10 +944,83 @@ struct sdw_stream_runtime {
|
||||
struct list_head master_list;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sdw_bus - SoundWire bus
|
||||
* @dev: Shortcut to &bus->md->dev to avoid changing the entire code.
|
||||
* @md: Master device
|
||||
* @bus_lock_key: bus lock key associated to @bus_lock
|
||||
* @bus_lock: bus lock
|
||||
* @slaves: list of Slaves on this bus
|
||||
* @msg_lock_key: message lock key associated to @msg_lock
|
||||
* @msg_lock: message lock
|
||||
* @m_rt_list: List of Master instance of all stream(s) running on Bus. This
|
||||
* is used to compute and program bus bandwidth, clock, frame shape,
|
||||
* transport and port parameters
|
||||
* @defer_msg: Defer message
|
||||
* @params: Current bus parameters
|
||||
* @stream_refcount: number of streams currently using this bus
|
||||
* @ops: Master callback ops
|
||||
* @port_ops: Master port callback ops
|
||||
* @prop: Master properties
|
||||
* @vendor_specific_prop: pointer to non-standard properties
|
||||
* @hw_sync_min_links: Number of links used by a stream above which
|
||||
* hardware-based synchronization is required. This value is only
|
||||
* meaningful if multi_link is set. If set to 1, hardware-based
|
||||
* synchronization will be used even if a stream only uses a single
|
||||
* SoundWire segment.
|
||||
* @controller_id: system-unique controller ID. If set to -1, the bus @id will be used.
|
||||
* @link_id: Link id number, can be 0 to N, unique for each Controller
|
||||
* @id: bus system-wide unique id
|
||||
* @compute_params: points to Bus resource management implementation
|
||||
* @assigned: Bitmap for Slave device numbers.
|
||||
* Bit set implies used number, bit clear implies unused number.
|
||||
* @clk_stop_timeout: Clock stop timeout computed
|
||||
* @bank_switch_timeout: Bank switch timeout computed
|
||||
* @domain: IRQ domain
|
||||
* @irq_chip: IRQ chip
|
||||
* @debugfs: Bus debugfs (optional)
|
||||
* @multi_link: Store bus property that indicates if multi links
|
||||
* are supported. This flag is populated by drivers after reading
|
||||
* appropriate firmware (ACPI/DT).
|
||||
* @lane_used_bandwidth: how much bandwidth in bits per second is used by each lane
|
||||
*/
|
||||
struct sdw_bus {
|
||||
struct device *dev;
|
||||
struct sdw_master_device *md;
|
||||
struct lock_class_key bus_lock_key;
|
||||
struct mutex bus_lock;
|
||||
struct list_head slaves;
|
||||
struct lock_class_key msg_lock_key;
|
||||
struct mutex msg_lock;
|
||||
struct list_head m_rt_list;
|
||||
struct sdw_defer defer_msg;
|
||||
struct sdw_bus_params params;
|
||||
int stream_refcount;
|
||||
const struct sdw_master_ops *ops;
|
||||
const struct sdw_master_port_ops *port_ops;
|
||||
struct sdw_master_prop prop;
|
||||
void *vendor_specific_prop;
|
||||
int hw_sync_min_links;
|
||||
int controller_id;
|
||||
unsigned int link_id;
|
||||
int id;
|
||||
int (*compute_params)(struct sdw_bus *bus, struct sdw_stream_runtime *stream);
|
||||
DECLARE_BITMAP(assigned, SDW_MAX_DEVICES);
|
||||
unsigned int clk_stop_timeout;
|
||||
u32 bank_switch_timeout;
|
||||
struct irq_chip irq_chip;
|
||||
struct irq_domain *domain;
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
struct dentry *debugfs;
|
||||
#endif
|
||||
bool multi_link;
|
||||
unsigned int lane_used_bandwidth[SDW_MAX_LANES];
|
||||
};
|
||||
|
||||
struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name);
|
||||
void sdw_release_stream(struct sdw_stream_runtime *stream);
|
||||
|
||||
int sdw_compute_params(struct sdw_bus *bus);
|
||||
int sdw_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream);
|
||||
|
||||
int sdw_stream_add_master(struct sdw_bus *bus,
|
||||
struct sdw_stream_config *stream_config,
|
||||
@@ -1034,6 +1041,7 @@ int sdw_bus_exit_clk_stop(struct sdw_bus *bus);
|
||||
|
||||
int sdw_compare_devid(struct sdw_slave *slave, struct sdw_slave_id id);
|
||||
void sdw_extract_slave_id(struct sdw_bus *bus, u64 addr, struct sdw_slave_id *id);
|
||||
bool is_clock_scaling_supported_by_slave(struct sdw_slave *slave);
|
||||
|
||||
#if IS_ENABLED(CONFIG_SOUNDWIRE)
|
||||
|
||||
@@ -1045,6 +1053,8 @@ int sdw_stream_add_slave(struct sdw_slave *slave,
|
||||
int sdw_stream_remove_slave(struct sdw_slave *slave,
|
||||
struct sdw_stream_runtime *stream);
|
||||
|
||||
int sdw_slave_get_scale_index(struct sdw_slave *slave, u8 *base);
|
||||
|
||||
/* messaging and data APIs */
|
||||
int sdw_read(struct sdw_slave *slave, u32 addr);
|
||||
int sdw_write(struct sdw_slave *slave, u32 addr, u8 value);
|
||||
|
||||
Reference in New Issue
Block a user