mirror of
https://github.com/Dasharo/linux.git
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Merge tag 'drm-misc-next-2020-09-21' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for 5.10:
UAPI Changes:
Cross-subsystem Changes:
- virtio: Merged a PR for patches that will affect drm/virtio
Core Changes:
- dev: More devm_drm convertions and removal of drm_dev_init
- atomic: Split out drm_atomic_helper_calc_timestamping_constants of
drm_atomic_helper_update_legacy_modeset_state
- ttm: More rework
Driver Changes:
- i915: selftests improvements
- panfrost: support for Amlogic SoC
- vc4: one fix
- tree-wide: conversions to devm_drm_dev_alloc,
- ast: simplifications of the atomic modesetting code
- panfrost: multiple fixes
- vc4: multiple fixes
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20200921152956.2gxnsdgxmwhvjyut@gilmour.lan
This commit is contained in:
Dave Airlie
117
Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
Normal file
117
Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
Normal file
@@ -0,0 +1,117 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM2711 HDMI Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Eric Anholt <eric@anholt.net>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,bcm2711-hdmi0
|
||||
- brcm,bcm2711-hdmi1
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: HDMI controller register range
|
||||
- description: DVP register range
|
||||
- description: HDMI PHY register range
|
||||
- description: Rate Manager register range
|
||||
- description: Packet RAM register range
|
||||
- description: Metadata RAM register range
|
||||
- description: CSC register range
|
||||
- description: CEC register range
|
||||
- description: HD register range
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: hdmi
|
||||
- const: dvp
|
||||
- const: phy
|
||||
- const: rm
|
||||
- const: packet
|
||||
- const: metadata
|
||||
- const: csc
|
||||
- const: cec
|
||||
- const: hd
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: The HDMI state machine clock
|
||||
- description: The Pixel BVB clock
|
||||
- description: The HDMI Audio parent clock
|
||||
- description: The HDMI CEC parent clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: hdmi
|
||||
- const: bvb
|
||||
- const: audio
|
||||
- const: cec
|
||||
|
||||
ddc:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: >
|
||||
Phandle of the I2C controller used for DDC EDID probing
|
||||
|
||||
hpd-gpios:
|
||||
description: >
|
||||
The GPIO pin for the HDMI hotplug detect (if it doesn't appear
|
||||
as an interrupt/status bit in the HDMI controller itself)
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
description: >
|
||||
Should contain one entry pointing to the DMA channel used to
|
||||
transfer audio data.
|
||||
|
||||
dma-names:
|
||||
const: audio-rx
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- resets
|
||||
- ddc
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
hdmi0: hdmi@7ef00700 {
|
||||
compatible = "brcm,bcm2711-hdmi0";
|
||||
reg = <0x7ef00700 0x300>,
|
||||
<0x7ef00300 0x200>,
|
||||
<0x7ef00f00 0x80>,
|
||||
<0x7ef00f80 0x80>,
|
||||
<0x7ef01b00 0x200>,
|
||||
<0x7ef01f00 0x400>,
|
||||
<0x7ef00200 0x80>,
|
||||
<0x7ef04300 0x100>,
|
||||
<0x7ef20000 0x100>;
|
||||
reg-names = "hdmi",
|
||||
"dvp",
|
||||
"phy",
|
||||
"rm",
|
||||
"packet",
|
||||
"metadata",
|
||||
"csc",
|
||||
"cec",
|
||||
"hd";
|
||||
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
|
||||
clock-names = "hdmi", "bvb", "audio", "cec";
|
||||
resets = <&dvp 0>;
|
||||
ddc = <&ddc0>;
|
||||
};
|
||||
|
||||
...
|
||||
@@ -11,7 +11,9 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,bcm2835-hvs
|
||||
enum:
|
||||
- brcm,bcm2711-hvs
|
||||
- brcm,bcm2835-hvs
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -19,6 +21,10 @@ properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: Core Clock
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@@ -26,6 +32,16 @@ required:
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,bcm2711-hvs"
|
||||
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
hvs@7e400000 {
|
||||
|
||||
@@ -15,6 +15,11 @@ properties:
|
||||
- brcm,bcm2835-pixelvalve0
|
||||
- brcm,bcm2835-pixelvalve1
|
||||
- brcm,bcm2835-pixelvalve2
|
||||
- brcm,bcm2711-pixelvalve0
|
||||
- brcm,bcm2711-pixelvalve1
|
||||
- brcm,bcm2711-pixelvalve2
|
||||
- brcm,bcm2711-pixelvalve3
|
||||
- brcm,bcm2711-pixelvalve4
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -17,6 +17,7 @@ description: >
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,bcm2711-vc5
|
||||
- brcm,bcm2835-vc4
|
||||
- brcm,cygnus-vc4
|
||||
|
||||
|
||||
@@ -0,0 +1,108 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
# Copyright 2019 NXP
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: iMX8MQ Display Controller Subsystem (DCSS)
|
||||
|
||||
maintainers:
|
||||
- Laurentiu Palcu <laurentiu.palcu@nxp.com>
|
||||
|
||||
description:
|
||||
|
||||
The DCSS (display controller sub system) is used to source up to three
|
||||
display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
|
||||
2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
|
||||
image processing capabilities are included to provide a solution capable of
|
||||
driving next generation high dynamic range displays.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nxp,imx8mq-dcss
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: DCSS base address and size, up to IRQ steer start
|
||||
- description: DCSS BLKCTL base address and size
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: Context loader completion and error interrupt
|
||||
- description: DTG interrupt used to signal context loader trigger time
|
||||
- description: DTG interrupt for Vblank
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: ctxld
|
||||
- const: ctxld_kick
|
||||
- const: vblank
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display APB clock for all peripheral PIO access interfaces
|
||||
- description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
|
||||
- description: RTRAM clock
|
||||
- description: Pixel clock, can be driven either by HDMI phy clock or MIPI
|
||||
- description: DTRC clock, needed by video decompressor
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: apb
|
||||
- const: axi
|
||||
- const: rtrm
|
||||
- const: pix
|
||||
- const: dtrc
|
||||
|
||||
assigned-clocks:
|
||||
items:
|
||||
- description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
|
||||
- description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
|
||||
- description: Phandle and clock specifier of either IMX8MQ_VIDEO2_PLL1_REF_SEL or
|
||||
IMX8MQ_VIDEO_PLL1_REF_SEL
|
||||
|
||||
assigned-clock-parents:
|
||||
items:
|
||||
- description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
|
||||
- description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
|
||||
- description: Phandle and clock specifier of IMX8MQ_CLK_27M
|
||||
|
||||
assigned-clock-rates:
|
||||
items:
|
||||
- description: Must be 800 MHz
|
||||
- description: Must be 400 MHz
|
||||
|
||||
port:
|
||||
type: object
|
||||
description:
|
||||
A port node pointing to the input port of a HDMI/DP or MIPI display bridge.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx8mq-clock.h>
|
||||
dcss: display-controller@32e00000 {
|
||||
compatible = "nxp,imx8mq-dcss";
|
||||
reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
|
||||
interrupts = <6>, <8>, <9>;
|
||||
interrupt-names = "ctxld", "ctxld_kick", "vblank";
|
||||
interrupt-parent = <&irqsteer>;
|
||||
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
|
||||
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>,
|
||||
<&clk IMX8MQ_CLK_DISP_DTRC>;
|
||||
clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,
|
||||
<&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
|
||||
<&clk IMX8MQ_CLK_27M>;
|
||||
assigned-clock-rates = <800000000>,
|
||||
<400000000>;
|
||||
port {
|
||||
dcss_out: endpoint {
|
||||
remote-endpoint = <&hdmi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -19,6 +19,7 @@ Optional properties:
|
||||
- vbat-supply: The supply for VBAT
|
||||
- solomon,segment-no-remap: Display needs normal (non-inverted) data column
|
||||
to segment mapping
|
||||
- solomon,col-offset: Offset of columns (COL/SEG) that the screen is mapped to.
|
||||
- solomon,com-seq: Display uses sequential COM pin configuration
|
||||
- solomon,com-lrremap: Display uses left-right COM pin remap
|
||||
- solomon,com-invdir: Display uses inverted COM pin scan direction
|
||||
|
||||
@@ -263,7 +263,7 @@ DMA
|
||||
dmam_pool_destroy()
|
||||
|
||||
DRM
|
||||
devm_drm_dev_init()
|
||||
devm_drm_dev_alloc()
|
||||
|
||||
GPIO
|
||||
devm_gpiod_get()
|
||||
|
||||
@@ -20,8 +20,8 @@ A. Configuration
|
||||
================
|
||||
|
||||
The framebuffer console can be enabled by using your favorite kernel
|
||||
configuration tool. It is under Device Drivers->Graphics Support->Frame
|
||||
buffer Devices->Console display driver support->Framebuffer Console Support.
|
||||
configuration tool. It is under Device Drivers->Graphics Support->
|
||||
Console display driver support->Framebuffer Console Support.
|
||||
Select 'y' to compile support statically or 'm' for module support. The
|
||||
module will be fbcon.
|
||||
|
||||
|
||||
@@ -356,8 +356,6 @@ Code Seq# Include File Comments
|
||||
0xEC 00-01 drivers/platform/chrome/cros_ec_dev.h ChromeOS EC driver
|
||||
0xF3 00-3F drivers/usb/misc/sisusbvga/sisusb.h sisfb (in development)
|
||||
<mailto:thomas@winischhofer.net>
|
||||
0xF4 00-1F video/mbxfb.h mbxfb
|
||||
<mailto:raph@8d.com>
|
||||
0xF6 all LTTng Linux Trace Toolkit Next Generation
|
||||
<mailto:mathieu.desnoyers@efficios.com>
|
||||
0xFD all linux/dm-ioctl.h
|
||||
|
||||
24
MAINTAINERS
24
MAINTAINERS
@@ -5411,7 +5411,7 @@ F: drivers/gpu/drm/panel/panel-arm-versatile.c
|
||||
|
||||
DRM DRIVER FOR ASPEED BMC GFX
|
||||
M: Joel Stanley <joel@jms.id.au>
|
||||
L: linux-aspeed@lists.ozlabs.org
|
||||
L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
F: Documentation/devicetree/bindings/gpu/aspeed-gfx.txt
|
||||
@@ -5419,7 +5419,10 @@ F: drivers/gpu/drm/aspeed/
|
||||
|
||||
DRM DRIVER FOR AST SERVER GRAPHICS CHIPS
|
||||
M: Dave Airlie <airlied@redhat.com>
|
||||
S: Odd Fixes
|
||||
R: Thomas Zimmermann <tzimmermann@suse.de>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Supported
|
||||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
F: drivers/gpu/drm/ast/
|
||||
|
||||
DRM DRIVER FOR BOCHS VIRTUAL GPU
|
||||
@@ -5507,7 +5510,10 @@ F: include/uapi/drm/mga_drm.h
|
||||
|
||||
DRM DRIVER FOR MGA G200 GRAPHICS CHIPS
|
||||
M: Dave Airlie <airlied@redhat.com>
|
||||
S: Odd Fixes
|
||||
R: Thomas Zimmermann <tzimmermann@suse.de>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Supported
|
||||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
F: drivers/gpu/drm/mgag200/
|
||||
|
||||
DRM DRIVER FOR MI0283QT
|
||||
@@ -5652,13 +5658,15 @@ F: drivers/gpu/drm/panel/panel-tpo-tpg110.c
|
||||
DRM DRIVER FOR USB DISPLAYLINK VIDEO ADAPTERS
|
||||
M: Dave Airlie <airlied@redhat.com>
|
||||
R: Sean Paul <sean@poorly.run>
|
||||
R: Thomas Zimmermann <tzimmermann@suse.de>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Odd Fixes
|
||||
S: Supported
|
||||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
F: drivers/gpu/drm/udl/
|
||||
|
||||
DRM DRIVER FOR VIRTUAL KERNEL MODESETTING (VKMS)
|
||||
M: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
|
||||
M: Melissa Wen <melissa.srw@gmail.com>
|
||||
R: Haneen Mohammed <hamohammed.sa@gmail.com>
|
||||
R: Daniel Vetter <daniel@ffwll.ch>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
@@ -12462,6 +12470,14 @@ F: drivers/iio/gyro/fxas21002c_core.c
|
||||
F: drivers/iio/gyro/fxas21002c_i2c.c
|
||||
F: drivers/iio/gyro/fxas21002c_spi.c
|
||||
|
||||
NXP i.MX 8MQ DCSS DRIVER
|
||||
M: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
|
||||
R: Lucas Stach <l.stach@pengutronix.de>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
|
||||
F: drivers/gpu/drm/imx/dcss/
|
||||
|
||||
NXP SGTL5000 DRIVER
|
||||
M: Fabio Estevam <festevam@gmail.com>
|
||||
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
|
||||
|
||||
@@ -283,6 +283,7 @@ EXPORT_SYMBOL(dma_fence_begin_signalling);
|
||||
|
||||
/**
|
||||
* dma_fence_end_signalling - end a critical DMA fence signalling section
|
||||
* @cookie: opaque cookie from dma_fence_begin_signalling()
|
||||
*
|
||||
* Closes a critical section annotation opened by dma_fence_begin_signalling().
|
||||
*/
|
||||
|
||||
@@ -98,12 +98,14 @@ static int __init dma_resv_lockdep(void)
|
||||
struct mm_struct *mm = mm_alloc();
|
||||
struct ww_acquire_ctx ctx;
|
||||
struct dma_resv obj;
|
||||
struct address_space mapping;
|
||||
int ret;
|
||||
|
||||
if (!mm)
|
||||
return -ENOMEM;
|
||||
|
||||
dma_resv_init(&obj);
|
||||
address_space_init_once(&mapping);
|
||||
|
||||
mmap_read_lock(mm);
|
||||
ww_acquire_init(&ctx, &reservation_ww_class);
|
||||
@@ -111,6 +113,9 @@ static int __init dma_resv_lockdep(void)
|
||||
if (ret == -EDEADLK)
|
||||
dma_resv_lock_slow(&obj, &ctx);
|
||||
fs_reclaim_acquire(GFP_KERNEL);
|
||||
/* for unmap_mapping_range on trylocked buffer objects in shrinkers */
|
||||
i_mmap_lock_write(&mapping);
|
||||
i_mmap_unlock_write(&mapping);
|
||||
#ifdef CONFIG_MMU_NOTIFIER
|
||||
lock_map_acquire(&__mmu_notifier_invalidate_range_start_map);
|
||||
__dma_fence_might_wait();
|
||||
|
||||
@@ -307,6 +307,9 @@ static long udmabuf_ioctl(struct file *filp, unsigned int ioctl,
|
||||
static const struct file_operations udmabuf_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.unlocked_ioctl = udmabuf_ioctl,
|
||||
#ifdef CONFIG_COMPAT
|
||||
.compat_ioctl = udmabuf_ioctl,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct miscdevice udmabuf_misc = {
|
||||
|
||||
@@ -100,7 +100,7 @@ obj-$(CONFIG_DRM_MSM) += msm/
|
||||
obj-$(CONFIG_DRM_TEGRA) += tegra/
|
||||
obj-$(CONFIG_DRM_STM) += stm/
|
||||
obj-$(CONFIG_DRM_STI) += sti/
|
||||
obj-$(CONFIG_DRM_IMX) += imx/
|
||||
obj-y += imx/
|
||||
obj-$(CONFIG_DRM_INGENIC) += ingenic/
|
||||
obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
|
||||
obj-$(CONFIG_DRM_MESON) += meson/
|
||||
|
||||
@@ -303,7 +303,8 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
|
||||
|
||||
switch (bo->tbo.mem.mem_type) {
|
||||
case TTM_PL_TT:
|
||||
sgt = drm_prime_pages_to_sg(bo->tbo.ttm->pages,
|
||||
sgt = drm_prime_pages_to_sg(obj->dev,
|
||||
bo->tbo.ttm->pages,
|
||||
bo->tbo.num_pages);
|
||||
if (IS_ERR(sgt))
|
||||
return sgt;
|
||||
|
||||
@@ -1159,25 +1159,20 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
|
||||
if (!adev)
|
||||
return -ENOMEM;
|
||||
adev = devm_drm_dev_alloc(&pdev->dev, &kms_driver, typeof(*adev), ddev);
|
||||
if (IS_ERR(adev))
|
||||
return PTR_ERR(adev);
|
||||
|
||||
adev->dev = &pdev->dev;
|
||||
adev->pdev = pdev;
|
||||
ddev = adev_to_drm(adev);
|
||||
ret = drm_dev_init(ddev, &kms_driver, &pdev->dev);
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
drmm_add_final_kfree(ddev, adev);
|
||||
|
||||
if (!supports_atomic)
|
||||
ddev->driver_features &= ~DRIVER_ATOMIC;
|
||||
|
||||
ret = pci_enable_device(pdev);
|
||||
if (ret)
|
||||
goto err_free;
|
||||
return ret;
|
||||
|
||||
ddev->pdev = pdev;
|
||||
pci_set_drvdata(pdev, ddev);
|
||||
@@ -1205,8 +1200,6 @@ retry_init:
|
||||
|
||||
err_pci:
|
||||
pci_disable_device(pdev);
|
||||
err_free:
|
||||
drm_dev_put(ddev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -1223,7 +1216,6 @@ amdgpu_pci_remove(struct pci_dev *pdev)
|
||||
amdgpu_driver_unload_kms(dev);
|
||||
pci_disable_device(pdev);
|
||||
pci_set_drvdata(pdev, NULL);
|
||||
drm_dev_put(dev);
|
||||
}
|
||||
|
||||
static void
|
||||
|
||||
@@ -95,8 +95,6 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size)
|
||||
|
||||
man->use_tt = true;
|
||||
man->func = &amdgpu_gtt_mgr_func;
|
||||
man->available_caching = TTM_PL_MASK_CACHING;
|
||||
man->default_caching = TTM_PL_FLAG_CACHED;
|
||||
|
||||
ttm_resource_manager_init(man, gtt_size >> PAGE_SHIFT);
|
||||
|
||||
|
||||
@@ -136,8 +136,8 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
|
||||
|
||||
places[c].fpfn = 0;
|
||||
places[c].lpfn = 0;
|
||||
places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
|
||||
TTM_PL_FLAG_VRAM;
|
||||
places[c].mem_type = TTM_PL_VRAM;
|
||||
places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
|
||||
|
||||
if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
|
||||
places[c].lpfn = visible_pfn;
|
||||
@@ -152,7 +152,8 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
|
||||
if (domain & AMDGPU_GEM_DOMAIN_GTT) {
|
||||
places[c].fpfn = 0;
|
||||
places[c].lpfn = 0;
|
||||
places[c].flags = TTM_PL_FLAG_TT;
|
||||
places[c].mem_type = TTM_PL_TT;
|
||||
places[c].flags = 0;
|
||||
if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
|
||||
places[c].flags |= TTM_PL_FLAG_WC |
|
||||
TTM_PL_FLAG_UNCACHED;
|
||||
@@ -164,7 +165,8 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
|
||||
if (domain & AMDGPU_GEM_DOMAIN_CPU) {
|
||||
places[c].fpfn = 0;
|
||||
places[c].lpfn = 0;
|
||||
places[c].flags = TTM_PL_FLAG_SYSTEM;
|
||||
places[c].mem_type = TTM_PL_SYSTEM;
|
||||
places[c].flags = 0;
|
||||
if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
|
||||
places[c].flags |= TTM_PL_FLAG_WC |
|
||||
TTM_PL_FLAG_UNCACHED;
|
||||
@@ -176,28 +178,32 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
|
||||
if (domain & AMDGPU_GEM_DOMAIN_GDS) {
|
||||
places[c].fpfn = 0;
|
||||
places[c].lpfn = 0;
|
||||
places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
|
||||
places[c].mem_type = AMDGPU_PL_GDS;
|
||||
places[c].flags = TTM_PL_FLAG_UNCACHED;
|
||||
c++;
|
||||
}
|
||||
|
||||
if (domain & AMDGPU_GEM_DOMAIN_GWS) {
|
||||
places[c].fpfn = 0;
|
||||
places[c].lpfn = 0;
|
||||
places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
|
||||
places[c].mem_type = AMDGPU_PL_GWS;
|
||||
places[c].flags = TTM_PL_FLAG_UNCACHED;
|
||||
c++;
|
||||
}
|
||||
|
||||
if (domain & AMDGPU_GEM_DOMAIN_OA) {
|
||||
places[c].fpfn = 0;
|
||||
places[c].lpfn = 0;
|
||||
places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
|
||||
places[c].mem_type = AMDGPU_PL_OA;
|
||||
places[c].flags = TTM_PL_FLAG_UNCACHED;
|
||||
c++;
|
||||
}
|
||||
|
||||
if (!c) {
|
||||
places[c].fpfn = 0;
|
||||
places[c].lpfn = 0;
|
||||
places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
|
||||
places[c].mem_type = TTM_PL_SYSTEM;
|
||||
places[c].flags = TTM_PL_MASK_CACHING;
|
||||
c++;
|
||||
}
|
||||
|
||||
@@ -594,7 +600,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
|
||||
amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
|
||||
|
||||
if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
|
||||
bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
|
||||
bo->tbo.mem.mem_type == TTM_PL_VRAM) {
|
||||
struct dma_fence *fence;
|
||||
|
||||
r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);
|
||||
|
||||
@@ -63,12 +63,15 @@
|
||||
|
||||
#define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128
|
||||
|
||||
static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
|
||||
struct ttm_tt *ttm,
|
||||
struct ttm_resource *bo_mem);
|
||||
|
||||
static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
|
||||
unsigned int type,
|
||||
uint64_t size)
|
||||
{
|
||||
return ttm_range_man_init(&adev->mman.bdev, type,
|
||||
TTM_PL_FLAG_UNCACHED, TTM_PL_FLAG_UNCACHED,
|
||||
false, size >> PAGE_SHIFT);
|
||||
}
|
||||
|
||||
@@ -88,7 +91,8 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
|
||||
static const struct ttm_place placements = {
|
||||
.fpfn = 0,
|
||||
.lpfn = 0,
|
||||
.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
|
||||
.mem_type = TTM_PL_SYSTEM,
|
||||
.flags = TTM_PL_MASK_CACHING
|
||||
};
|
||||
|
||||
/* Don't handle scatter gather BOs */
|
||||
@@ -174,24 +178,6 @@ static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
|
||||
filp->private_data);
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_move_null - Register memory for a buffer object
|
||||
*
|
||||
* @bo: The bo to assign the memory to
|
||||
* @new_mem: The memory to be assigned.
|
||||
*
|
||||
* Assign the memory from new_mem to the memory of the buffer object bo.
|
||||
*/
|
||||
static void amdgpu_move_null(struct ttm_buffer_object *bo,
|
||||
struct ttm_resource *new_mem)
|
||||
{
|
||||
struct ttm_resource *old_mem = &bo->mem;
|
||||
|
||||
BUG_ON(old_mem->mm_node != NULL);
|
||||
*old_mem = *new_mem;
|
||||
new_mem->mm_node = NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
|
||||
*
|
||||
@@ -514,9 +500,9 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
|
||||
|
||||
/* Always block for VM page tables before committing the new location */
|
||||
if (bo->type == ttm_bo_type_kernel)
|
||||
r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
|
||||
r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
|
||||
else
|
||||
r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
|
||||
r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
|
||||
dma_fence_put(fence);
|
||||
return r;
|
||||
|
||||
@@ -551,7 +537,8 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
|
||||
placement.busy_placement = &placements;
|
||||
placements.fpfn = 0;
|
||||
placements.lpfn = 0;
|
||||
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
|
||||
placements.mem_type = TTM_PL_TT;
|
||||
placements.flags = TTM_PL_MASK_CACHING;
|
||||
r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
|
||||
if (unlikely(r)) {
|
||||
pr_err("Failed to find GTT space for blit from VRAM\n");
|
||||
@@ -564,8 +551,12 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
|
||||
goto out_cleanup;
|
||||
}
|
||||
|
||||
r = ttm_tt_populate(bo->bdev, bo->ttm, ctx);
|
||||
if (unlikely(r))
|
||||
goto out_cleanup;
|
||||
|
||||
/* Bind the memory to the GTT space */
|
||||
r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
|
||||
r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem);
|
||||
if (unlikely(r)) {
|
||||
goto out_cleanup;
|
||||
}
|
||||
@@ -607,7 +598,8 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
|
||||
placement.busy_placement = &placements;
|
||||
placements.fpfn = 0;
|
||||
placements.lpfn = 0;
|
||||
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
|
||||
placements.mem_type = TTM_PL_TT;
|
||||
placements.flags = TTM_PL_MASK_CACHING;
|
||||
r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
|
||||
if (unlikely(r)) {
|
||||
pr_err("Failed to find GTT space for blit to VRAM\n");
|
||||
@@ -676,7 +668,7 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
|
||||
adev = amdgpu_ttm_adev(bo->bdev);
|
||||
|
||||
if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
|
||||
amdgpu_move_null(bo, new_mem);
|
||||
ttm_bo_move_null(bo, new_mem);
|
||||
return 0;
|
||||
}
|
||||
if ((old_mem->mem_type == TTM_PL_TT &&
|
||||
@@ -684,7 +676,7 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
|
||||
(old_mem->mem_type == TTM_PL_SYSTEM &&
|
||||
new_mem->mem_type == TTM_PL_TT)) {
|
||||
/* bind is enough */
|
||||
amdgpu_move_null(bo, new_mem);
|
||||
ttm_bo_move_null(bo, new_mem);
|
||||
return 0;
|
||||
}
|
||||
if (old_mem->mem_type == AMDGPU_PL_GDS ||
|
||||
@@ -694,7 +686,7 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
|
||||
new_mem->mem_type == AMDGPU_PL_GWS ||
|
||||
new_mem->mem_type == AMDGPU_PL_OA) {
|
||||
/* Nothing to save here */
|
||||
amdgpu_move_null(bo, new_mem);
|
||||
ttm_bo_move_null(bo, new_mem);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -773,7 +765,7 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso
|
||||
mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
|
||||
mem->bus.offset;
|
||||
|
||||
mem->bus.base = adev->gmc.aper_base;
|
||||
mem->bus.offset += adev->gmc.aper_base;
|
||||
mem->bus.is_iomem = true;
|
||||
break;
|
||||
default:
|
||||
@@ -785,12 +777,13 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso
|
||||
static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
|
||||
unsigned long page_offset)
|
||||
{
|
||||
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
|
||||
uint64_t offset = (page_offset << PAGE_SHIFT);
|
||||
struct drm_mm_node *mm;
|
||||
|
||||
mm = amdgpu_find_mm_node(&bo->mem, &offset);
|
||||
return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
|
||||
(offset >> PAGE_SHIFT);
|
||||
offset += adev->gmc.aper_base;
|
||||
return mm->start + (offset >> PAGE_SHIFT);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -824,6 +817,7 @@ struct amdgpu_ttm_tt {
|
||||
uint64_t userptr;
|
||||
struct task_struct *usertask;
|
||||
uint32_t userflags;
|
||||
bool bound;
|
||||
#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
|
||||
struct hmm_range *range;
|
||||
#endif
|
||||
@@ -991,9 +985,10 @@ void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
|
||||
*
|
||||
* Called by amdgpu_ttm_backend_bind()
|
||||
**/
|
||||
static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
|
||||
static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
|
||||
struct ttm_tt *ttm)
|
||||
{
|
||||
struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
|
||||
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
|
||||
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
||||
int r;
|
||||
|
||||
@@ -1028,9 +1023,10 @@ release_sg:
|
||||
/**
|
||||
* amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
|
||||
*/
|
||||
static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
|
||||
static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev,
|
||||
struct ttm_tt *ttm)
|
||||
{
|
||||
struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
|
||||
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
|
||||
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
||||
|
||||
int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
|
||||
@@ -1111,16 +1107,23 @@ gart_bind_fail:
|
||||
* Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
|
||||
* This handles binding GTT memory to the device address space.
|
||||
*/
|
||||
static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
|
||||
static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
|
||||
struct ttm_tt *ttm,
|
||||
struct ttm_resource *bo_mem)
|
||||
{
|
||||
struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
|
||||
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
|
||||
struct amdgpu_ttm_tt *gtt = (void*)ttm;
|
||||
uint64_t flags;
|
||||
int r = 0;
|
||||
|
||||
if (!bo_mem)
|
||||
return -EINVAL;
|
||||
|
||||
if (gtt->bound)
|
||||
return 0;
|
||||
|
||||
if (gtt->userptr) {
|
||||
r = amdgpu_ttm_tt_pin_userptr(ttm);
|
||||
r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
|
||||
if (r) {
|
||||
DRM_ERROR("failed to pin userptr\n");
|
||||
return r;
|
||||
@@ -1152,6 +1155,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
|
||||
if (r)
|
||||
DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
|
||||
ttm->num_pages, gtt->offset);
|
||||
gtt->bound = true;
|
||||
return r;
|
||||
}
|
||||
|
||||
@@ -1191,8 +1195,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
|
||||
placement.busy_placement = &placements;
|
||||
placements.fpfn = 0;
|
||||
placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
|
||||
placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
|
||||
TTM_PL_FLAG_TT;
|
||||
placements.mem_type = TTM_PL_TT;
|
||||
placements.flags = bo->mem.placement;
|
||||
|
||||
r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
|
||||
if (unlikely(r))
|
||||
@@ -1243,15 +1247,19 @@ int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
|
||||
* Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
|
||||
* ttm_tt_destroy().
|
||||
*/
|
||||
static void amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
|
||||
static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
|
||||
struct ttm_tt *ttm)
|
||||
{
|
||||
struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
|
||||
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
|
||||
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
||||
int r;
|
||||
|
||||
if (!gtt->bound)
|
||||
return;
|
||||
|
||||
/* if the pages have userptr pinning then clear that first */
|
||||
if (gtt->userptr)
|
||||
amdgpu_ttm_tt_unpin_userptr(ttm);
|
||||
amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
|
||||
|
||||
if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
|
||||
return;
|
||||
@@ -1261,12 +1269,16 @@ static void amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
|
||||
if (r)
|
||||
DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
|
||||
gtt->ttm.ttm.num_pages, gtt->offset);
|
||||
gtt->bound = false;
|
||||
}
|
||||
|
||||
static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
|
||||
static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev,
|
||||
struct ttm_tt *ttm)
|
||||
{
|
||||
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
||||
|
||||
amdgpu_ttm_backend_unbind(bdev, ttm);
|
||||
ttm_tt_destroy_common(bdev, ttm);
|
||||
if (gtt->usertask)
|
||||
put_task_struct(gtt->usertask);
|
||||
|
||||
@@ -1274,12 +1286,6 @@ static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
|
||||
kfree(gtt);
|
||||
}
|
||||
|
||||
static struct ttm_backend_func amdgpu_backend_func = {
|
||||
.bind = &amdgpu_ttm_backend_bind,
|
||||
.unbind = &amdgpu_ttm_backend_unbind,
|
||||
.destroy = &amdgpu_ttm_backend_destroy,
|
||||
};
|
||||
|
||||
/**
|
||||
* amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
|
||||
*
|
||||
@@ -1296,7 +1302,6 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
|
||||
if (gtt == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
gtt->ttm.ttm.func = &amdgpu_backend_func;
|
||||
gtt->gobj = &bo->base;
|
||||
|
||||
/* allocate space for the uninitialized page entries */
|
||||
@@ -1313,10 +1318,11 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
|
||||
* Map the pages of a ttm_tt object to an address space visible
|
||||
* to the underlying device.
|
||||
*/
|
||||
static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
|
||||
struct ttm_operation_ctx *ctx)
|
||||
static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev,
|
||||
struct ttm_tt *ttm,
|
||||
struct ttm_operation_ctx *ctx)
|
||||
{
|
||||
struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
|
||||
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
|
||||
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
||||
|
||||
/* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
|
||||
@@ -1326,7 +1332,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
|
||||
return -ENOMEM;
|
||||
|
||||
ttm->page_flags |= TTM_PAGE_FLAG_SG;
|
||||
ttm->state = tt_unbound;
|
||||
ttm_tt_set_populated(ttm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1346,7 +1352,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
|
||||
drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
|
||||
gtt->ttm.dma_address,
|
||||
ttm->num_pages);
|
||||
ttm->state = tt_unbound;
|
||||
ttm_tt_set_populated(ttm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1367,7 +1373,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
|
||||
* Unmaps pages of a ttm_tt object from the device address space and
|
||||
* unpopulates the page array backing it.
|
||||
*/
|
||||
static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
|
||||
static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
|
||||
{
|
||||
struct amdgpu_ttm_tt *gtt = (void *)ttm;
|
||||
struct amdgpu_device *adev;
|
||||
@@ -1391,7 +1397,7 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
|
||||
if (ttm->page_flags & TTM_PAGE_FLAG_SG)
|
||||
return;
|
||||
|
||||
adev = amdgpu_ttm_adev(ttm->bdev);
|
||||
adev = amdgpu_ttm_adev(bdev);
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
if (adev->need_swiotlb && swiotlb_nr_tbl()) {
|
||||
@@ -1697,6 +1703,9 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
|
||||
.ttm_tt_create = &amdgpu_ttm_tt_create,
|
||||
.ttm_tt_populate = &amdgpu_ttm_tt_populate,
|
||||
.ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
|
||||
.ttm_tt_bind = &amdgpu_ttm_backend_bind,
|
||||
.ttm_tt_unbind = &amdgpu_ttm_backend_unbind,
|
||||
.ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
|
||||
.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
|
||||
.evict_flags = &amdgpu_evict_flags,
|
||||
.move = &amdgpu_bo_move,
|
||||
|
||||
@@ -32,10 +32,6 @@
|
||||
#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
|
||||
#define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
|
||||
|
||||
#define AMDGPU_PL_FLAG_GDS (TTM_PL_FLAG_PRIV << 0)
|
||||
#define AMDGPU_PL_FLAG_GWS (TTM_PL_FLAG_PRIV << 1)
|
||||
#define AMDGPU_PL_FLAG_OA (TTM_PL_FLAG_PRIV << 2)
|
||||
|
||||
#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
|
||||
#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user