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Merge tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes, nothing too exciting about
this.
Some changes hit arch/sh and arch/arm but are well isolated and
acknowledged by the respective arch maintainers.
Core changes:
- Dropped the chained IRQ setup callback into GPIOLIB as we got rid
of the last users of that in this changeset.
New drivers:
- New driver for Ingenic X1830.
- New driver for Freescale i.MX8MP.
Driver enhancements:
- Fix all remaining Intel drivers to pass their IRQ chips along with
the GPIO chips.
- Intel Baytrail allocates its irqchip dynamically.
- Intel Lynxpoint is thoroughly rewritten and modernized.
- Aspeed AST2600 pin muxing and configuration is much improved.
- Qualcomm SC7180 functions are updated and wakeup interrupt map is
provided.
- A whole slew of Renesas SH-PFC cleanups and improvements.
- Fix up the Intel DT bindings to use the generic YAML DT bindings
schema (a first user of this)"
* tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
pinctrl: madera: Remove extra blank line
pinctrl: qcom: Don't lock around irq_set_irq_wake()
pinctrl: mvebu: armada-37xx: use use platform api
gpio: Drop the chained IRQ handler assign function
pinctrl: freescale: Add i.MX8MP pinctrl driver support
dt-bindings: imx: Add pinctrl binding doc for i.MX8MP
pinctrl: tigerlake: Tiger Lake uses _HID enumeration
pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID
pinctrl: iproc: Use platform_get_irq_optional() to avoid error message
pinctrl: dt-bindings: Fix some errors in the lgm and pinmux schema
pinctrl: intel: Pass irqchip when adding gpiochip
pinctrl: intel: Add GPIO <-> pin mapping ranges via callback
pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output
pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins
pinctrl: sunrisepoint: Add missing Interrupt Status register offset
pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers
pinctrl: artpec6: fix __iomem on reg in set
pinctrl: ingenic: Use devm_platform_ioremap_resource()
pinctrl: ingenic: Factorize irq_set_type function
pinctrl: ingenic: Remove duplicated ingenic_chip_info structures
...
This commit is contained in:
Linus Torvalds
@@ -54,8 +54,9 @@ patternProperties:
|
||||
TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
|
||||
TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
|
||||
THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13,
|
||||
UART6, UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
|
||||
WDTRST3, WDTRST4, ]
|
||||
UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
|
||||
USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
|
||||
WDTRST4, ]
|
||||
groups:
|
||||
allOf:
|
||||
- $ref: "/schemas/types.yaml#/definitions/string"
|
||||
@@ -85,8 +86,8 @@ patternProperties:
|
||||
TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
|
||||
TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
|
||||
THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0,
|
||||
UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, VB,
|
||||
VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]
|
||||
UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, USBA,
|
||||
USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
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||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale IMX8MP IOMUX Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description:
|
||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
|
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for common binding part and usage.
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||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mp-iomuxc
|
||||
|
||||
reg:
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||||
maxItems: 1
|
||||
|
||||
# Client device subnode's properties
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||||
patternProperties:
|
||||
'grp$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
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Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
fsl,pins:
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allOf:
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||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
|
||||
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
|
||||
be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
|
||||
integer CONFIG is the pad setting value like pull-up on this pin. Please
|
||||
refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
|
||||
|
||||
required:
|
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- fsl,pins
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||||
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||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
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additionalProperties: false
|
||||
|
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examples:
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# Pinmux controller node
|
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- |
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iomuxc: pinctrl@30330000 {
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compatible = "fsl,imx8mp-iomuxc";
|
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reg = <0x30330000 0x10000>;
|
||||
|
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pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
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0x228 0x488 0x5F0 0x0 0x6 0x49
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0x228 0x488 0x000 0x0 0x0 0x49
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -10,9 +10,9 @@ GPIO port configuration registers and it is typical to refer to pins using the
|
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naming scheme "PxN" where x is a character identifying the GPIO port with
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which the pin is associated and N is an integer from 0 to 31 identifying the
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pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
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PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO
|
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ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780
|
||||
contains 6 GPIO ports, PA to PF, for a total of 192 pins.
|
||||
PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
|
||||
contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
|
||||
jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
|
||||
|
||||
|
||||
Required properties:
|
||||
@@ -28,6 +28,7 @@ Required properties:
|
||||
- "ingenic,x1000-pinctrl"
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- "ingenic,x1000e-pinctrl"
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- "ingenic,x1500-pinctrl"
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||||
- "ingenic,x1830-pinctrl"
|
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- reg: Address range of the pinctrl registers.
|
||||
|
||||
|
||||
@@ -40,6 +41,7 @@ Required properties for sub-nodes (GPIO chips):
|
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- "ingenic,jz4770-gpio"
|
||||
- "ingenic,jz4780-gpio"
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- "ingenic,x1000-gpio"
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||||
- "ingenic,x1830-gpio"
|
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- reg: The GPIO bank number.
|
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- interrupt-controller: Marks the device node as an interrupt controller.
|
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- interrupts: Interrupt specifier for the controllers interrupt.
|
||||
|
||||
75
Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml
Normal file
75
Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml
Normal file
@@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
|
||||
|
||||
maintainers:
|
||||
- Rahul Tanwar <rahul.tanwar@linux.intel.com>
|
||||
|
||||
description: |
|
||||
Pinmux & GPIO controller controls pin multiplexing & configuration including
|
||||
GPIO function selection & GPIO attributes configuration.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,lgm-io
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
# Client device subnode's properties
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
allOf:
|
||||
- $ref: pincfg-node.yaml#
|
||||
- $ref: pinmux-node.yaml#
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
function: true
|
||||
groups: true
|
||||
pins: true
|
||||
pinmux: true
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||||
bias-pull-up: true
|
||||
bias-pull-down: true
|
||||
drive-strength: true
|
||||
slew-rate: true
|
||||
drive-open-drain: true
|
||||
output-enable: true
|
||||
|
||||
required:
|
||||
- function
|
||||
- groups
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl: pinctrl@e2880000 {
|
||||
compatible = "intel,lgm-io";
|
||||
reg = <0xe2880000 0x100000>;
|
||||
|
||||
uart0-pins {
|
||||
pins = <64>, /* UART_RX0 */
|
||||
<65>; /* UART_TX0 */
|
||||
function = "CONSOLE_UART0";
|
||||
pinmux = <1>,
|
||||
<1>;
|
||||
groups = "CONSOLE_UART0";
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -1,116 +0,0 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
|
||||
|
||||
maintainers:
|
||||
- Rahul Tanwar <rahul.tanwar@linux.intel.com>
|
||||
|
||||
description: |
|
||||
Pinmux & GPIO controller controls pin multiplexing & configuration including
|
||||
GPIO function selection & GPIO attributes configuration.
|
||||
|
||||
Please refer to [1] for details of the common pinctrl bindings used by the
|
||||
client devices.
|
||||
|
||||
[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,lgm-io
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
# Client device subnode's properties
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
function:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description:
|
||||
A string containing the name of the function to mux to the group.
|
||||
|
||||
groups:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
description:
|
||||
An array of strings identifying the list of groups.
|
||||
|
||||
pins:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
List of pins to select with this function.
|
||||
|
||||
pinmux:
|
||||
description: The applicable mux group.
|
||||
allOf:
|
||||
- $ref: "/schemas/types.yaml#/definitions/uint32-array"
|
||||
|
||||
bias-pull-up:
|
||||
type: boolean
|
||||
|
||||
bias-pull-down:
|
||||
type: boolean
|
||||
|
||||
drive-strength:
|
||||
description: |
|
||||
Selects the drive strength for the specified pins in mA.
|
||||
0: 2 mA
|
||||
1: 4 mA
|
||||
2: 8 mA
|
||||
3: 12 mA
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [0, 1, 2, 3]
|
||||
|
||||
slew-rate:
|
||||
type: boolean
|
||||
description: |
|
||||
Sets slew rate for specified pins.
|
||||
0: slow slew
|
||||
1: fast slew
|
||||
|
||||
drive-open-drain:
|
||||
type: boolean
|
||||
|
||||
output-enable:
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- function
|
||||
- groups
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl: pinctrl@e2880000 {
|
||||
compatible = "intel,lgm-pinctrl";
|
||||
reg = <0xe2880000 0x100000>;
|
||||
|
||||
uart0-pins {
|
||||
pins = <64>, /* UART_RX0 */
|
||||
<65>; /* UART_TX0 */
|
||||
function = "CONSOLE_UART0";
|
||||
pinmux = <1>,
|
||||
<1>;
|
||||
groups = "CONSOLE_UART0";
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -114,7 +114,7 @@ properties:
|
||||
specific binding for the hardware defines whether the entries are integers
|
||||
or strings, and their meaning.
|
||||
|
||||
group:
|
||||
groups:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
description:
|
||||
the group to apply the properties to, if the driver supports
|
||||
|
||||
@@ -125,8 +125,9 @@ to specify in a pin configuration subnode:
|
||||
mi2s_1, mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag,
|
||||
PLL_BIST, pll_bypassnl, pll_reset, prng_rosc, qdss,
|
||||
qdss_cti, qlink_enable, qlink_request, qspi_clk, qspi_cs,
|
||||
qspi_data, qup00, qup01, qup02, qup03, qup04, qup05,
|
||||
qup10, qup11, qup12, qup13, qup14, qup15, sdc1_tb,
|
||||
qspi_data, qup00, qup01, qup02_i2c, qup02_uart, qup03,
|
||||
qup04_i2c, qup04_uart, qup05, qup10, qup11_i2c, qup11_uart,
|
||||
qup12, qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb,
|
||||
sdc2_tb, sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2,
|
||||
tgu_ch3, tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt,
|
||||
usb_phy, vfr_1, _V_GPIO, _V_PPS_IN, _V_PPS_OUT,
|
||||
|
||||
@@ -507,11 +507,6 @@ available but we try to move away from this:
|
||||
cascaded irq has to be handled by a threaded interrupt handler.
|
||||
Apart from that it works exactly like the chained irqchip.
|
||||
|
||||
- DEPRECATED: gpiochip_set_chained_irqchip(): sets up a chained cascaded irq
|
||||
handler for a gpio_chip from a parent IRQ and passes the struct gpio_chip*
|
||||
as handler data. Notice that we pass is as the handler data, since the
|
||||
irqchip data is likely used by the parent irqchip.
|
||||
|
||||
- gpiochip_set_nested_irqchip(): sets up a nested cascaded irq handler for a
|
||||
gpio_chip from a parent IRQ. As the parent IRQ has usually been
|
||||
explicitly requested by the driver, this does very little more than
|
||||
|
||||
@@ -8383,7 +8383,6 @@ S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git
|
||||
F: drivers/gpio/gpio-ich.c
|
||||
F: drivers/gpio/gpio-intel-mid.c
|
||||
F: drivers/gpio/gpio-lynxpoint.c
|
||||
F: drivers/gpio/gpio-merrifield.c
|
||||
F: drivers/gpio/gpio-ml-ioh.c
|
||||
F: drivers/gpio/gpio-pch.c
|
||||
|
||||
@@ -201,7 +201,7 @@ static unsigned long pin_highz_conf[] = {
|
||||
};
|
||||
|
||||
/* Pin control settings */
|
||||
static struct pinctrl_map __initdata u300_pinmux_map[] = {
|
||||
static const struct pinctrl_map u300_pinmux_map[] = {
|
||||
/* anonymous maps for chip power and EMIFs */
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
|
||||
|
||||
@@ -112,12 +112,6 @@ enum {
|
||||
GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
|
||||
GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
|
||||
|
||||
/* SSU */
|
||||
GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
|
||||
GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
|
||||
GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
|
||||
GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
|
||||
|
||||
/* SCIF */
|
||||
GPIO_FN_SCK0, GPIO_FN_SCK1, GPIO_FN_SCK2, GPIO_FN_SCK3,
|
||||
GPIO_FN_RXD0, GPIO_FN_RXD1, GPIO_FN_RXD2, GPIO_FN_RXD3,
|
||||
|
||||
@@ -78,8 +78,15 @@ enum {
|
||||
GPIO_FN_WDTOVF,
|
||||
|
||||
/* CAN */
|
||||
GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
|
||||
GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2,
|
||||
GPIO_FN_CTX2, GPIO_FN_CRX2,
|
||||
GPIO_FN_CTX1, GPIO_FN_CRX1,
|
||||
GPIO_FN_CTX0, GPIO_FN_CRX0,
|
||||
GPIO_FN_CTX0_CTX1, GPIO_FN_CRX0_CRX1,
|
||||
GPIO_FN_CTX0_CTX1_CTX2, GPIO_FN_CRX0_CRX1_CRX2,
|
||||
GPIO_FN_CTX2_PJ21, GPIO_FN_CRX2_PJ20,
|
||||
GPIO_FN_CTX1_PJ23, GPIO_FN_CRX1_PJ22,
|
||||
GPIO_FN_CTX0_CTX1_PJ23, GPIO_FN_CRX0_CRX1_PJ22,
|
||||
GPIO_FN_CTX0_CTX1_CTX2_PJ21, GPIO_FN_CRX0_CRX1_CRX2_PJ20,
|
||||
|
||||
/* DMAC */
|
||||
GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
|
||||
@@ -119,12 +126,6 @@ enum {
|
||||
GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
|
||||
GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
|
||||
|
||||
/* SSU */
|
||||
GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
|
||||
GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
|
||||
GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
|
||||
GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
|
||||
|
||||
/* SCIF */
|
||||
GPIO_FN_SCK0, GPIO_FN_RXD0, GPIO_FN_TXD0,
|
||||
GPIO_FN_SCK1, GPIO_FN_RXD1, GPIO_FN_TXD1, GPIO_FN_RTS1, GPIO_FN_CTS1,
|
||||
|
||||
@@ -341,14 +341,6 @@ config GPIO_LPC32XX
|
||||
Select this option to enable GPIO driver for
|
||||
NXP LPC32XX devices.
|
||||
|
||||
config GPIO_LYNXPOINT
|
||||
tristate "Intel Lynxpoint GPIO support"
|
||||
depends on ACPI && X86
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
driver for GPIO functionality on Intel Lynxpoint PCH chipset
|
||||
Requires ACPI device enumeration code to set up a platform device.
|
||||
|
||||
config GPIO_MB86S7X
|
||||
tristate "GPIO support for Fujitsu MB86S7x Platforms"
|
||||
help
|
||||
|
||||
@@ -77,7 +77,6 @@ obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o
|
||||
obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o
|
||||
obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o
|
||||
obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o
|
||||
obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o
|
||||
obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o
|
||||
obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o
|
||||
obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
|
||||
|
||||
@@ -1,471 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* GPIO controller driver for Intel Lynxpoint PCH chipset>
|
||||
* Copyright (c) 2012, Intel Corporation.
|
||||
*
|
||||
* Author: Mathias Nyman <mathias.nyman@linux.intel.com>
|
||||
*/
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
/* LynxPoint chipset has support for 94 gpio pins */
|
||||
|
||||
#define LP_NUM_GPIO 94
|
||||
|
||||
/* Bitmapped register offsets */
|
||||
#define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
|
||||
#define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
|
||||
#define LP_INT_STAT 0x80
|
||||
#define LP_INT_ENABLE 0x90
|
||||
|
||||
/* Each pin has two 32 bit config registers, starting at 0x100 */
|
||||
#define LP_CONFIG1 0x100
|
||||
#define LP_CONFIG2 0x104
|
||||
|
||||
/* LP_CONFIG1 reg bits */
|
||||
#define OUT_LVL_BIT BIT(31)
|
||||
#define IN_LVL_BIT BIT(30)
|
||||
#define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */
|
||||
#define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
|
||||
#define DIR_BIT BIT(2) /* 0: Output, 1: Input */
|
||||
#define USE_SEL_BIT BIT(0) /* 0: Native, 1: GPIO */
|
||||
|
||||
/* LP_CONFIG2 reg bits */
|
||||
#define GPINDIS_BIT BIT(2) /* disable input sensing */
|
||||
#define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */
|
||||
|
||||
struct lp_gpio {
|
||||
struct gpio_chip chip;
|
||||
struct platform_device *pdev;
|
||||
spinlock_t lock;
|
||||
unsigned long reg_base;
|
||||
};
|
||||
|
||||
/*
|
||||
* Lynxpoint gpios are controlled through both bitmapped registers and
|
||||
* per gpio specific registers. The bitmapped registers are in chunks of
|
||||
* 3 x 32bit registers to cover all 94 gpios
|
||||
*
|
||||
* per gpio specific registers consist of two 32bit registers per gpio
|
||||
* (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of
|
||||
* 188 config registers.
|
||||
*
|
||||
* A simplified view of the register layout look like this:
|
||||
*
|
||||
* LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
|
||||
* LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
|
||||
* LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
|
||||
* ...
|
||||
* LP_INT_ENABLE[31:0] ...
|
||||
* LP_INT_ENABLE[63:31] ...
|
||||
* LP_INT_ENABLE[94:64] ...
|
||||
* LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
|
||||
* LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
|
||||
* LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
|
||||
* LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
|
||||
* LP2_CONFIG1 (gpio 2) ...
|
||||
* LP2_CONFIG2 (gpio 2) ...
|
||||
* ...
|
||||
* LP94_CONFIG1 (gpio 94) ...
|
||||
* LP94_CONFIG2 (gpio 94) ...
|
||||
*/
|
||||
|
||||
static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
|
||||
int reg)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
int reg_offset;
|
||||
|
||||
if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
|
||||
/* per gpio specific config registers */
|
||||
reg_offset = offset * 8;
|
||||
else
|
||||
/* bitmapped registers */
|
||||
reg_offset = (offset / 32) * 4;
|
||||
|
||||
return lg->reg_base + reg + reg_offset;
|
||||
}
|
||||
|
||||
static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
|
||||
unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
|
||||
unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED);
|
||||
|
||||
pm_runtime_get(&lg->pdev->dev); /* should we put if failed */
|
||||
|
||||
/* Fail if BIOS reserved pin for ACPI use */
|
||||
if (!(inl(acpi_use) & BIT(offset % 32))) {
|
||||
dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset);
|
||||
return -EBUSY;
|
||||
}
|
||||
/* Fail if pin is in alternate function mode (not GPIO mode) */
|
||||
if (!(inl(reg) & USE_SEL_BIT))
|
||||
return -ENODEV;
|
||||
|
||||
/* enable input sensing */
|
||||
outl(inl(conf2) & ~GPINDIS_BIT, conf2);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
|
||||
|
||||
/* disable input sensing */
|
||||
outl(inl(conf2) | GPINDIS_BIT, conf2);
|
||||
|
||||
pm_runtime_put(&lg->pdev->dev);
|
||||
}
|
||||
|
||||
static int lp_irq_type(struct irq_data *d, unsigned type)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct lp_gpio *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
|
||||
|
||||
if (hwirq >= lg->chip.ngpio)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&lg->lock, flags);
|
||||
value = inl(reg);
|
||||
|
||||
/* set both TRIG_SEL and INV bits to 0 for rising edge */
|
||||
if (type & IRQ_TYPE_EDGE_RISING)
|
||||
value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
|
||||
|
||||
/* TRIG_SEL bit 0, INV bit 1 for falling edge */
|
||||
if (type & IRQ_TYPE_EDGE_FALLING)
|
||||
value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
|
||||
|
||||
/* TRIG_SEL bit 1, INV bit 0 for level low */
|
||||
if (type & IRQ_TYPE_LEVEL_LOW)
|
||||
value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
|
||||
|
||||
/* TRIG_SEL bit 1, INV bit 1 for level high */
|
||||
if (type & IRQ_TYPE_LEVEL_HIGH)
|
||||
value |= TRIG_SEL_BIT | INT_INV_BIT;
|
||||
|
||||
outl(value, reg);
|
||||
|
||||
if (type & IRQ_TYPE_EDGE_BOTH)
|
||||
irq_set_handler_locked(d, handle_edge_irq);
|
||||
else if (type & IRQ_TYPE_LEVEL_MASK)
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
|
||||
spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
|
||||
return !!(inl(reg) & IN_LVL_BIT);
|
||||
}
|
||||
|
||||
static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&lg->lock, flags);
|
||||
|
||||
if (value)
|
||||
outl(inl(reg) | OUT_LVL_BIT, reg);
|
||||
else
|
||||
outl(inl(reg) & ~OUT_LVL_BIT, reg);
|
||||
|
||||
spin_unlock_irqrestore(&lg->lock, flags);
|
||||
}
|
||||
|
||||
static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&lg->lock, flags);
|
||||
outl(inl(reg) | DIR_BIT, reg);
|
||||
spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned offset, int value)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
|
||||
unsigned long flags;
|
||||
|
||||
lp_gpio_set(chip, offset, value);
|
||||
|
||||
spin_lock_irqsave(&lg->lock, flags);
|
||||
outl(inl(reg) & ~DIR_BIT, reg);
|
||||
spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void lp_gpio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_data *data = irq_desc_get_irq_data(desc);
|
||||
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
|
||||
struct lp_gpio *lg = gpiochip_get_data(gc);
|
||||
struct irq_chip *chip = irq_data_get_irq_chip(data);
|
||||
unsigned long reg, ena, pending;
|
||||
u32 base, pin;
|
||||
|
||||
/* check from GPIO controller which pin triggered the interrupt */
|
||||
for (base = 0; base < lg->chip.ngpio; base += 32) {
|
||||
reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
|
||||
ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
|
||||
|
||||
/* Only interrupts that are enabled */
|
||||
pending = inl(reg) & inl(ena);
|
||||
|
||||
for_each_set_bit(pin, &pending, 32) {
|
||||
unsigned irq;
|
||||
|
||||
/* Clear before handling so we don't lose an edge */
|
||||
outl(BIT(pin), reg);
|
||||
|
||||
irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
}
|
||||
chip->irq_eoi(data);
|
||||
}
|
||||
|
||||
static void lp_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
}
|
||||
|
||||
static void lp_irq_mask(struct irq_data *d)
|
||||
{
|
||||
}
|
||||
|
||||
static void lp_irq_enable(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct lp_gpio *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&lg->lock, flags);
|
||||
outl(inl(reg) | BIT(hwirq % 32), reg);
|
||||
spin_unlock_irqrestore(&lg->lock, flags);
|
||||
}
|
||||
|
||||
static void lp_irq_disable(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct lp_gpio *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&lg->lock, flags);
|
||||
outl(inl(reg) & ~BIT(hwirq % 32), reg);
|
||||
spin_unlock_irqrestore(&lg->lock, flags);
|
||||
}
|
||||
|
||||
static struct irq_chip lp_irqchip = {
|
||||
.name = "LP-GPIO",
|
||||
.irq_mask = lp_irq_mask,
|
||||
.irq_unmask = lp_irq_unmask,
|
||||
.irq_enable = lp_irq_enable,
|
||||
.irq_disable = lp_irq_disable,
|
||||
.irq_set_type = lp_irq_type,
|
||||
.flags = IRQCHIP_SKIP_SET_WAKE,
|
||||
};
|
||||
|
||||
static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
|
||||
{
|
||||
struct lp_gpio *lg = gpiochip_get_data(chip);
|
||||
unsigned long reg;
|
||||
unsigned base;
|
||||
|
||||
for (base = 0; base < lg->chip.ngpio; base += 32) {
|
||||
/* disable gpio pin interrupts */
|
||||
reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
|
||||
outl(0, reg);
|
||||
/* Clear interrupt status register */
|
||||
reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
|
||||
outl(0xffffffff, reg);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct lp_gpio *lg;
|
||||
struct gpio_chip *gc;
|
||||
struct resource *io_rc, *irq_rc;
|
||||
struct device *dev = &pdev->dev;
|
||||
unsigned long reg_len;
|
||||
int ret = -ENODEV;
|
||||
|
||||
lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL);
|
||||
if (!lg)
|
||||
return -ENOMEM;
|
||||
|
||||
lg->pdev = pdev;
|
||||
platform_set_drvdata(pdev, lg);
|
||||
|
||||
io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
|
||||
irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
|
||||
if (!io_rc) {
|
||||
dev_err(dev, "missing IO resources\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
lg->reg_base = io_rc->start;
|
||||
reg_len = resource_size(io_rc);
|
||||
|
||||
if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) {
|
||||
dev_err(dev, "failed requesting IO region 0x%x\n",
|
||||
(unsigned int)lg->reg_base);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
spin_lock_init(&lg->lock);
|
||||
|
||||
gc = &lg->chip;
|
||||
gc->label = dev_name(dev);
|
||||
gc->owner = THIS_MODULE;
|
||||
gc->request = lp_gpio_request;
|
||||
gc->free = lp_gpio_free;
|
||||
gc->direction_input = lp_gpio_direction_input;
|
||||
gc->direction_output = lp_gpio_direction_output;
|
||||
gc->get = lp_gpio_get;
|
||||
gc->set = lp_gpio_set;
|
||||
gc->base = -1;
|
||||
gc->ngpio = LP_NUM_GPIO;
|
||||
gc->can_sleep = false;
|
||||
gc->parent = dev;
|
||||
|
||||
/* set up interrupts */
|
||||
if (irq_rc && irq_rc->start) {
|
||||
struct gpio_irq_chip *girq;
|
||||
|
||||
girq = &gc->irq;
|
||||
girq->chip = &lp_irqchip;
|
||||
girq->init_hw = lp_gpio_irq_init_hw;
|
||||
girq->parent_handler = lp_gpio_irq_handler;
|
||||
girq->num_parents = 1;
|
||||
girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
|
||||
sizeof(*girq->parents),
|
||||
GFP_KERNEL);
|
||||
if (!girq->parents)
|
||||
return -ENOMEM;
|
||||
girq->parents[0] = (unsigned)irq_rc->start;
|
||||
girq->default_type = IRQ_TYPE_NONE;
|
||||
girq->handler = handle_bad_irq;
|
||||
}
|
||||
|
||||
ret = devm_gpiochip_add_data(dev, gc, lg);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed adding lp-gpio chip\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_runtime_suspend(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_runtime_resume(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_resume(struct device *dev)
|
||||
{
|
||||
struct lp_gpio *lg = dev_get_drvdata(dev);
|
||||
unsigned long reg;
|
||||
int i;
|
||||
|
||||
/* on some hardware suspend clears input sensing, re-enable it here */
|
||||
for (i = 0; i < lg->chip.ngpio; i++) {
|
||||
if (gpiochip_is_requested(&lg->chip, i) != NULL) {
|
||||
reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
|
||||
outl(inl(reg) & ~GPINDIS_BIT, reg);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops lp_gpio_pm_ops = {
|
||||
.runtime_suspend = lp_gpio_runtime_suspend,
|
||||
.runtime_resume = lp_gpio_runtime_resume,
|
||||
.resume = lp_gpio_resume,
|
||||
};
|
||||
|
||||
static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
|
||||
{ "INT33C7", 0 },
|
||||
{ "INT3437", 0 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
|
||||
|
||||
static int lp_gpio_remove(struct platform_device *pdev)
|
||||
{
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver lp_gpio_driver = {
|
||||
.probe = lp_gpio_probe,
|
||||
.remove = lp_gpio_remove,
|
||||
.driver = {
|
||||
.name = "lp_gpio",
|
||||
.pm = &lp_gpio_pm_ops,
|
||||
.acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init lp_gpio_init(void)
|
||||
{
|
||||
return platform_driver_register(&lp_gpio_driver);
|
||||
}
|
||||
|
||||
static void __exit lp_gpio_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&lp_gpio_driver);
|
||||
}
|
||||
|
||||
subsys_initcall(lp_gpio_init);
|
||||
module_exit(lp_gpio_exit);
|
||||
|
||||
MODULE_AUTHOR("Mathias Nyman (Intel)");
|
||||
MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:lp_gpio");
|
||||
@@ -253,8 +253,7 @@ mediatek_gpio_bank_probe(struct device *dev,
|
||||
|
||||
/*
|
||||
* Directly request the irq here instead of passing
|
||||
* a flow-handler to gpiochip_set_chained_irqchip,
|
||||
* because the irq is shared.
|
||||
* a flow-handler because the irq is shared.
|
||||
*/
|
||||
ret = devm_request_irq(dev, mtk->gpio_irq,
|
||||
mediatek_gpio_irq_handler, IRQF_SHARED,
|
||||
|
||||
@@ -251,8 +251,7 @@ static int iproc_gpio_probe(struct platform_device *pdev)
|
||||
|
||||
/*
|
||||
* Directly request the irq here instead of passing
|
||||
* a flow-handler to gpiochip_set_chained_irqchip,
|
||||
* because the irq is shared.
|
||||
* a flow-handler because the irq is shared.
|
||||
*/
|
||||
ret = devm_request_irq(dev, irq, iproc_gpio_irq_handler,
|
||||
IRQF_SHARED, chip->gc.label, &chip->gc);
|
||||
|
||||
@@ -1800,7 +1800,7 @@ EXPORT_SYMBOL_GPL(gpiochip_irqchip_irq_valid);
|
||||
* gpiochip_set_cascaded_irqchip() - connects a cascaded irqchip to a gpiochip
|
||||
* @gc: the gpiochip to set the irqchip chain to
|
||||
* @parent_irq: the irq number corresponding to the parent IRQ for this
|
||||
* chained irqchip
|
||||
* cascaded irqchip
|
||||
* @parent_handler: the parent interrupt handler for the accumulated IRQ
|
||||
* coming out of the gpiochip. If the interrupt is nested rather than
|
||||
* cascaded, pass NULL in this handler argument
|
||||
@@ -1842,29 +1842,6 @@ static void gpiochip_set_cascaded_irqchip(struct gpio_chip *gc,
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* gpiochip_set_chained_irqchip() - connects a chained irqchip to a gpiochip
|
||||
* @gpiochip: the gpiochip to set the irqchip chain to
|
||||
* @irqchip: the irqchip to chain to the gpiochip
|
||||
* @parent_irq: the irq number corresponding to the parent IRQ for this
|
||||
* chained irqchip
|
||||
* @parent_handler: the parent interrupt handler for the accumulated IRQ
|
||||
* coming out of the gpiochip.
|
||||
*/
|
||||
void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
|
||||
struct irq_chip *irqchip,
|
||||
unsigned int parent_irq,
|
||||
irq_flow_handler_t parent_handler)
|
||||
{
|
||||
if (gpiochip->irq.threaded) {
|
||||
chip_err(gpiochip, "tried to chain a threaded gpiochip\n");
|
||||
return;
|
||||
}
|
||||
|
||||
gpiochip_set_cascaded_irqchip(gpiochip, parent_irq, parent_handler);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(gpiochip_set_chained_irqchip);
|
||||
|
||||
/**
|
||||
* gpiochip_set_nested_irqchip() - connects a nested irqchip to a gpiochip
|
||||
* @gpiochip: the gpiochip to set the irqchip nested handler to
|
||||
|
||||
@@ -1583,7 +1583,6 @@ static const struct owl_pinmux_func s700_functions[] = {
|
||||
[S700_MUX_USB30] = FUNCTION(usb30),
|
||||
[S700_MUX_CLKO_25M] = FUNCTION(clko_25m),
|
||||
[S700_MUX_MIPI_CSI] = FUNCTION(mipi_csi),
|
||||
[S700_MUX_DSI] = FUNCTION(dsi),
|
||||
[S700_MUX_NAND] = FUNCTION(nand),
|
||||
[S700_MUX_SPDIF] = FUNCTION(spdif),
|
||||
[S700_MUX_SIRQ0] = FUNCTION(sirq0),
|
||||
|
||||
@@ -2439,88 +2439,88 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
|
||||
|
||||
static const struct aspeed_pin_config aspeed_g4_configs[] = {
|
||||
/* GPIO banks ranges [A, B], [D, J], [M, R] */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { D6, D5 }, SCU8C, 16 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { D6, D5 }, SCU8C, 16 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { J21, E18 }, SCU8C, 17 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { J21, E18 }, SCU8C, 17 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { A18, E15 }, SCU8C, 19 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { A18, E15 }, SCU8C, 19 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { D15, B14 }, SCU8C, 20 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { D15, B14 }, SCU8C, 20 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { D18, C17 }, SCU8C, 21 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { D18, C17 }, SCU8C, 21 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { A14, U18 }, SCU8C, 22 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { A14, U18 }, SCU8C, 22 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { A8, E7 }, SCU8C, 23 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { A8, E7 }, SCU8C, 23 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { C22, E20 }, SCU8C, 24 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { C22, E20 }, SCU8C, 24 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { J5, T1 }, SCU8C, 25 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { J5, T1 }, SCU8C, 25 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { U1, U5 }, SCU8C, 26 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { U1, U5 }, SCU8C, 26 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { V3, V5 }, SCU8C, 27 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { V3, V5 }, SCU8C, 27 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { W4, AB2 }, SCU8C, 28 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { W4, AB2 }, SCU8C, 28 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { V6, V7 }, SCU8C, 29 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { V6, V7 }, SCU8C, 29 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { Y6, AB7 }, SCU8C, 30 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { Y6, AB7 }, SCU8C, 30 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { V20, A5 }, SCU8C, 31 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { V20, A5 }, SCU8C, 31 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D6, D5, SCU8C, 16),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D6, D5, SCU8C, 16),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J21, E18, SCU8C, 17),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J21, E18, SCU8C, 17),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, E15, SCU8C, 19),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, E15, SCU8C, 19),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D15, B14, SCU8C, 20),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D15, B14, SCU8C, 20),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D18, C17, SCU8C, 21),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D18, C17, SCU8C, 21),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A14, U18, SCU8C, 22),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A14, U18, SCU8C, 22),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A8, E7, SCU8C, 23),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A8, E7, SCU8C, 23),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C22, E20, SCU8C, 24),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C22, E20, SCU8C, 24),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J5, T1, SCU8C, 25),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J5, T1, SCU8C, 25),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U1, U5, SCU8C, 26),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U1, U5, SCU8C, 26),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V3, V5, SCU8C, 27),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V3, V5, SCU8C, 27),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, W4, AB2, SCU8C, 28),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, W4, AB2, SCU8C, 28),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V6, V7, SCU8C, 29),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V6, V7, SCU8C, 29),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y6, AB7, SCU8C, 30),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y6, AB7, SCU8C, 30),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, A5, SCU8C, 31),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, A5, SCU8C, 31),
|
||||
|
||||
/* GPIOs T[0-5] (RGMII1 Tx pins) */
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { A12, A13 }, SCU90, 9 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { A12, A13 }, SCU90, 12 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { A12, A13 }, SCU90, 12 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, A12, A13, SCU90, 9),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A12, A13, SCU90, 12),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A12, A13, SCU90, 12),
|
||||
|
||||
/* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, { D9, D10 }, SCU90, 11 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { D9, D10 }, SCU90, 14 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { D9, D10 }, SCU90, 14 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, D9, D10, SCU90, 11),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D9, D10, SCU90, 14),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D9, D10, SCU90, 14),
|
||||
|
||||
/* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { E11, E10 }, SCU90, 13 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { E11, E10 }, SCU90, 13 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E11, E10, SCU90, 13),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E11, E10, SCU90, 13),
|
||||
|
||||
/* GPIOs V[2-7] (RGMII2 Rx pins) */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { C9, C8 }, SCU90, 15 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { C9, C8 }, SCU90, 15 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C9, C8, SCU90, 15),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C9, C8, SCU90, 15),
|
||||
|
||||
/* ADC pull-downs (SCUA8[19:4]) */
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { L5, L5 }, SCUA8, 4 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { L5, L5 }, SCUA8, 4 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { L4, L4 }, SCUA8, 5 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { L4, L4 }, SCUA8, 5 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { L3, L3 }, SCUA8, 6 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { L3, L3 }, SCUA8, 6 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { L2, L2 }, SCUA8, 7 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { L2, L2 }, SCUA8, 7 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { L1, L1 }, SCUA8, 8 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { L1, L1 }, SCUA8, 8 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { M5, M5 }, SCUA8, 9 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { M5, M5 }, SCUA8, 9 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { M4, M4 }, SCUA8, 10 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { M4, M4 }, SCUA8, 10 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { M3, M3 }, SCUA8, 11 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { M3, M3 }, SCUA8, 11 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { M2, M2 }, SCUA8, 12 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { M2, M2 }, SCUA8, 12 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { M1, M1 }, SCUA8, 13 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { M1, M1 }, SCUA8, 13 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { N5, N5 }, SCUA8, 14 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { N5, N5 }, SCUA8, 14 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { N4, N4 }, SCUA8, 15 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { N4, N4 }, SCUA8, 15 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { N3, N3 }, SCUA8, 16 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { N3, N3 }, SCUA8, 16 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { N2, N2 }, SCUA8, 17 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { N2, N2 }, SCUA8, 17 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { N1, N1 }, SCUA8, 18 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { N1, N1 }, SCUA8, 18 },
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, { P5, P5 }, SCUA8, 19 },
|
||||
{ PIN_CONFIG_BIAS_DISABLE, { P5, P5 }, SCUA8, 19 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L5, L5, SCUA8, 4),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L5, L5, SCUA8, 4),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L4, L4, SCUA8, 5),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L4, L4, SCUA8, 5),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, L3, SCUA8, 6),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, L3, SCUA8, 6),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L2, L2, SCUA8, 7),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L2, L2, SCUA8, 7),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L1, L1, SCUA8, 8),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L1, L1, SCUA8, 8),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M5, M5, SCUA8, 9),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M5, M5, SCUA8, 9),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M4, M4, SCUA8, 10),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M4, M4, SCUA8, 10),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M3, M3, SCUA8, 11),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M3, M3, SCUA8, 11),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M2, M2, SCUA8, 12),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M2, M2, SCUA8, 12),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M1, M1, SCUA8, 13),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M1, M1, SCUA8, 13),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N5, N5, SCUA8, 14),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N5, N5, SCUA8, 14),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N4, N4, SCUA8, 15),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N4, N4, SCUA8, 15),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N3, N3, SCUA8, 16),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N3, N3, SCUA8, 16),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N2, N2, SCUA8, 17),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N2, N2, SCUA8, 17),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N1, N1, SCUA8, 18),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N1, N1, SCUA8, 18),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, P5, P5, SCUA8, 19),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, P5, P5, SCUA8, 19),
|
||||
|
||||
/*
|
||||
* Debounce settings for GPIOs D and E passthrough mode are in
|
||||
@@ -2531,14 +2531,14 @@ static const struct aspeed_pin_config aspeed_g4_configs[] = {
|
||||
* controller. Due to this tangle between GPIO and pinctrl we don't yet
|
||||
* fully support pass-through debounce.
|
||||
*/
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { A18, D16 }, SCUA8, 20 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { B17, A17 }, SCUA8, 21 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { C16, B16 }, SCUA8, 22 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { A16, E15 }, SCUA8, 23 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { D15, C15 }, SCUA8, 24 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { B15, A15 }, SCUA8, 25 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { E14, D14 }, SCUA8, 26 },
|
||||
{ PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 },
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A18, D16, SCUA8, 20),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B17, A17, SCUA8, 21),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C16, B16, SCUA8, 22),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A16, E15, SCUA8, 23),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D15, C15, SCUA8, 24),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B15, A15, SCUA8, 25),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E14, D14, SCUA8, 26),
|
||||
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C14, B14, SCUA8, 27),
|
||||
};
|
||||
|
||||
static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx,
|
||||
@@ -2594,6 +2594,14 @@ static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct aspeed_pin_config_map aspeed_g4_pin_config_map[] = {
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)},
|
||||
{ PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)},
|
||||
};
|
||||
|
||||
static const struct aspeed_pinmux_ops aspeed_g4_ops = {
|
||||
.set = aspeed_g4_sig_expr_set,
|
||||
};
|
||||
@@ -2610,6 +2618,8 @@ static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
|
||||
},
|
||||
.configs = aspeed_g4_configs,
|
||||
.nconfigs = ARRAY_SIZE(aspeed_g4_configs),
|
||||
.confmaps = aspeed_g4_pin_config_map,
|
||||
.nconfmaps = ARRAY_SIZE(aspeed_g4_pin_config_map),
|
||||
};
|
||||
|
||||
static const struct pinmux_ops aspeed_g4_pinmux_ops = {
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user