mirror of
https://github.com/Dasharo/linux.git
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm updates from Paolo Bonzini:
"ARM:
- Generalized infrastructure for 'writable' ID registers, effectively
allowing userspace to opt-out of certain vCPU features for its
guest
- Optimization for vSGI injection, opportunistically compressing
MPIDR to vCPU mapping into a table
- Improvements to KVM's PMU emulation, allowing userspace to select
the number of PMCs available to a VM
- Guest support for memory operation instructions (FEAT_MOPS)
- Cleanups to handling feature flags in KVM_ARM_VCPU_INIT, squashing
bugs and getting rid of useless code
- Changes to the way the SMCCC filter is constructed, avoiding wasted
memory allocations when not in use
- Load the stage-2 MMU context at vcpu_load() for VHE systems,
reducing the overhead of errata mitigations
- Miscellaneous kernel and selftest fixes
LoongArch:
- New architecture for kvm.
The hardware uses the same model as x86, s390 and RISC-V, where
guest/host mode is orthogonal to supervisor/user mode. The
virtualization extensions are very similar to MIPS, therefore the
code also has some similarities but it's been cleaned up to avoid
some of the historical bogosities that are found in arch/mips. The
kernel emulates MMU, timer and CSR accesses, while interrupt
controllers are only emulated in userspace, at least for now.
RISC-V:
- Support for the Smstateen and Zicond extensions
- Support for virtualizing senvcfg
- Support for virtualized SBI debug console (DBCN)
S390:
- Nested page table management can be monitored through tracepoints
and statistics
x86:
- Fix incorrect handling of VMX posted interrupt descriptor in
KVM_SET_LAPIC, which could result in a dropped timer IRQ
- Avoid WARN on systems with Intel IPI virtualization
- Add CONFIG_KVM_MAX_NR_VCPUS, to allow supporting up to 4096 vCPUs
without forcing more common use cases to eat the extra memory
overhead.
- Add virtualization support for AMD SRSO mitigation (IBPB_BRTYPE and
SBPB, aka Selective Branch Predictor Barrier).
- Fix a bug where restoring a vCPU snapshot that was taken within 1
second of creating the original vCPU would cause KVM to try to
synchronize the vCPU's TSC and thus clobber the correct TSC being
set by userspace.
- Compute guest wall clock using a single TSC read to avoid
generating an inaccurate time, e.g. if the vCPU is preempted
between multiple TSC reads.
- "Virtualize" HWCR.TscFreqSel to make Linux guests happy, which
complain about a "Firmware Bug" if the bit isn't set for select
F/M/S combos. Likewise "virtualize" (ignore) MSR_AMD64_TW_CFG to
appease Windows Server 2022.
- Don't apply side effects to Hyper-V's synthetic timer on writes
from userspace to fix an issue where the auto-enable behavior can
trigger spurious interrupts, i.e. do auto-enabling only for guest
writes.
- Remove an unnecessary kick of all vCPUs when synchronizing the
dirty log without PML enabled.
- Advertise "support" for non-serializing FS/GS base MSR writes as
appropriate.
- Harden the fast page fault path to guard against encountering an
invalid root when walking SPTEs.
- Omit "struct kvm_vcpu_xen" entirely when CONFIG_KVM_XEN=n.
- Use the fast path directly from the timer callback when delivering
Xen timer events, instead of waiting for the next iteration of the
run loop. This was not done so far because previously proposed code
had races, but now care is taken to stop the hrtimer at critical
points such as restarting the timer or saving the timer information
for userspace.
- Follow the lead of upstream Xen and ignore the VCPU_SSHOTTMR_future
flag.
- Optimize injection of PMU interrupts that are simultaneous with
NMIs.
- Usual handful of fixes for typos and other warts.
x86 - MTRR/PAT fixes and optimizations:
- Clean up code that deals with honoring guest MTRRs when the VM has
non-coherent DMA and host MTRRs are ignored, i.e. EPT is enabled.
- Zap EPT entries when non-coherent DMA assignment stops/start to
prevent using stale entries with the wrong memtype.
- Don't ignore guest PAT for CR0.CD=1 && KVM_X86_QUIRK_CD_NW_CLEARED=y
This was done as a workaround for virtual machine BIOSes that did
not bother to clear CR0.CD (because ancient KVM/QEMU did not bother
to set it, in turn), and there's zero reason to extend the quirk to
also ignore guest PAT.
x86 - SEV fixes:
- Report KVM_EXIT_SHUTDOWN instead of EINVAL if KVM intercepts
SHUTDOWN while running an SEV-ES guest.
- Clean up the recognition of emulation failures on SEV guests, when
KVM would like to "skip" the instruction but it had already been
partially emulated. This makes it possible to drop a hack that
second guessed the (insufficient) information provided by the
emulator, and just do the right thing.
Documentation:
- Various updates and fixes, mostly for x86
- MTRR and PAT fixes and optimizations"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (164 commits)
KVM: selftests: Avoid using forced target for generating arm64 headers
tools headers arm64: Fix references to top srcdir in Makefile
KVM: arm64: Add tracepoint for MMIO accesses where ISV==0
KVM: arm64: selftest: Perform ISB before reading PAR_EL1
KVM: arm64: selftest: Add the missing .guest_prepare()
KVM: arm64: Always invalidate TLB for stage-2 permission faults
KVM: x86: Service NMI requests after PMI requests in VM-Enter path
KVM: arm64: Handle AArch32 SPSR_{irq,abt,und,fiq} as RAZ/WI
KVM: arm64: Do not let a L1 hypervisor access the *32_EL2 sysregs
KVM: arm64: Refine _EL2 system register list that require trap reinjection
arm64: Add missing _EL2 encodings
arm64: Add missing _EL12 encodings
KVM: selftests: aarch64: vPMU test for validating user accesses
KVM: selftests: aarch64: vPMU register test for unimplemented counters
KVM: selftests: aarch64: vPMU register test for implemented counters
KVM: selftests: aarch64: Introduce vpmu_counter_access test
tools: Import arm_pmuv3.h
KVM: arm64: PMU: Allow userspace to limit PMCR_EL0.N for the guest
KVM: arm64: Sanitize PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} before first run
KVM: arm64: Add {get,set}_user for PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR}
...
This commit is contained in:
Linus Torvalds
@@ -128,6 +128,12 @@ properties:
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changes to interrupts as frozen at commit ccbddab ("Merge pull
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request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
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- const: smstateen
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description: |
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The standard Smstateen extension for controlling access to CSRs
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added by other RISC-V extensions in H/S/VS/U/VU modes and as
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ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
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- const: ssaia
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description: |
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The standard Ssaia supervisor-level extension for the advanced
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@@ -212,6 +218,12 @@ properties:
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ratified in the 20191213 version of the unprivileged ISA
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specification.
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- const: zicond
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description:
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The standard Zicond extension for conditional arithmetic and
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conditional-select/move operations as ratified in commit 95cf1f9
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("Add changes requested by Ved during signoff") of riscv-zicond.
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- const: zicsr
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description: |
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The standard Zicsr extension for control and status register
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@@ -416,6 +416,13 @@ Reads the general purpose registers from the vcpu.
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__u64 pc;
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};
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/* LoongArch */
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struct kvm_regs {
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/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
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unsigned long gpr[32];
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unsigned long pc;
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};
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4.12 KVM_SET_REGS
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-----------------
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@@ -506,7 +513,7 @@ translation mode.
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------------------
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:Capability: basic
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:Architectures: x86, ppc, mips, riscv
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:Architectures: x86, ppc, mips, riscv, loongarch
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:Type: vcpu ioctl
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:Parameters: struct kvm_interrupt (in)
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:Returns: 0 on success, negative on failure.
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@@ -540,7 +547,7 @@ ioctl is useful if the in-kernel PIC is not used.
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PPC:
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^^^^
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Queues an external interrupt to be injected. This ioctl is overleaded
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Queues an external interrupt to be injected. This ioctl is overloaded
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with 3 different irq values:
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a) KVM_INTERRUPT_SET
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@@ -592,6 +599,14 @@ b) KVM_INTERRUPT_UNSET
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This is an asynchronous vcpu ioctl and can be invoked from any thread.
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LOONGARCH:
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^^^^^^^^^^
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Queues an external interrupt to be injected into the virtual CPU. A negative
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interrupt number dequeues the interrupt.
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This is an asynchronous vcpu ioctl and can be invoked from any thread.
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4.17 KVM_DEBUG_GUEST
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--------------------
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@@ -737,7 +752,7 @@ signal mask.
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----------------
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:Capability: basic
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:Architectures: x86
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:Architectures: x86, loongarch
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:Type: vcpu ioctl
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:Parameters: struct kvm_fpu (out)
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:Returns: 0 on success, -1 on error
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@@ -746,7 +761,7 @@ Reads the floating point state from the vcpu.
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::
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/* for KVM_GET_FPU and KVM_SET_FPU */
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/* x86: for KVM_GET_FPU and KVM_SET_FPU */
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struct kvm_fpu {
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__u8 fpr[8][16];
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__u16 fcw;
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@@ -761,12 +776,21 @@ Reads the floating point state from the vcpu.
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__u32 pad2;
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};
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/* LoongArch: for KVM_GET_FPU and KVM_SET_FPU */
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struct kvm_fpu {
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__u32 fcsr;
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__u64 fcc;
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struct kvm_fpureg {
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__u64 val64[4];
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}fpr[32];
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};
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4.23 KVM_SET_FPU
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----------------
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:Capability: basic
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:Architectures: x86
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:Architectures: x86, loongarch
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:Type: vcpu ioctl
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:Parameters: struct kvm_fpu (in)
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:Returns: 0 on success, -1 on error
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@@ -775,7 +799,7 @@ Writes the floating point state to the vcpu.
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::
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/* for KVM_GET_FPU and KVM_SET_FPU */
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/* x86: for KVM_GET_FPU and KVM_SET_FPU */
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struct kvm_fpu {
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__u8 fpr[8][16];
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__u16 fcw;
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@@ -790,6 +814,15 @@ Writes the floating point state to the vcpu.
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__u32 pad2;
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};
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/* LoongArch: for KVM_GET_FPU and KVM_SET_FPU */
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struct kvm_fpu {
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__u32 fcsr;
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__u64 fcc;
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struct kvm_fpureg {
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__u64 val64[4];
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}fpr[32];
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};
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4.24 KVM_CREATE_IRQCHIP
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-----------------------
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@@ -965,7 +998,7 @@ be set in the flags field of this ioctl:
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The KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL flag requests KVM to generate
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the contents of the hypercall page automatically; hypercalls will be
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intercepted and passed to userspace through KVM_EXIT_XEN. In this
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ase, all of the blob size and address fields must be zero.
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case, all of the blob size and address fields must be zero.
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The KVM_XEN_HVM_CONFIG_EVTCHN_SEND flag indicates to KVM that userspace
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will always use the KVM_XEN_HVM_EVTCHN_SEND ioctl to deliver event
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@@ -1070,7 +1103,7 @@ Other flags returned by ``KVM_GET_CLOCK`` are accepted but ignored.
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:Extended by: KVM_CAP_INTR_SHADOW
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:Architectures: x86, arm64
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:Type: vcpu ioctl
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:Parameters: struct kvm_vcpu_event (out)
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:Parameters: struct kvm_vcpu_events (out)
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:Returns: 0 on success, -1 on error
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X86:
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@@ -1193,7 +1226,7 @@ directly to the virtual CPU).
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:Extended by: KVM_CAP_INTR_SHADOW
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:Architectures: x86, arm64
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:Type: vcpu ioctl
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:Parameters: struct kvm_vcpu_event (in)
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:Parameters: struct kvm_vcpu_events (in)
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:Returns: 0 on success, -1 on error
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X86:
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@@ -1387,7 +1420,7 @@ documentation when it pops into existence).
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-------------------
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:Capability: KVM_CAP_ENABLE_CAP
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:Architectures: mips, ppc, s390, x86
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:Architectures: mips, ppc, s390, x86, loongarch
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:Type: vcpu ioctl
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:Parameters: struct kvm_enable_cap (in)
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:Returns: 0 on success; -1 on error
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@@ -1442,7 +1475,7 @@ for vm-wide capabilities.
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---------------------
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:Capability: KVM_CAP_MP_STATE
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:Architectures: x86, s390, arm64, riscv
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:Architectures: x86, s390, arm64, riscv, loongarch
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:Type: vcpu ioctl
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:Parameters: struct kvm_mp_state (out)
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:Returns: 0 on success; -1 on error
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@@ -1460,7 +1493,7 @@ Possible values are:
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========================== ===============================================
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KVM_MP_STATE_RUNNABLE the vcpu is currently running
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[x86,arm64,riscv]
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[x86,arm64,riscv,loongarch]
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KVM_MP_STATE_UNINITIALIZED the vcpu is an application processor (AP)
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which has not yet received an INIT signal [x86]
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KVM_MP_STATE_INIT_RECEIVED the vcpu has received an INIT signal, and is
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@@ -1516,11 +1549,14 @@ For riscv:
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The only states that are valid are KVM_MP_STATE_STOPPED and
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KVM_MP_STATE_RUNNABLE which reflect if the vcpu is paused or not.
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On LoongArch, only the KVM_MP_STATE_RUNNABLE state is used to reflect
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whether the vcpu is runnable.
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4.39 KVM_SET_MP_STATE
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---------------------
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:Capability: KVM_CAP_MP_STATE
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:Architectures: x86, s390, arm64, riscv
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:Architectures: x86, s390, arm64, riscv, loongarch
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:Type: vcpu ioctl
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:Parameters: struct kvm_mp_state (in)
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:Returns: 0 on success; -1 on error
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@@ -1538,6 +1574,9 @@ For arm64/riscv:
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The only states that are valid are KVM_MP_STATE_STOPPED and
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KVM_MP_STATE_RUNNABLE which reflect if the vcpu should be paused or not.
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On LoongArch, only the KVM_MP_STATE_RUNNABLE state is used to reflect
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whether the vcpu is runnable.
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4.40 KVM_SET_IDENTITY_MAP_ADDR
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------------------------------
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@@ -2841,6 +2880,19 @@ Following are the RISC-V D-extension registers:
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0x8020 0000 0600 0020 fcsr Floating point control and status register
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======================= ========= =============================================
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LoongArch registers are mapped using the lower 32 bits. The upper 16 bits of
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that is the register group type.
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LoongArch csr registers are used to control guest cpu or get status of guest
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cpu, and they have the following id bit patterns::
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0x9030 0000 0001 00 <reg:5> <sel:3> (64-bit)
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LoongArch KVM control registers are used to implement some new defined functions
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such as set vcpu counter or reset vcpu, and they have the following id bit patterns::
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0x9030 0000 0002 <reg:16>
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4.69 KVM_GET_ONE_REG
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--------------------
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@@ -3063,7 +3115,7 @@ as follow::
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};
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An entry with a "page_shift" of 0 is unused. Because the array is
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organized in increasing order, a lookup can stop when encoutering
|
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organized in increasing order, a lookup can stop when encountering
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such an entry.
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The "slb_enc" field provides the encoding to use in the SLB for the
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@@ -3370,6 +3422,8 @@ return indicates the attribute is implemented. It does not necessarily
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indicate that the attribute can be read or written in the device's
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current state. "addr" is ignored.
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.. _KVM_ARM_VCPU_INIT:
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4.82 KVM_ARM_VCPU_INIT
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----------------------
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@@ -3455,7 +3509,7 @@ Possible features:
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- KVM_RUN and KVM_GET_REG_LIST are not available;
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- KVM_GET_ONE_REG and KVM_SET_ONE_REG cannot be used to access
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the scalable archietctural SVE registers
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the scalable architectural SVE registers
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KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() or
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KVM_REG_ARM64_SVE_FFR;
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||||
@@ -4401,7 +4455,7 @@ This will have undefined effects on the guest if it has not already
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placed itself in a quiescent state where no vcpu will make MMU enabled
|
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memory accesses.
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On succsful completion, the pending HPT will become the guest's active
|
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On successful completion, the pending HPT will become the guest's active
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HPT and the previous HPT will be discarded.
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On failure, the guest will still be operating on its previous HPT.
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@@ -5016,7 +5070,7 @@ before the vcpu is fully usable.
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|
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Between KVM_ARM_VCPU_INIT and KVM_ARM_VCPU_FINALIZE, the feature may be
|
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configured by use of ioctls such as KVM_SET_ONE_REG. The exact configuration
|
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that should be performaned and how to do it are feature-dependent.
|
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that should be performed and how to do it are feature-dependent.
|
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|
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Other calls that depend on a particular feature being finalized, such as
|
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KVM_RUN, KVM_GET_REG_LIST, KVM_GET_ONE_REG and KVM_SET_ONE_REG, will fail with
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@@ -5124,6 +5178,24 @@ Valid values for 'action'::
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#define KVM_PMU_EVENT_ALLOW 0
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#define KVM_PMU_EVENT_DENY 1
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Via this API, KVM userspace can also control the behavior of the VM's fixed
|
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counters (if any) by configuring the "action" and "fixed_counter_bitmap" fields.
|
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|
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Specifically, KVM follows the following pseudo-code when determining whether to
|
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allow the guest FixCtr[i] to count its pre-defined fixed event::
|
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|
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FixCtr[i]_is_allowed = (action == ALLOW) && (bitmap & BIT(i)) ||
|
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(action == DENY) && !(bitmap & BIT(i));
|
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FixCtr[i]_is_denied = !FixCtr[i]_is_allowed;
|
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|
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KVM always consumes fixed_counter_bitmap, it's userspace's responsibility to
|
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ensure fixed_counter_bitmap is set correctly, e.g. if userspace wants to define
|
||||
a filter that only affects general purpose counters.
|
||||
|
||||
Note, the "events" field also applies to fixed counters' hardcoded event_select
|
||||
and unit_mask values. "fixed_counter_bitmap" has higher priority than "events"
|
||||
if there is a contradiction between the two.
|
||||
|
||||
4.121 KVM_PPC_SVM_OFF
|
||||
---------------------
|
||||
|
||||
@@ -5475,7 +5547,7 @@ KVM_XEN_ATTR_TYPE_EVTCHN
|
||||
from the guest. A given sending port number may be directed back to
|
||||
a specified vCPU (by APIC ID) / port / priority on the guest, or to
|
||||
trigger events on an eventfd. The vCPU and priority can be changed
|
||||
by setting KVM_XEN_EVTCHN_UPDATE in a subsequent call, but but other
|
||||
by setting KVM_XEN_EVTCHN_UPDATE in a subsequent call, but other
|
||||
fields cannot change for a given sending port. A port mapping is
|
||||
removed by using KVM_XEN_EVTCHN_DEASSIGN in the flags field. Passing
|
||||
KVM_XEN_EVTCHN_RESET in the flags field removes all interception of
|
||||
@@ -6070,6 +6142,56 @@ writes to the CNTVCT_EL0 and CNTPCT_EL0 registers using the SET_ONE_REG
|
||||
interface. No error will be returned, but the resulting offset will not be
|
||||
applied.
|
||||
|
||||
.. _KVM_ARM_GET_REG_WRITABLE_MASKS:
|
||||
|
||||
4.139 KVM_ARM_GET_REG_WRITABLE_MASKS
|
||||
-------------------------------------------
|
||||
|
||||
:Capability: KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES
|
||||
:Architectures: arm64
|
||||
:Type: vm ioctl
|
||||
:Parameters: struct reg_mask_range (in/out)
|
||||
:Returns: 0 on success, < 0 on error
|
||||
|
||||
|
||||
::
|
||||
|
||||
#define KVM_ARM_FEATURE_ID_RANGE 0
|
||||
#define KVM_ARM_FEATURE_ID_RANGE_SIZE (3 * 8 * 8)
|
||||
|
||||
struct reg_mask_range {
|
||||
__u64 addr; /* Pointer to mask array */
|
||||
__u32 range; /* Requested range */
|
||||
__u32 reserved[13];
|
||||
};
|
||||
|
||||
This ioctl copies the writable masks for a selected range of registers to
|
||||
userspace.
|
||||
|
||||
The ``addr`` field is a pointer to the destination array where KVM copies
|
||||
the writable masks.
|
||||
|
||||
The ``range`` field indicates the requested range of registers.
|
||||
``KVM_CHECK_EXTENSION`` for the ``KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES``
|
||||
capability returns the supported ranges, expressed as a set of flags. Each
|
||||
flag's bit index represents a possible value for the ``range`` field.
|
||||
All other values are reserved for future use and KVM may return an error.
|
||||
|
||||
The ``reserved[13]`` array is reserved for future use and should be 0, or
|
||||
KVM may return an error.
|
||||
|
||||
KVM_ARM_FEATURE_ID_RANGE (0)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The Feature ID range is defined as the AArch64 System register space with
|
||||
op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, op2=={0-7}.
|
||||
|
||||
The mask returned array pointed to by ``addr`` is indexed by the macro
|
||||
``ARM64_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2)``, allowing userspace
|
||||
to know what fields can be changed for the system register described by
|
||||
``op0, op1, crn, crm, op2``. KVM rejects ID register values that describe a
|
||||
superset of the features supported by the system.
|
||||
|
||||
5. The kvm_run structure
|
||||
========================
|
||||
|
||||
|
||||
@@ -11,3 +11,4 @@ ARM
|
||||
hypercalls
|
||||
pvtime
|
||||
ptp_kvm
|
||||
vcpu-features
|
||||
|
||||
48
Documentation/virt/kvm/arm/vcpu-features.rst
Normal file
48
Documentation/virt/kvm/arm/vcpu-features.rst
Normal file
@@ -0,0 +1,48 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
===============================
|
||||
vCPU feature selection on arm64
|
||||
===============================
|
||||
|
||||
KVM/arm64 provides two mechanisms that allow userspace to configure
|
||||
the CPU features presented to the guest.
|
||||
|
||||
KVM_ARM_VCPU_INIT
|
||||
=================
|
||||
|
||||
The ``KVM_ARM_VCPU_INIT`` ioctl accepts a bitmap of feature flags
|
||||
(``struct kvm_vcpu_init::features``). Features enabled by this interface are
|
||||
*opt-in* and may change/extend UAPI. See :ref:`KVM_ARM_VCPU_INIT` for complete
|
||||
documentation of the features controlled by the ioctl.
|
||||
|
||||
Otherwise, all CPU features supported by KVM are described by the architected
|
||||
ID registers.
|
||||
|
||||
The ID Registers
|
||||
================
|
||||
|
||||
The Arm architecture specifies a range of *ID Registers* that describe the set
|
||||
of architectural features supported by the CPU implementation. KVM initializes
|
||||
the guest's ID registers to the maximum set of CPU features supported by the
|
||||
system. The ID register values may be VM-scoped in KVM, meaning that the
|
||||
values could be shared for all vCPUs in a VM.
|
||||
|
||||
KVM allows userspace to *opt-out* of certain CPU features described by the ID
|
||||
registers by writing values to them via the ``KVM_SET_ONE_REG`` ioctl. The ID
|
||||
registers are mutable until the VM has started, i.e. userspace has called
|
||||
``KVM_RUN`` on at least one vCPU in the VM. Userspace can discover what fields
|
||||
are mutable in the ID registers using the ``KVM_ARM_GET_REG_WRITABLE_MASKS``.
|
||||
See the :ref:`ioctl documentation <KVM_ARM_GET_REG_WRITABLE_MASKS>` for more
|
||||
details.
|
||||
|
||||
Userspace is allowed to *limit* or *mask* CPU features according to the rules
|
||||
outlined by the architecture in DDI0487J.a D19.1.3 'Principles of the ID
|
||||
scheme for fields in ID register'. KVM does not allow ID register values that
|
||||
exceed the capabilities of the system.
|
||||
|
||||
.. warning::
|
||||
It is **strongly recommended** that userspace modify the ID register values
|
||||
before accessing the rest of the vCPU's CPU register state. KVM may use the
|
||||
ID register values to control feature emulation. Interleaving ID register
|
||||
modification with other system register accesses may lead to unpredictable
|
||||
behavior.
|
||||
@@ -59,6 +59,13 @@ Groups:
|
||||
It is invalid to mix calls with KVM_VGIC_V3_ADDR_TYPE_REDIST and
|
||||
KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION attributes.
|
||||
|
||||
Note that to obtain reproducible results (the same VCPU being associated
|
||||
with the same redistributor across a save/restore operation), VCPU creation
|
||||
order, redistributor region creation order as well as the respective
|
||||
interleaves of VCPU and region creation MUST be preserved. Any change in
|
||||
either ordering may result in a different vcpu_id/redistributor association,
|
||||
resulting in a VM that will fail to run at restore time.
|
||||
|
||||
Errors:
|
||||
|
||||
======= =============================================================
|
||||
|
||||
@@ -202,10 +202,22 @@ Shadow pages contain the following information:
|
||||
Is 1 if the MMU instance cannot use A/D bits. EPT did not have A/D
|
||||
bits before Haswell; shadow EPT page tables also cannot use A/D bits
|
||||
if the L1 hypervisor does not enable them.
|
||||
role.guest_mode:
|
||||
Indicates the shadow page is created for a nested guest.
|
||||
role.passthrough:
|
||||
The page is not backed by a guest page table, but its first entry
|
||||
points to one. This is set if NPT uses 5-level page tables (host
|
||||
CR4.LA57=1) and is shadowing L1's 4-level NPT (L1 CR4.LA57=0).
|
||||
mmu_valid_gen:
|
||||
The MMU generation of this page, used to fast zap of all MMU pages within a
|
||||
VM without blocking vCPUs too long. Specifically, KVM updates the per-VM
|
||||
valid MMU generation which causes the mismatch of mmu_valid_gen for each mmu
|
||||
page. This makes all existing MMU pages obsolete. Obsolete pages can't be
|
||||
used. Therefore, vCPUs must load a new, valid root before re-entering the
|
||||
guest. The MMU generation is only ever '0' or '1'. Note, the TDP MMU doesn't
|
||||
use this field as non-root TDP MMU pages are reachable only from their
|
||||
owning root. Thus it suffices for TDP MMU to use role.invalid in root pages
|
||||
to invalidate all MMU pages.
|
||||
gfn:
|
||||
Either the guest page table containing the translations shadowed by this
|
||||
page, or the base page frame for linear translations. See role.direct.
|
||||
@@ -219,21 +231,30 @@ Shadow pages contain the following information:
|
||||
at __pa(sp2->spt). sp2 will point back at sp1 through parent_pte.
|
||||
The spt array forms a DAG structure with the shadow page as a node, and
|
||||
guest pages as leaves.
|
||||
gfns:
|
||||
An array of 512 guest frame numbers, one for each present pte. Used to
|
||||
perform a reverse map from a pte to a gfn. When role.direct is set, any
|
||||
element of this array can be calculated from the gfn field when used, in
|
||||
this case, the array of gfns is not allocated. See role.direct and gfn.
|
||||
root_count:
|
||||
A counter keeping track of how many hardware registers (guest cr3 or
|
||||
pdptrs) are now pointing at the page. While this counter is nonzero, the
|
||||
page cannot be destroyed. See role.invalid.
|
||||
shadowed_translation:
|
||||
An array of 512 shadow translation entries, one for each present pte. Used
|
||||
to perform a reverse map from a pte to a gfn as well as its access
|
||||
permission. When role.direct is set, the shadow_translation array is not
|
||||
allocated. This is because the gfn contained in any element of this array
|
||||
can be calculated from the gfn field when used. In addition, when
|
||||
role.direct is set, KVM does not track access permission for each of the
|
||||
gfn. See role.direct and gfn.
|
||||
root_count / tdp_mmu_root_count:
|
||||
root_count is a reference counter for root shadow pages in Shadow MMU.
|
||||
vCPUs elevate the refcount when getting a shadow page that will be used as
|
||||
a root page, i.e. page that will be loaded into hardware directly (CR3,
|
||||
PDPTRs, nCR3 EPTP). Root pages cannot be destroyed while their refcount is
|
||||
non-zero. See role.invalid. tdp_mmu_root_count is similar but exclusively
|
||||
used in TDP MMU as an atomic refcount.
|
||||
parent_ptes:
|
||||
The reverse mapping for the pte/ptes pointing at this page's spt. If
|
||||
parent_ptes bit 0 is zero, only one spte points at this page and
|
||||
parent_ptes points at this single spte, otherwise, there exists multiple
|
||||
sptes pointing at this page and (parent_ptes & ~0x1) points at a data
|
||||
structure with a list of parent sptes.
|
||||
ptep:
|
||||
The kernel virtual address of the SPTE that points at this shadow page.
|
||||
Used exclusively by the TDP MMU, this field is a union with parent_ptes.
|
||||
unsync:
|
||||
If true, then the translations in this page may not match the guest's
|
||||
translation. This is equivalent to the state of the tlb when a pte is
|
||||
@@ -261,6 +282,10 @@ Shadow pages contain the following information:
|
||||
since the last time the page table was actually used; if emulation
|
||||
is triggered too frequently on this page, KVM will unmap the page
|
||||
to avoid emulation in the future.
|
||||
tdp_mmu_page:
|
||||
Is 1 if the shadow page is a TDP MMU page. This variable is used to
|
||||
bifurcate the control flows for KVM when walking any data structure that
|
||||
may contain pages from both TDP MMU and shadow MMU.
|
||||
|
||||
Reverse map
|
||||
===========
|
||||
|
||||
13
MAINTAINERS
13
MAINTAINERS
@@ -11604,6 +11604,18 @@ F: include/kvm/arm_*
|
||||
F: tools/testing/selftests/kvm/*/aarch64/
|
||||
F: tools/testing/selftests/kvm/aarch64/
|
||||
|
||||
KERNEL VIRTUAL MACHINE FOR LOONGARCH (KVM/LoongArch)
|
||||
M: Tianrui Zhao <zhaotianrui@loongson.cn>
|
||||
M: Bibo Mao <maobibo@loongson.cn>
|
||||
M: Huacai Chen <chenhuacai@kernel.org>
|
||||
L: kvm@vger.kernel.org
|
||||
L: loongarch@lists.linux.dev
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
|
||||
F: arch/loongarch/include/asm/kvm*
|
||||
F: arch/loongarch/include/uapi/asm/kvm*
|
||||
F: arch/loongarch/kvm/
|
||||
|
||||
KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips)
|
||||
M: Huacai Chen <chenhuacai@kernel.org>
|
||||
L: linux-mips@vger.kernel.org
|
||||
@@ -11640,6 +11652,7 @@ F: arch/riscv/include/asm/kvm*
|
||||
F: arch/riscv/include/uapi/asm/kvm*
|
||||
F: arch/riscv/kvm/
|
||||
F: tools/testing/selftests/kvm/*/riscv/
|
||||
F: tools/testing/selftests/kvm/riscv/
|
||||
|
||||
KERNEL VIRTUAL MACHINE for s390 (KVM/s390)
|
||||
M: Christian Borntraeger <borntraeger@linux.ibm.com>
|
||||
|
||||
@@ -102,7 +102,9 @@
|
||||
#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)
|
||||
#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
|
||||
|
||||
#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En)
|
||||
#define HCRX_GUEST_FLAGS \
|
||||
(HCRX_EL2_SMPME | HCRX_EL2_TCR2En | \
|
||||
(cpus_have_final_cap(ARM64_HAS_MOPS) ? (HCRX_EL2_MSCEn | HCRX_EL2_MCE2) : 0))
|
||||
#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En)
|
||||
|
||||
/* TCR_EL2 Registers bits */
|
||||
|
||||
@@ -54,6 +54,11 @@ void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu);
|
||||
int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2);
|
||||
int kvm_inject_nested_irq(struct kvm_vcpu *vcpu);
|
||||
|
||||
static inline bool vcpu_has_feature(const struct kvm_vcpu *vcpu, int feature)
|
||||
{
|
||||
return test_bit(feature, vcpu->kvm->arch.vcpu_features);
|
||||
}
|
||||
|
||||
#if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__)
|
||||
static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
@@ -62,7 +67,7 @@ static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
|
||||
#else
|
||||
static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features);
|
||||
return vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -465,7 +470,7 @@ static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
|
||||
|
||||
static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
|
||||
return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
|
||||
}
|
||||
|
||||
static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
|
||||
@@ -565,12 +570,6 @@ static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu)
|
||||
vcpu_set_flag((v), e); \
|
||||
} while (0)
|
||||
|
||||
|
||||
static inline bool vcpu_has_feature(struct kvm_vcpu *vcpu, int feature)
|
||||
{
|
||||
return test_bit(feature, vcpu->arch.features);
|
||||
}
|
||||
|
||||
static __always_inline void kvm_write_cptr_el2(u64 val)
|
||||
{
|
||||
if (has_vhe() || has_hvhe())
|
||||
|
||||
@@ -78,7 +78,7 @@ extern unsigned int __ro_after_init kvm_sve_max_vl;
|
||||
int __init kvm_arm_init_sve(void);
|
||||
|
||||
u32 __attribute_const__ kvm_target_cpu(void);
|
||||
int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
|
||||
void kvm_reset_vcpu(struct kvm_vcpu *vcpu);
|
||||
void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
|
||||
|
||||
struct kvm_hyp_memcache {
|
||||
@@ -158,6 +158,16 @@ struct kvm_s2_mmu {
|
||||
phys_addr_t pgd_phys;
|
||||
struct kvm_pgtable *pgt;
|
||||
|
||||
/*
|
||||
* VTCR value used on the host. For a non-NV guest (or a NV
|
||||
* guest that runs in a context where its own S2 doesn't
|
||||
* apply), its T0SZ value reflects that of the IPA size.
|
||||
*
|
||||
* For a shadow S2 MMU, T0SZ reflects the PARange exposed to
|
||||
* the guest.
|
||||
*/
|
||||
u64 vtcr;
|
||||
|
||||
/* The last vcpu id that ran on each physical CPU */
|
||||
int __percpu *last_vcpu_ran;
|
||||
|
||||
@@ -202,12 +212,34 @@ struct kvm_protected_vm {
|
||||
struct kvm_hyp_memcache teardown_mc;
|
||||
};
|
||||
|
||||
struct kvm_mpidr_data {
|
||||
u64 mpidr_mask;
|
||||
DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx);
|
||||
};
|
||||
|
||||
static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr)
|
||||
{
|
||||
unsigned long mask = data->mpidr_mask;
|
||||
u64 aff = mpidr & MPIDR_HWID_BITMASK;
|
||||
int nbits, bit, bit_idx = 0;
|
||||
u16 index = 0;
|
||||
|
||||
/*
|
||||
* If this looks like RISC-V's BEXT or x86's PEXT
|
||||
* instructions, it isn't by accident.
|
||||
*/
|
||||
nbits = fls(mask);
|
||||
for_each_set_bit(bit, &mask, nbits) {
|
||||
index |= (aff & BIT(bit)) >> (bit - bit_idx);
|
||||
bit_idx++;
|
||||
}
|
||||
|
||||
return index;
|
||||
}
|
||||
|
||||
struct kvm_arch {
|
||||
struct kvm_s2_mmu mmu;
|
||||
|
||||
/* VTCR_EL2 value for this VM */
|
||||
u64 vtcr;
|
||||
|
||||
/* Interrupt controller */
|
||||
struct vgic_dist vgic;
|
||||
|
||||
@@ -239,15 +271,16 @@ struct kvm_arch {
|
||||
#define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5
|
||||
/* Timer PPIs made immutable */
|
||||
#define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6
|
||||
/* SMCCC filter initialized for the VM */
|
||||
#define KVM_ARCH_FLAG_SMCCC_FILTER_CONFIGURED 7
|
||||
/* Initial ID reg values loaded */
|
||||
#define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 8
|
||||
#define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7
|
||||
unsigned long flags;
|
||||
|
||||
/* VM-wide vCPU feature set */
|
||||
DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES);
|
||||
|
||||
/* MPIDR to vcpu index mapping, optional */
|
||||
struct kvm_mpidr_data *mpidr_data;
|
||||
|
||||
/*
|
||||
* VM-wide PMU filter, implemented as a bitmap and big enough for
|
||||
* up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
|
||||
@@ -257,6 +290,9 @@ struct kvm_arch {
|
||||
|
||||
cpumask_var_t supported_cpus;
|
||||
|
||||
/* PMCR_EL0.N value for the guest */
|
||||
u8 pmcr_n;
|
||||
|
||||
/* Hypercall features firmware registers' descriptor */
|
||||
struct kvm_smccc_features smccc_feat;
|
||||
struct maple_tree smccc_filter;
|
||||
@@ -574,9 +610,6 @@ struct kvm_vcpu_arch {
|
||||
/* Cache some mmu pages needed inside spinlock regions */
|
||||
struct kvm_mmu_memory_cache mmu_page_cache;
|
||||
|
||||
/* feature flags */
|
||||
DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
|
||||
|
||||
/* Virtual SError ESR to restore when HCR_EL2.VSE is set */
|
||||
u64 vsesr_el2;
|
||||
|
||||
@@ -1025,7 +1058,7 @@ int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
|
||||
extern unsigned int __ro_after_init kvm_arm_vmid_bits;
|
||||
int __init kvm_arm_vmid_alloc_init(void);
|
||||
void __init kvm_arm_vmid_alloc_free(void);
|
||||
void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
|
||||
bool kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
|
||||
void kvm_arm_vmid_clear_active(void);
|
||||
|
||||
static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
|
||||
@@ -1078,6 +1111,8 @@ int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
|
||||
struct kvm_arm_copy_mte_tags *copy_tags);
|
||||
int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm,
|
||||
struct kvm_arm_counter_offset *offset);
|
||||
int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm,
|
||||
struct reg_mask_range *range);
|
||||
|
||||
/* Guest/host FPSIMD coordination helpers */
|
||||
int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
|
||||
@@ -1109,8 +1144,8 @@ static inline bool kvm_set_pmuserenr(u64 val)
|
||||
}
|
||||
#endif
|
||||
|
||||
void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
|
||||
void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu);
|
||||
void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu);
|
||||
void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu);
|
||||
|
||||
int __init kvm_set_ipa_limit(void);
|
||||
|
||||
|
||||
@@ -93,6 +93,8 @@ void __timer_disable_traps(struct kvm_vcpu *vcpu);
|
||||
void __sysreg_save_state_nvhe(struct kvm_cpu_context *ctxt);
|
||||
void __sysreg_restore_state_nvhe(struct kvm_cpu_context *ctxt);
|
||||
#else
|
||||
void __vcpu_load_switch_sysregs(struct kvm_vcpu *vcpu);
|
||||
void __vcpu_put_switch_sysregs(struct kvm_vcpu *vcpu);
|
||||
void sysreg_save_host_state_vhe(struct kvm_cpu_context *ctxt);
|
||||
void sysreg_restore_host_state_vhe(struct kvm_cpu_context *ctxt);
|
||||
void sysreg_save_guest_state_vhe(struct kvm_cpu_context *ctxt);
|
||||
@@ -111,11 +113,6 @@ void __fpsimd_save_state(struct user_fpsimd_state *fp_regs);
|
||||
void __fpsimd_restore_state(struct user_fpsimd_state *fp_regs);
|
||||
void __sve_restore_state(void *sve_pffr, u32 *fpsr);
|
||||
|
||||
#ifndef __KVM_NVHE_HYPERVISOR__
|
||||
void activate_traps_vhe_load(struct kvm_vcpu *vcpu);
|
||||
void deactivate_traps_vhe_put(struct kvm_vcpu *vcpu);
|
||||
#endif
|
||||
|
||||
u64 __guest_enter(struct kvm_vcpu *vcpu);
|
||||
|
||||
bool kvm_host_psci_handler(struct kvm_cpu_context *host_ctxt, u32 func_id);
|
||||
|
||||
@@ -150,9 +150,9 @@ static __always_inline unsigned long __kern_hyp_va(unsigned long v)
|
||||
*/
|
||||
#define KVM_PHYS_SHIFT (40)
|
||||
|
||||
#define kvm_phys_shift(kvm) VTCR_EL2_IPA(kvm->arch.vtcr)
|
||||
#define kvm_phys_size(kvm) (_AC(1, ULL) << kvm_phys_shift(kvm))
|
||||
#define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL))
|
||||
#define kvm_phys_shift(mmu) VTCR_EL2_IPA((mmu)->vtcr)
|
||||
#define kvm_phys_size(mmu) (_AC(1, ULL) << kvm_phys_shift(mmu))
|
||||
#define kvm_phys_mask(mmu) (kvm_phys_size(mmu) - _AC(1, ULL))
|
||||
|
||||
#include <asm/kvm_pgtable.h>
|
||||
#include <asm/stage2_pgtable.h>
|
||||
@@ -224,16 +224,41 @@ static inline void __clean_dcache_guest_page(void *va, size_t size)
|
||||
kvm_flush_dcache_to_poc(va, size);
|
||||
}
|
||||
|
||||
static inline size_t __invalidate_icache_max_range(void)
|
||||
{
|
||||
u8 iminline;
|
||||
u64 ctr;
|
||||
|
||||
asm volatile(ALTERNATIVE_CB("movz %0, #0\n"
|
||||
"movk %0, #0, lsl #16\n"
|
||||
"movk %0, #0, lsl #32\n"
|
||||
"movk %0, #0, lsl #48\n",
|
||||
ARM64_ALWAYS_SYSTEM,
|
||||
kvm_compute_final_ctr_el0)
|
||||
: "=r" (ctr));
|
||||
|
||||
iminline = SYS_FIELD_GET(CTR_EL0, IminLine, ctr) + 2;
|
||||
return MAX_DVM_OPS << iminline;
|
||||
}
|
||||
|
||||
static inline void __invalidate_icache_guest_page(void *va, size_t size)
|
||||
{
|
||||
if (icache_is_aliasing()) {
|
||||
/* any kind of VIPT cache */
|
||||
/*
|
||||
* VPIPT I-cache maintenance must be done from EL2. See comment in the
|
||||
* nVHE flavor of __kvm_tlb_flush_vmid_ipa().
|
||||
*/
|
||||
if (icache_is_vpipt() && read_sysreg(CurrentEL) != CurrentEL_EL2)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Blow the whole I-cache if it is aliasing (i.e. VIPT) or the
|
||||
* invalidation range exceeds our arbitrary limit on invadations by
|
||||
* cache line.
|
||||
*/
|
||||
if (icache_is_aliasing() || size > __invalidate_icache_max_range())
|
||||
icache_inval_all_pou();
|
||||
} else if (read_sysreg(CurrentEL) != CurrentEL_EL1 ||
|
||||
!icache_is_vpipt()) {
|
||||
/* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */
|
||||
else
|
||||
icache_inval_pou((unsigned long)va, (unsigned long)va + size);
|
||||
}
|
||||
}
|
||||
|
||||
void kvm_set_way_flush(struct kvm_vcpu *vcpu);
|
||||
@@ -299,7 +324,7 @@ static __always_inline u64 kvm_get_vttbr(struct kvm_s2_mmu *mmu)
|
||||
static __always_inline void __load_stage2(struct kvm_s2_mmu *mmu,
|
||||
struct kvm_arch *arch)
|
||||
{
|
||||
write_sysreg(arch->vtcr, vtcr_el2);
|
||||
write_sysreg(mmu->vtcr, vtcr_el2);
|
||||
write_sysreg(kvm_get_vttbr(mmu), vttbr_el2);
|
||||
|
||||
/*
|
||||
|
||||
@@ -2,13 +2,14 @@
|
||||
#ifndef __ARM64_KVM_NESTED_H
|
||||
#define __ARM64_KVM_NESTED_H
|
||||
|
||||
#include <asm/kvm_emulate.h>
|
||||
#include <linux/kvm_host.h>
|
||||
|
||||
static inline bool vcpu_has_nv(const struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return (!__is_defined(__KVM_NVHE_HYPERVISOR__) &&
|
||||
cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) &&
|
||||
test_bit(KVM_ARM_VCPU_HAS_EL2, vcpu->arch.features));
|
||||
vcpu_has_feature(vcpu, KVM_ARM_VCPU_HAS_EL2));
|
||||
}
|
||||
|
||||
extern bool __check_nv_sr_forward(struct kvm_vcpu *vcpu);
|
||||
|
||||
@@ -21,13 +21,13 @@
|
||||
* (IPA_SHIFT - 4).
|
||||
*/
|
||||
#define stage2_pgtable_levels(ipa) ARM64_HW_PGTABLE_LEVELS((ipa) - 4)
|
||||
#define kvm_stage2_levels(kvm) VTCR_EL2_LVLS(kvm->arch.vtcr)
|
||||
#define kvm_stage2_levels(mmu) VTCR_EL2_LVLS((mmu)->vtcr)
|
||||
|
||||
/*
|
||||
* kvm_mmmu_cache_min_pages() is the number of pages required to install
|
||||
* a stage-2 translation. We pre-allocate the entry level page table at
|
||||
* the VM creation.
|
||||
*/
|
||||
#define kvm_mmu_cache_min_pages(kvm) (kvm_stage2_levels(kvm) - 1)
|
||||
#define kvm_mmu_cache_min_pages(mmu) (kvm_stage2_levels(mmu) - 1)
|
||||
|
||||
#endif /* __ARM64_S2_PGTABLE_H_ */
|
||||
|
||||
@@ -270,6 +270,8 @@
|
||||
/* ETM */
|
||||
#define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
|
||||
|
||||
#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
|
||||
|
||||
#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
|
||||
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
|
||||
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
|
||||
@@ -484,6 +486,7 @@
|
||||
|
||||
#define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
|
||||
#define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
|
||||
#define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
|
||||
#define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
|
||||
#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
|
||||
#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
|
||||
@@ -497,10 +500,15 @@
|
||||
#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
|
||||
|
||||
#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
|
||||
#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
|
||||
#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
|
||||
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
|
||||
#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
|
||||
#define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
|
||||
#define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
|
||||
#define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
|
||||
#define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
|
||||
#define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3)
|
||||
#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
|
||||
#define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
|
||||
#define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
|
||||
@@ -514,6 +522,18 @@
|
||||
|
||||
#define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
|
||||
#define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
|
||||
#define SYS_MPAMHCR_EL2 sys_reg(3, 4, 10, 4, 0)
|
||||
#define SYS_MPAMVPMV_EL2 sys_reg(3, 4, 10, 4, 1)
|
||||
#define SYS_MPAM2_EL2 sys_reg(3, 4, 10, 5, 0)
|
||||
#define __SYS__MPAMVPMx_EL2(x) sys_reg(3, 4, 10, 6, x)
|
||||
#define SYS_MPAMVPM0_EL2 __SYS__MPAMVPMx_EL2(0)
|
||||
#define SYS_MPAMVPM1_EL2 __SYS__MPAMVPMx_EL2(1)
|
||||
#define SYS_MPAMVPM2_EL2 __SYS__MPAMVPMx_EL2(2)
|
||||
#define SYS_MPAMVPM3_EL2 __SYS__MPAMVPMx_EL2(3)
|
||||
#define SYS_MPAMVPM4_EL2 __SYS__MPAMVPMx_EL2(4)
|
||||
#define SYS_MPAMVPM5_EL2 __SYS__MPAMVPMx_EL2(5)
|
||||
#define SYS_MPAMVPM6_EL2 __SYS__MPAMVPMx_EL2(6)
|
||||
#define SYS_MPAMVPM7_EL2 __SYS__MPAMVPMx_EL2(7)
|
||||
|
||||
#define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
|
||||
#define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
|
||||
@@ -562,24 +582,49 @@
|
||||
|
||||
#define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
|
||||
#define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
|
||||
#define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
|
||||
|
||||
#define __AMEV_op2(m) (m & 0x7)
|
||||
#define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3))
|
||||
#define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
|
||||
#define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m)
|
||||
#define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
|
||||
#define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m)
|
||||
|
||||
#define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
|
||||
#define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
|
||||
#define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
|
||||
#define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
|
||||
#define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
|
||||
#define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
|
||||
#define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
|
||||
#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
|
||||
|
||||
/* VHE encodings for architectural EL0/1 system registers */
|
||||
#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
|
||||
#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
|
||||
#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
|
||||
#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
|
||||
#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
|
||||
#define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1)
|
||||
#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
|
||||
#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
|
||||
#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
|
||||
#define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
|
||||
#define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3)
|
||||
#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
|
||||
#define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
|
||||
#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
|
||||
#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
|
||||
#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
|
||||
#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
|
||||
#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
|
||||
#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
|
||||
#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
|
||||
#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
|
||||
#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
|
||||
#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
|
||||
#define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
|
||||
#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
|
||||
#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
|
||||
#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
|
||||
|
||||
@@ -332,7 +332,7 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
|
||||
* This is meant to avoid soft lock-ups on large TLB flushing ranges and not
|
||||
* necessarily a performance improvement.
|
||||
*/
|
||||
#define MAX_TLBI_OPS PTRS_PER_PTE
|
||||
#define MAX_DVM_OPS PTRS_PER_PTE
|
||||
|
||||
/*
|
||||
* __flush_tlb_range_op - Perform TLBI operation upon a range
|
||||
@@ -412,12 +412,12 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
|
||||
|
||||
/*
|
||||
* When not uses TLB range ops, we can handle up to
|
||||
* (MAX_TLBI_OPS - 1) pages;
|
||||
* (MAX_DVM_OPS - 1) pages;
|
||||
* When uses TLB range ops, we can handle up to
|
||||
* (MAX_TLBI_RANGE_PAGES - 1) pages.
|
||||
*/
|
||||
if ((!system_supports_tlb_range() &&
|
||||
(end - start) >= (MAX_TLBI_OPS * stride)) ||
|
||||
(end - start) >= (MAX_DVM_OPS * stride)) ||
|
||||
pages >= MAX_TLBI_RANGE_PAGES) {
|
||||
flush_tlb_mm(vma->vm_mm);
|
||||
return;
|
||||
@@ -450,7 +450,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end
|
||||
{
|
||||
unsigned long addr;
|
||||
|
||||
if ((end - start) > (MAX_TLBI_OPS * PAGE_SIZE)) {
|
||||
if ((end - start) > (MAX_DVM_OPS * PAGE_SIZE)) {
|
||||
flush_tlb_all();
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -9,10 +9,9 @@
|
||||
|
||||
#include <linux/list.h>
|
||||
#include <asm/esr.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/sections.h>
|
||||
|
||||
struct pt_regs;
|
||||
|
||||
#ifdef CONFIG_ARMV8_DEPRECATED
|
||||
bool try_emulate_armv8_deprecated(struct pt_regs *regs, u32 insn);
|
||||
#else
|
||||
@@ -101,4 +100,55 @@ static inline unsigned long arm64_ras_serror_get_severity(unsigned long esr)
|
||||
|
||||
bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr);
|
||||
void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr);
|
||||
|
||||
static inline void arm64_mops_reset_regs(struct user_pt_regs *regs, unsigned long esr)
|
||||
{
|
||||
bool wrong_option = esr & ESR_ELx_MOPS_ISS_WRONG_OPTION;
|
||||
bool option_a = esr & ESR_ELx_MOPS_ISS_OPTION_A;
|
||||
int dstreg = ESR_ELx_MOPS_ISS_DESTREG(esr);
|
||||
int srcreg = ESR_ELx_MOPS_ISS_SRCREG(esr);
|
||||
int sizereg = ESR_ELx_MOPS_ISS_SIZEREG(esr);
|
||||
unsigned long dst, src, size;
|
||||
|
||||
dst = regs->regs[dstreg];
|
||||
src = regs->regs[srcreg];
|
||||
size = regs->regs[sizereg];
|
||||
|
||||
/*
|
||||
* Put the registers back in the original format suitable for a
|
||||
* prologue instruction, using the generic return routine from the
|
||||
* Arm ARM (DDI 0487I.a) rules CNTMJ and MWFQH.
|
||||
*/
|
||||
if (esr & ESR_ELx_MOPS_ISS_MEM_INST) {
|
||||
/* SET* instruction */
|
||||
if (option_a ^ wrong_option) {
|
||||
/* Format is from Option A; forward set */
|
||||
regs->regs[dstreg] = dst + size;
|
||||
regs->regs[sizereg] = -size;
|
||||
}
|
||||
} else {
|
||||
/* CPY* instruction */
|
||||
if (!(option_a ^ wrong_option)) {
|
||||
/* Format is from Option B */
|
||||
if (regs->pstate & PSR_N_BIT) {
|
||||
/* Backward copy */
|
||||
regs->regs[dstreg] = dst - size;
|
||||
regs->regs[srcreg] = src - size;
|
||||
}
|
||||
} else {
|
||||
/* Format is from Option A */
|
||||
if (size & BIT(63)) {
|
||||
/* Forward copy */
|
||||
regs->regs[dstreg] = dst + size;
|
||||
regs->regs[srcreg] = src + size;
|
||||
regs->regs[sizereg] = -size;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (esr & ESR_ELx_MOPS_ISS_FROM_EPILOGUE)
|
||||
regs->pc -= 8;
|
||||
else
|
||||
regs->pc -= 4;
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -505,6 +505,38 @@ struct kvm_smccc_filter {
|
||||
#define KVM_HYPERCALL_EXIT_SMC (1U << 0)
|
||||
#define KVM_HYPERCALL_EXIT_16BIT (1U << 1)
|
||||
|
||||
/*
|
||||
* Get feature ID registers userspace writable mask.
|
||||
*
|
||||
* From DDI0487J.a, D19.2.66 ("ID_AA64MMFR2_EL1, AArch64 Memory Model
|
||||
* Feature Register 2"):
|
||||
*
|
||||
* "The Feature ID space is defined as the System register space in
|
||||
* AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7},
|
||||
* op2=={0-7}."
|
||||
*
|
||||
* This covers all currently known R/O registers that indicate
|
||||
* anything useful feature wise, including the ID registers.
|
||||
*
|
||||
* If we ever need to introduce a new range, it will be described as
|
||||
* such in the range field.
|
||||
*/
|
||||
#define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \
|
||||
({ \
|
||||
__u64 __op1 = (op1) & 3; \
|
||||
__op1 -= (__op1 == 3); \
|
||||
(__op1 << 6 | ((crm) & 7) << 3 | (op2)); \
|
||||
})
|
||||
|
||||
#define KVM_ARM_FEATURE_ID_RANGE 0
|
||||
#define KVM_ARM_FEATURE_ID_RANGE_SIZE (3 * 8 * 8)
|
||||
|
||||
struct reg_mask_range {
|
||||
__u64 addr; /* Pointer to mask array */
|
||||
__u32 range; /* Requested range */
|
||||
__u32 reserved[13];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ARM_KVM_H__ */
|
||||
|
||||
@@ -516,53 +516,7 @@ void do_el1_fpac(struct pt_regs *regs, unsigned long esr)
|
||||
|
||||
void do_el0_mops(struct pt_regs *regs, unsigned long esr)
|
||||
{
|
||||
bool wrong_option = esr & ESR_ELx_MOPS_ISS_WRONG_OPTION;
|
||||
bool option_a = esr & ESR_ELx_MOPS_ISS_OPTION_A;
|
||||
int dstreg = ESR_ELx_MOPS_ISS_DESTREG(esr);
|
||||
int srcreg = ESR_ELx_MOPS_ISS_SRCREG(esr);
|
||||
int sizereg = ESR_ELx_MOPS_ISS_SIZEREG(esr);
|
||||
unsigned long dst, src, size;
|
||||
|
||||
dst = pt_regs_read_reg(regs, dstreg);
|
||||
src = pt_regs_read_reg(regs, srcreg);
|
||||
size = pt_regs_read_reg(regs, sizereg);
|
||||
|
||||
/*
|
||||
* Put the registers back in the original format suitable for a
|
||||
* prologue instruction, using the generic return routine from the
|
||||
* Arm ARM (DDI 0487I.a) rules CNTMJ and MWFQH.
|
||||
*/
|
||||
if (esr & ESR_ELx_MOPS_ISS_MEM_INST) {
|
||||
/* SET* instruction */
|
||||
if (option_a ^ wrong_option) {
|
||||
/* Format is from Option A; forward set */
|
||||
pt_regs_write_reg(regs, dstreg, dst + size);
|
||||
pt_regs_write_reg(regs, sizereg, -size);
|
||||
}
|
||||
} else {
|
||||
/* CPY* instruction */
|
||||
if (!(option_a ^ wrong_option)) {
|
||||
/* Format is from Option B */
|
||||
if (regs->pstate & PSR_N_BIT) {
|
||||
/* Backward copy */
|
||||
pt_regs_write_reg(regs, dstreg, dst - size);
|
||||
pt_regs_write_reg(regs, srcreg, src - size);
|
||||
}
|
||||
} else {
|
||||
/* Format is from Option A */
|
||||
if (size & BIT(63)) {
|
||||
/* Forward copy */
|
||||
pt_regs_write_reg(regs, dstreg, dst + size);
|
||||
pt_regs_write_reg(regs, srcreg, src + size);
|
||||
pt_regs_write_reg(regs, sizereg, -size);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (esr & ESR_ELx_MOPS_ISS_FROM_EPILOGUE)
|
||||
regs->pc -= 8;
|
||||
else
|
||||
regs->pc -= 4;
|
||||
arm64_mops_reset_regs(®s->user_regs, esr);
|
||||
|
||||
/*
|
||||
* If single stepping then finish the step before executing the
|
||||
|
||||
@@ -453,7 +453,7 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level,
|
||||
timer_ctx->irq.level);
|
||||
|
||||
if (!userspace_irqchip(vcpu->kvm)) {
|
||||
ret = kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
|
||||
ret = kvm_vgic_inject_irq(vcpu->kvm, vcpu,
|
||||
timer_irq(timer_ctx),
|
||||
timer_ctx->irq.level,
|
||||
timer_ctx);
|
||||
@@ -936,7 +936,7 @@ void kvm_timer_sync_user(struct kvm_vcpu *vcpu)
|
||||
unmask_vtimer_irq_user(vcpu);
|
||||
}
|
||||
|
||||
int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu)
|
||||
void kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct arch_timer_cpu *timer = vcpu_timer(vcpu);
|
||||
struct timer_map map;
|
||||
@@ -980,8 +980,6 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu)
|
||||
soft_timer_cancel(&map.emul_vtimer->hrtimer);
|
||||
if (map.emul_ptimer)
|
||||
soft_timer_cancel(&map.emul_ptimer->hrtimer);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void timer_context_init(struct kvm_vcpu *vcpu, int timerid)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user