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Merge tag 'pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Browse Source 
Pull pin control updates from Linus Walleij:
 "We have some patches to DTS[I] files in arm and arm64 as well, that
  were merged here as DT headers were being changed.

  The most interesting stuff is the Intel Tangier chip support and
  AMLogic C3 in my opinion.

  No core changes this time.

  Drivers:

   - Intel Tangier SoC pin control support

   - AMLogic C3 SoC pin control support

   - Texas Instruments AM654 SoC pin control support

   - Qualcomm SM8350 and SM6115 LPASS (Low Power Audio Sub-System) pin
     control support

   - Qualcomm PMX75 and PM7550BA (Power Management) pin control support

   - Qualcomm PMC8180 and PMC8180C (Power Management) pin control
     support

   - DROP the Oxnas driver as there is not enough of community interest
     to keep carrying this ARM(11) port

  Enhancements:

   - Bias control in the MT7986 pin control driver

   - Misc device tree binding enhancements such as the Broadcom 11351
     being converted to YAML

   - New macro: DEFINE_NOIRQ_DEV_PM_OPS() put to use

   - Clean up some SPDX headers

   - Handle non-unique devicetree subnode names in two Renesas drivers"

* tag 'pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
  pinctrl: mlxbf3: Remove gpio_disable_free()
  pinctrl: use capital "OR" for multiple licenses in SPDX
  dt-bindings: pinctrl: renesas,rza2: Use 'additionalProperties' for child nodes
  pinctrl: cherryview: fix address_space_handler() argument
  pinctrl: intel: consolidate ACPI dependency
  pinctrl: tegra: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: mvebu: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: at91: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: cherryview: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pm: Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: mediatek: assign functions to configure pin bias on MT7986
  pinctrl: mediatek: fix pull_type data for MT7981
  dt-bindings: pinctrl: aspeed: Allow only defined pin mux node properties
  dt-bindings: pinctrl: Drop 'phandle' properties
  pinctrl: lynxpoint: Make use of pm_ptr()
  pinctrl: baytrail: Make use of pm_ptr()
  pinctrl: intel: Switch to use exported namespace
  pinctrl: lynxpoint: reuse common functions from pinctrl-intel
  pinctrl: cherryview: reuse common functions from pinctrl-intel
  ...
This commit is contained in:
Linus Torvalds
2023-08-30 19:36:19 -07:00
parent bb511d4b25 82a65f0844
commit 4a3b1007ee
228 changed files with 3868 additions and 4297 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/omap/ctrl.txt
View File

@@ -8,7 +8,7 @@ control module driver itself.
See [2] for documentation about clock/clockdomain nodes.
[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
[2] Documentation/devicetree/bindings/clock/ti/*
Required properties:

47
Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
View File

@@ -1,47 +0,0 @@
* Oxford Semiconductor OXNAS SoC GPIO Controller
Please refer to gpio.txt for generic information regarding GPIO bindings.
Required properties:
- compatible: "oxsemi,ox810se-gpio" or "oxsemi,ox820-gpio"
- reg: Base address and length for the device.
- interrupts: The port interrupt shared by all pins.
- gpio-controller: Marks the port as GPIO controller.
- #gpio-cells: Two. The first cell is the pin number and
the second cell is used to specify the gpio polarity as defined in
defined in <dt-bindings/gpio/gpio.h>:
0 = GPIO_ACTIVE_HIGH
1 = GPIO_ACTIVE_LOW
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Two. The first cell is the GPIO number and second cell
is used to specify the trigger type as defined in
<dt-bindings/interrupt-controller/irq.h>:
IRQ_TYPE_EDGE_RISING
IRQ_TYPE_EDGE_FALLING
IRQ_TYPE_EDGE_BOTH
- gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the
gpio base and count, should be in the format of numeric-gpio-range as
specified in the gpio.txt file.
Example:
gpio0: gpio@0 {
compatible = "oxsemi,ox810se-gpio";
reg = <0x000000 0x100000>;
interrupts = <21>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pinctrl 0 0 32>;
};
keys {
...
button-esc {
label = "ESC";
linux,code = <1>;
gpios = <&gpio0 12 0>;
};
};

5
Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml
View File

@@ -15,6 +15,7 @@ allOf:
properties:
compatible:
enum:
- amlogic,c3-periphs-pinctrl
- amlogic,meson-a1-periphs-pinctrl
- amlogic,meson-s4-periphs-pinctrl
@@ -36,6 +37,10 @@ patternProperties:
- const: mux
- const: gpio
gpio-line-names:
minItems: 62 # A1
maxItems: 82 # S4
unevaluatedProperties:
type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins

7
Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml
View File

@@ -41,6 +41,13 @@ $defs:
gpio-ranges:
maxItems: 1
patternProperties:
"^.+-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog
required:
- reg
- reg-names

3
Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml
View File

@@ -36,6 +36,9 @@ patternProperties:
- const: ds
- const: gpio
gpio-line-names:
maxItems: 15
unevaluatedProperties:
type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins

3
Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml
View File

@@ -38,6 +38,9 @@ patternProperties:
- const: mux
- const: ds
gpio-line-names:
maxItems: 85
unevaluatedProperties:
type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins

4
Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml
View File

@@ -44,6 +44,10 @@ patternProperties:
- const: pull
- const: gpio
gpio-line-names:
minItems: 11 # GXL
maxItems: 16 # Meson8
unevaluatedProperties:
type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins

4
Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml
View File

@@ -45,6 +45,10 @@ patternProperties:
- const: pull-enable
- const: gpio
gpio-line-names:
minItems: 86 # AXG
maxItems: 120 # Meson8
unevaluatedProperties:
type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins

52
Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
View File

@@ -25,30 +25,32 @@ properties:
reg:
maxItems: 2
patternProperties:
'^.*$':
if:
type: object
then:
patternProperties:
"^function|groups$":
$ref: /schemas/types.yaml#/definitions/string
enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0,
GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4,
I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK,
MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2,
NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4,
NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0,
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3,
RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD,
SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO,
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU,
SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2,
TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM,
VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2]
additionalProperties:
$ref: pinmux-node.yaml#
additionalProperties: false
properties:
pins: true
bias-disable: true
patternProperties:
"^function|groups$":
enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0,
GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4,
I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK,
MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2,
NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4,
NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0,
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3,
RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD,
SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO,
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU,
SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2,
TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM,
VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2]
allOf:
- $ref: pinctrl.yaml#
@@ -56,8 +58,6 @@ allOf:
required:
- compatible
additionalProperties: false
examples:
- |
syscon: scu@1e6e2000 {

56
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
View File

@@ -37,32 +37,34 @@ properties:
0: compatible with "aspeed,ast2500-gfx", "syscon"
1: compatible with "aspeed,ast2500-lhc", "syscon"
patternProperties:
'^.*$':
if:
type: object
then:
patternProperties:
"^function|groups$":
$ref: /schemas/types.yaml#/definitions/string
enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2,
GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5,
I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, LAD2, LAD3, LCLK, LFRAME, LPCHC,
LPCPD, LPCPLUS, LPCPME, LPCRST, LPCSMI, LSIRQ, MAC1LINK, MAC2LINK,
MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2,
NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0,
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
RMII2, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13,
SALT14, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1,
SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, SPI1DEBUG,
SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, SPI2MOSI, TIMER3,
TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, TXD3, TXD4, UART6,
USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS,
VGAVS, VPI24, VPO, WDTRST1, WDTRST2]
additionalProperties:
$ref: pinmux-node.yaml#
additionalProperties: false
properties:
pins: true
bias-disable: true
patternProperties:
"^function|groups$":
enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2,
GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5,
I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, LAD2, LAD3, LCLK, LFRAME, LPCHC,
LPCPD, LPCPLUS, LPCPME, LPCRST, LPCSMI, LSIRQ, MAC1LINK, MAC2LINK,
MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2,
NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0,
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
RMII2, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13,
SALT14, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1,
SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, SPI1DEBUG,
SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, SPI2MOSI, TIMER3,
TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, TXD3, TXD4, UART6,
USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS,
VGAVS, VPI24, VPO, WDTRST1, WDTRST2]
allOf:
- $ref: pinctrl.yaml#
@@ -71,8 +73,6 @@ required:
- compatible
- aspeed,external-nodes
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/aspeed-clock.h>

118
Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
View File

@@ -23,65 +23,65 @@ properties:
compatible:
const: aspeed,ast2600-pinctrl
patternProperties:
'^.*$':
if:
type: object
then:
properties:
function:
$ref: /schemas/types.yaml#/definitions/string
enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT,
FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3,
GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5,
GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16,
I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5,
I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4,
NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2,
NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4,
NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11,
PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8,
PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14,
SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8,
SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14,
TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0,
THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12,
UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4 ]
additionalProperties:
$ref: pinmux-node.yaml#
additionalProperties: false
groups:
$ref: /schemas/types.yaml#/definitions/string
enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4,
EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP,
GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10,
I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5,
I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3,
MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4,
NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0,
PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2,
PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1,
SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0,
SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6,
SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2,
SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6,
TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3,
TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
WDTRST3, WDTRST4]
properties:
function:
enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT,
FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3,
GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5,
GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16,
I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5,
I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4,
NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2,
NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4,
NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11,
PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8,
PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14,
SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8,
SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14,
TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0,
THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12,
UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4 ]
groups:
enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4,
EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP,
GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10,
I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5,
I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3,
MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4,
NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0,
PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2,
PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1,
SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0,
SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6,
SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2,
SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6,
TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3,
TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
WDTRST3, WDTRST4]
pins: true
bias-disable: true
allOf:
- $ref: pinctrl.yaml#
@@ -89,8 +89,6 @@ allOf:
required:
- compatible
additionalProperties: false
examples:
- |
syscon: scu@1e6e2000 {

461
Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt
View File

@@ -1,461 +0,0 @@
Broadcom BCM281xx Pin Controller
This is a pin controller for the Broadcom BCM281xx SoC family, which includes
BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs.
=== Pin Controller Node ===
Required Properties:
- compatible: Must be "brcm,bcm11351-pinctrl"
- reg: Base address of the PAD Controller register block and the size
of the block.
For example, the following is the bare minimum node:
pinctrl@35004800 {
compatible = "brcm,bcm11351-pinctrl";
reg = <0x35004800 0x430>;
};
As a pin controller device, in addition to the required properties, this node
should also contain the pin configuration nodes that client devices reference,
if any.
=== Pin Configuration Node ===
Each pin configuration node is a sub-node of the pin controller node and is a
container of an arbitrary number of subnodes, called pin group nodes in this
document.
Please refer to the pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the definition of a
"pin configuration node".
=== Pin Group Node ===
A pin group node specifies the desired pin mux and/or pin configuration for an
arbitrary number of pins. The name of the pin group node is optional and not
used.
A pin group node only affects the properties specified in the node, and has no
effect on any properties that are omitted.
The pin group node accepts a subset of the generic pin config properties. For
details generic pin config properties, please refer to pinctrl-bindings.txt
and <include/linux/pinctrl/pinconfig-generic.h>.
Each pin controlled by this pin controller belong to one of three types:
Standard, I2C, and HDMI. Each type accepts a different set of pin config
properties. A list of pins and their types is provided below.
Required Properties (applicable to all pins):
- pins: Multiple strings. Specifies the name(s) of one or more pins to
be configured by this node.
Optional Properties (for standard pins):
- function: String. Specifies the pin mux selection. Values
must be one of: "alt1", "alt2", "alt3", "alt4"
- input-schmitt-enable: No arguments. Enable schmitt-trigger mode.
- input-schmitt-disable: No arguments. Disable schmitt-trigger mode.
- bias-pull-up: No arguments. Pull up on pin.
- bias-pull-down: No arguments. Pull down on pin.
- bias-disable: No arguments. Disable pin bias.
- slew-rate: Integer. Meaning depends on configured pin mux:
*_SCL or *_SDA:
0: Standard(100kbps)& Fast(400kbps) mode
1: Highspeed (3.4Mbps) mode
IC_DM or IC_DP:
0: normal slew rate
1: fast slew rate
Otherwise:
0: fast slew rate
1: normal slew rate
- input-enable: No arguments. Enable input (does not affect
output.)
- input-disable: No arguments. Disable input (does not affect
output.)
- drive-strength: Integer. Drive strength in mA. Valid values are
2, 4, 6, 8, 10, 12, 14, 16 mA.
Optional Properties (for I2C pins):
- function: String. Specifies the pin mux selection. Values
must be one of: "alt1", "alt2", "alt3", "alt4"
- bias-pull-up: Integer. Pull up strength in Ohm. There are 3
pull-up resistors (1.2k, 1.8k, 2.7k) available
in parallel for I2C pins, so the valid values
are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm.
- bias-disable: No arguments. Disable pin bias.
- slew-rate: Integer. Meaning depends on configured pin mux:
*_SCL or *_SDA:
0: Standard(100kbps)& Fast(400kbps) mode
1: Highspeed (3.4Mbps) mode
IC_DM or IC_DP:
0: normal slew rate
1: fast slew rate
Otherwise:
0: fast slew rate
1: normal slew rate
- input-enable: No arguments. Enable input (does not affect
output.)
- input-disable: No arguments. Disable input (does not affect
output.)
Optional Properties (for HDMI pins):
- function: String. Specifies the pin mux selection. Values
must be one of: "alt1", "alt2", "alt3", "alt4"
- slew-rate: Integer. Controls slew rate.
0: Standard(100kbps)& Fast(400kbps) mode
1: Highspeed (3.4Mbps) mode
- input-enable: No arguments. Enable input (does not affect
output.)
- input-disable: No arguments. Disable input (does not affect
output.)
Example:
// pin controller node
pinctrl@35004800 {
compatible = "brcm,bcm11351-pinctrl";
reg = <0x35004800 0x430>;
// pin configuration node
dev_a_default: dev_a_active {
//group node defining 1 standard pin
grp_1 {
pins = "std_pin1";
function = "alt1";
input-schmitt-enable;
bias-disable;
slew-rate = <1>;
drive-strength = <4>;
};
// group node defining 2 I2C pins
grp_2 {
pins = "i2c_pin1", "i2c_pin2";
function = "alt2";
bias-pull-up = <720>;
input-enable;
};
// group node defining 2 HDMI pins
grp_3 {
pins = "hdmi_pin1", "hdmi_pin2";
function = "alt3";
slew-rate = <1>;
};
// other pin group nodes
...
};
// other pin configuration nodes
...
};
In the example above, "dev_a_active" is a pin configuration node with a number
of sub-nodes. In the pin group node "grp_1", one pin, "std_pin1", is defined in
the "pins" property. Thus, the remaining properties in the "grp_1" node applies
only to this pin, including the following settings:
- setting pinmux to "alt1"
- enabling schmitt-trigger (hystersis) mode
- disabling pin bias
- setting the slew-rate to 1
- setting the drive strength to 4 mA
Note that neither "input-enable" nor "input-disable" was specified - the pinctrl
subsystem will therefore leave this property unchanged from whatever state it
was in before applying these changes.
The "pins" property in the pin group node "grp_2" specifies two pins -
"i2c_pin1" and "i2c_pin2"; the remaining properties in this pin group node,
therefore, applies to both of these pins. The properties include:
- setting pinmux to "alt2"
- setting pull-up resistance to 720 Ohm (ie. enabling 1.2k and 1.8k resistors
in parallel)
- enabling both pins' input
"slew-rate" is not specified in this pin group node, so the slew-rate for these
pins are left as-is.
Finally, "grp_3" defines two HDMI pins. The following properties are applied to
both pins:
- setting pinmux to "alt3"
- setting slew-rate to 1; for HDMI pins, this corresponds to the 3.4 Mbps
Highspeed mode
The input is neither enabled or disabled, and is left untouched.
=== Pin Names and Type ===
The following are valid pin names and their pin types:
"adcsync", Standard
"bat_rm", Standard
"bsc1_scl", I2C
"bsc1_sda", I2C
"bsc2_scl", I2C
"bsc2_sda", I2C
"classgpwr", Standard
"clk_cx8", Standard
"clkout_0", Standard
"clkout_1", Standard
"clkout_2", Standard
"clkout_3", Standard
"clkreq_in_0", Standard
"clkreq_in_1", Standard
"cws_sys_req1", Standard
"cws_sys_req2", Standard
"cws_sys_req3", Standard
"digmic1_clk", Standard
"digmic1_dq", Standard
"digmic2_clk", Standard
"digmic2_dq", Standard
"gpen13", Standard
"gpen14", Standard
"gpen15", Standard
"gpio00", Standard
"gpio01", Standard
"gpio02", Standard
"gpio03", Standard
"gpio04", Standard
"gpio05", Standard
"gpio06", Standard
"gpio07", Standard
"gpio08", Standard
"gpio09", Standard
"gpio10", Standard
"gpio11", Standard
"gpio12", Standard
"gpio13", Standard
"gpio14", Standard
"gps_pablank", Standard
"gps_tmark", Standard
"hdmi_scl", HDMI
"hdmi_sda", HDMI
"ic_dm", Standard
"ic_dp", Standard
"kp_col_ip_0", Standard
"kp_col_ip_1", Standard
"kp_col_ip_2", Standard
"kp_col_ip_3", Standard
"kp_row_op_0", Standard
"kp_row_op_1", Standard
"kp_row_op_2", Standard
"kp_row_op_3", Standard
"lcd_b_0", Standard
"lcd_b_1", Standard
"lcd_b_2", Standard
"lcd_b_3", Standard
"lcd_b_4", Standard
"lcd_b_5", Standard
"lcd_b_6", Standard
"lcd_b_7", Standard
"lcd_g_0", Standard
"lcd_g_1", Standard
"lcd_g_2", Standard
"lcd_g_3", Standard
"lcd_g_4", Standard
"lcd_g_5", Standard
"lcd_g_6", Standard
"lcd_g_7", Standard
"lcd_hsync", Standard
"lcd_oe", Standard
"lcd_pclk", Standard
"lcd_r_0", Standard
"lcd_r_1", Standard
"lcd_r_2", Standard
"lcd_r_3", Standard
"lcd_r_4", Standard
"lcd_r_5", Standard
"lcd_r_6", Standard
"lcd_r_7", Standard
"lcd_vsync", Standard
"mdmgpio0", Standard
"mdmgpio1", Standard
"mdmgpio2", Standard
"mdmgpio3", Standard
"mdmgpio4", Standard
"mdmgpio5", Standard
"mdmgpio6", Standard
"mdmgpio7", Standard
"mdmgpio8", Standard
"mphi_data_0", Standard
"mphi_data_1", Standard
"mphi_data_2", Standard
"mphi_data_3", Standard
"mphi_data_4", Standard
"mphi_data_5", Standard
"mphi_data_6", Standard
"mphi_data_7", Standard
"mphi_data_8", Standard
"mphi_data_9", Standard
"mphi_data_10", Standard
"mphi_data_11", Standard
"mphi_data_12", Standard
"mphi_data_13", Standard
"mphi_data_14", Standard
"mphi_data_15", Standard
"mphi_ha0", Standard
"mphi_hat0", Standard
"mphi_hat1", Standard
"mphi_hce0_n", Standard
"mphi_hce1_n", Standard
"mphi_hrd_n", Standard
"mphi_hwr_n", Standard
"mphi_run0", Standard
"mphi_run1", Standard
"mtx_scan_clk", Standard
"mtx_scan_data", Standard
"nand_ad_0", Standard
"nand_ad_1", Standard
"nand_ad_2", Standard
"nand_ad_3", Standard
"nand_ad_4", Standard
"nand_ad_5", Standard
"nand_ad_6", Standard
"nand_ad_7", Standard
"nand_ale", Standard
"nand_cen_0", Standard
"nand_cen_1", Standard
"nand_cle", Standard
"nand_oen", Standard
"nand_rdy_0", Standard
"nand_rdy_1", Standard
"nand_wen", Standard
"nand_wp", Standard
"pc1", Standard
"pc2", Standard
"pmu_int", Standard
"pmu_scl", I2C
"pmu_sda", I2C
"rfst2g_mtsloten3g", Standard
"rgmii_0_rx_ctl", Standard
"rgmii_0_rxc", Standard
"rgmii_0_rxd_0", Standard
"rgmii_0_rxd_1", Standard
"rgmii_0_rxd_2", Standard
"rgmii_0_rxd_3", Standard
"rgmii_0_tx_ctl", Standard
"rgmii_0_txc", Standard
"rgmii_0_txd_0", Standard
"rgmii_0_txd_1", Standard
"rgmii_0_txd_2", Standard
"rgmii_0_txd_3", Standard
"rgmii_1_rx_ctl", Standard
"rgmii_1_rxc", Standard
"rgmii_1_rxd_0", Standard
"rgmii_1_rxd_1", Standard
"rgmii_1_rxd_2", Standard
"rgmii_1_rxd_3", Standard
"rgmii_1_tx_ctl", Standard
"rgmii_1_txc", Standard
"rgmii_1_txd_0", Standard
"rgmii_1_txd_1", Standard
"rgmii_1_txd_2", Standard
"rgmii_1_txd_3", Standard
"rgmii_gpio_0", Standard
"rgmii_gpio_1", Standard
"rgmii_gpio_2", Standard
"rgmii_gpio_3", Standard
"rtxdata2g_txdata3g1", Standard
"rtxen2g_txdata3g2", Standard
"rxdata3g0", Standard
"rxdata3g1", Standard
"rxdata3g2", Standard
"sdio1_clk", Standard
"sdio1_cmd", Standard
"sdio1_data_0", Standard
"sdio1_data_1", Standard
"sdio1_data_2", Standard
"sdio1_data_3", Standard
"sdio4_clk", Standard
"sdio4_cmd", Standard
"sdio4_data_0", Standard
"sdio4_data_1", Standard
"sdio4_data_2", Standard
"sdio4_data_3", Standard
"sim_clk", Standard
"sim_data", Standard
"sim_det", Standard
"sim_resetn", Standard
"sim2_clk", Standard
"sim2_data", Standard
"sim2_det", Standard
"sim2_resetn", Standard
"sri_c", Standard
"sri_d", Standard
"sri_e", Standard
"ssp_extclk", Standard
"ssp0_clk", Standard
"ssp0_fs", Standard
"ssp0_rxd", Standard
"ssp0_txd", Standard
"ssp2_clk", Standard
"ssp2_fs_0", Standard
"ssp2_fs_1", Standard
"ssp2_fs_2", Standard
"ssp2_fs_3", Standard
"ssp2_rxd_0", Standard
"ssp2_rxd_1", Standard
"ssp2_txd_0", Standard
"ssp2_txd_1", Standard
"ssp3_clk", Standard
"ssp3_fs", Standard
"ssp3_rxd", Standard
"ssp3_txd", Standard
"ssp4_clk", Standard
"ssp4_fs", Standard
"ssp4_rxd", Standard
"ssp4_txd", Standard
"ssp5_clk", Standard
"ssp5_fs", Standard
"ssp5_rxd", Standard
"ssp5_txd", Standard
"ssp6_clk", Standard
"ssp6_fs", Standard
"ssp6_rxd", Standard
"ssp6_txd", Standard
"stat_1", Standard
"stat_2", Standard
"sysclken", Standard
"traceclk", Standard
"tracedt00", Standard
"tracedt01", Standard
"tracedt02", Standard
"tracedt03", Standard
"tracedt04", Standard
"tracedt05", Standard
"tracedt06", Standard
"tracedt07", Standard
"tracedt08", Standard
"tracedt09", Standard
"tracedt10", Standard
"tracedt11", Standard
"tracedt12", Standard
"tracedt13", Standard
"tracedt14", Standard
"tracedt15", Standard
"txdata3g0", Standard
"txpwrind", Standard
"uartb1_ucts", Standard
"uartb1_urts", Standard
"uartb1_urxd", Standard
"uartb1_utxd", Standard
"uartb2_urxd", Standard
"uartb2_utxd", Standard
"uartb3_ucts", Standard
"uartb3_urts", Standard
"uartb3_urxd", Standard
"uartb3_utxd", Standard
"uartb4_ucts", Standard
"uartb4_urts", Standard
"uartb4_urxd", Standard
"uartb4_utxd", Standard
"vc_cam1_scl", I2C
"vc_cam1_sda", I2C
"vc_cam2_scl", I2C
"vc_cam2_sda", I2C
"vc_cam3_scl", I2C
"vc_cam3_sda", I2C

259
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View File

@@ -0,0 +1,259 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm11351-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM281xx pin controller
maintainers:
- Florian Fainelli <florian.fainelli@broadcom.com>
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
allOf:
- $ref: pinctrl.yaml#
properties:
compatible:
const: brcm,bcm11351-pinctrl
reg:
maxItems: 1
patternProperties:
'-pins$':
type: object
additionalProperties: false
patternProperties:
'-grp[0-9]$':
type: object
unevaluatedProperties: false
properties:
pins:
description:
Specifies the name(s) of one or more pins to be configured by
this node.
items:
enum: [ adcsync, bat_rm, bsc1_scl, bsc1_sda, bsc2_scl, bsc2_sda,
classgpwr, clk_cx8, clkout_0, clkout_1, clkout_2,
clkout_3, clkreq_in_0, clkreq_in_1, cws_sys_req1,
cws_sys_req2, cws_sys_req3, digmic1_clk, digmic1_dq,
digmic2_clk, digmic2_dq, gpen13, gpen14, gpen15, gpio00,
gpio01, gpio02, gpio03, gpio04, gpio05, gpio06, gpio07,
gpio08, gpio09, gpio10, gpio11, gpio12, gpio13, gpio14,
gps_pablank, gps_tmark, hdmi_scl, hdmi_sda, ic_dm, ic_dp,
kp_col_ip_0, kp_col_ip_1, kp_col_ip_2, kp_col_ip_3,
kp_row_op_0, kp_row_op_1, kp_row_op_2, kp_row_op_3,
lcd_b_0, lcd_b_1, lcd_b_2, lcd_b_3, lcd_b_4, lcd_b_5,
lcd_b_6, lcd_b_7, lcd_g_0, lcd_g_1, lcd_g_2, lcd_g_3,
lcd_g_4, lcd_g_5, lcd_g_6, lcd_g_7, lcd_hsync, lcd_oe,
lcd_pclk, lcd_r_0, lcd_r_1, lcd_r_2, lcd_r_3, lcd_r_4,
lcd_r_5, lcd_r_6, lcd_r_7, lcd_vsync, mdmgpio0, mdmgpio1,
mdmgpio2, mdmgpio3, mdmgpio4, mdmgpio5, mdmgpio6,
mdmgpio7, mdmgpio8, mphi_data_0, mphi_data_1, mphi_data_2,
mphi_data_3, mphi_data_4, mphi_data_5, mphi_data_6,
mphi_data_7, mphi_data_8, mphi_data_9, mphi_data_10,
mphi_data_11, mphi_data_12, mphi_data_13, mphi_data_14,
mphi_data_15, mphi_ha0, mphi_hat0, mphi_hat1, mphi_hce0_n,
mphi_hce1_n, mphi_hrd_n, mphi_hwr_n, mphi_run0, mphi_run1,
mtx_scan_clk, mtx_scan_data, nand_ad_0, nand_ad_1,
nand_ad_2, nand_ad_3, nand_ad_4, nand_ad_5, nand_ad_6,
nand_ad_7, nand_ale, nand_cen_0, nand_cen_1, nand_cle,
nand_oen, nand_rdy_0, nand_rdy_1, nand_wen, nand_wp, pc1,
pc2, pmu_int, pmu_scl, pmu_sda, rfst2g_mtsloten3g,
rgmii_0_rx_ctl, rgmii_0_rxc, rgmii_0_rxd_0, rgmii_0_rxd_1,
rgmii_0_rxd_2, rgmii_0_rxd_3, rgmii_0_tx_ctl, rgmii_0_txc,
rgmii_0_txd_0, rgmii_0_txd_1, rgmii_0_txd_2,
rgmii_0_txd_3, rgmii_1_rx_ctl, rgmii_1_rxc, rgmii_1_rxd_0,
rgmii_1_rxd_1, rgmii_1_rxd_2, rgmii_1_rxd_3,
rgmii_1_tx_ctl, rgmii_1_txc, rgmii_1_txd_0, rgmii_1_txd_1,
rgmii_1_txd_2, rgmii_1_txd_3, rgmii_gpio_0, rgmii_gpio_1,
rgmii_gpio_2, rgmii_gpio_3, rtxdata2g_txdata3g1,
rtxen2g_txdata3g2, rxdata3g0, rxdata3g1, rxdata3g2,
sdio1_clk, sdio1_cmd, sdio1_data_0, sdio1_data_1,
sdio1_data_2, sdio1_data_3, sdio4_clk, sdio4_cmd,
sdio4_data_0, sdio4_data_1, sdio4_data_2, sdio4_data_3,
sim_clk, sim_data, sim_det, sim_resetn, sim2_clk,
sim2_data, sim2_det, sim2_resetn, sri_c, sri_d, sri_e,
ssp_extclk, ssp0_clk, ssp0_fs, ssp0_rxd, ssp0_txd,
ssp2_clk, ssp2_fs_0, ssp2_fs_1, ssp2_fs_2, ssp2_fs_3,
ssp2_rxd_0, ssp2_rxd_1, ssp2_txd_0, ssp2_txd_1, ssp3_clk,
ssp3_fs, ssp3_rxd, ssp3_txd, ssp4_clk, ssp4_fs, ssp4_rxd,
ssp4_txd, ssp5_clk, ssp5_fs, ssp5_rxd, ssp5_txd, ssp6_clk,
ssp6_fs, ssp6_rxd, ssp6_txd, stat_1, stat_2, sysclken,
traceclk, tracedt00, tracedt01, tracedt02, tracedt03,
tracedt04, tracedt05, tracedt06, tracedt07, tracedt08
tracedt09, tracedt10, tracedt11, tracedt12, tracedt13
tracedt14, tracedt15, txdata3g0, txpwrind, uartb1_ucts,
uartb1_urts, uartb1_urxd, uartb1_utxd, uartb2_urxd,
uartb2_utxd, uartb3_ucts, uartb3_urts, uartb3_urxd,
uartb3_utxd, uartb4_ucts, uartb4_urts, uartb4_urxd,
uartb4_utxd, vc_cam1_scl, vc_cam1_sda, vc_cam2_scl,
vc_cam2_sda, vc_cam3_scl, vc_cam3_sda ]
function:
description:
Specifies the pin mux selection.
enum: [ alt1, alt2, alt3, alt4 ]
slew-rate:
description: |
Meaning depends on configured pin mux:
*_scl or *_sda:
0: Standard (100 kbps) & Fast (400 kbps) mode
1: Highspeed (3.4 Mbps) mode
ic_dm or ic_dp:
0: normal slew rate
1: fast slew rate
Otherwise:
0: fast slew rate
1: normal slew rate
bias-disable: true
input-disable: true
input-enable: true
required:
- pins
allOf:
- $ref: pincfg-node.yaml#
# Optional properties for standard pins
- if:
properties:
pins:
contains:
enum: [ adcsync, bat_rm, classgpwr, clk_cx8, clkout_0,
clkout_1, clkout_2, clkout_3, clkreq_in_0,
clkreq_in_1, cws_sys_req1, cws_sys_req2,
cws_sys_req3, digmic1_clk, digmic1_dq, digmic2_clk,
digmic2_dq, gpen13, gpen14, gpen15, gpio00, gpio01,
gpio02, gpio03, gpio04, gpio05, gpio06, gpio07,
gpio08, gpio09, gpio10, gpio11, gpio12, gpio13,
gpio14, gps_pablank, gps_tmark, ic_dm, ic_dp,
kp_col_ip_0, kp_col_ip_1, kp_col_ip_2, kp_col_ip_3,
kp_row_op_0, kp_row_op_1, kp_row_op_2, kp_row_op_3,
lcd_b_0, lcd_b_1, lcd_b_2, lcd_b_3, lcd_b_4, lcd_b_5,
lcd_b_6, lcd_b_7, lcd_g_0, lcd_g_1, lcd_g_2, lcd_g_3,
lcd_g_4, lcd_g_5, lcd_g_6, lcd_g_7, lcd_hsync,
lcd_oe, lcd_pclk, lcd_r_0, lcd_r_1, lcd_r_2,
lcd_r_3, lcd_r_4, lcd_r_5, lcd_r_6, lcd_r_7,
lcd_vsync, mdmgpio0, mdmgpio1, mdmgpio2, mdmgpio3,
mdmgpio4, mdmgpio5, mdmgpio6, mdmgpio7, mdmgpio8,
mphi_data_0, mphi_data_1, mphi_data_2, mphi_data_3,
mphi_data_4, mphi_data_5, mphi_data_6, mphi_data_7,
mphi_data_8, mphi_data_9, mphi_data_10,
mphi_data_11, mphi_data_12, mphi_data_13,
mphi_data_14, mphi_data_15, mphi_ha0, mphi_hat0,
mphi_hat1, mphi_hce0_n, mphi_hce1_n, mphi_hrd_n,
mphi_hwr_n, mphi_run0, mphi_run1, mtx_scan_clk,
mtx_scan_data, nand_ad_0, nand_ad_1, nand_ad_2,
nand_ad_3, nand_ad_4, nand_ad_5, nand_ad_6,
nand_ad_7, nand_ale, nand_cen_0, nand_cen_1,
nand_cle, nand_oen, nand_rdy_0, nand_rdy_1,
nand_wen, nand_wp, pc1, pc2, pmu_int,
rfst2g_mtsloten3g, rgmii_0_rx_ctl, rgmii_0_rxc,
rgmii_0_rxd_0, rgmii_0_rxd_1, rgmii_0_rxd_2,
rgmii_0_rxd_3, rgmii_0_tx_ctl, rgmii_0_txc,
rgmii_0_txd_0, rgmii_0_txd_1, rgmii_0_txd_2,
rgmii_0_txd_3, rgmii_1_rx_ctl, rgmii_1_rxc,
rgmii_1_rxd_0, rgmii_1_rxd_1, rgmii_1_rxd_2,
rgmii_1_rxd_3, rgmii_1_tx_ctl, rgmii_1_txc,
rgmii_1_txd_0, rgmii_1_txd_1, rgmii_1_txd_2,
rgmii_1_txd_3, rgmii_gpio_0, rgmii_gpio_1,
rgmii_gpio_2, rgmii_gpio_3, rtxdata2g_txdata3g1,
rtxen2g_txdata3g2, rxdata3g0, rxdata3g1, rxdata3g2,
sdio1_clk, sdio1_cmd, sdio1_data_0, sdio1_data_1,
sdio1_data_2, sdio1_data_3, sdio4_clk, sdio4_cmd,
sdio4_data_0, sdio4_data_1, sdio4_data_2,
sdio4_data_3, sim_clk, sim_data, sim_det,
sim_resetn, sim2_clk, sim2_data, sim2_det,
sim2_resetn, sri_c, sri_d, sri_e, ssp_extclk,
ssp0_clk, ssp0_fs, ssp0_rxd, ssp0_txd, ssp2_clk,
ssp2_fs_0, ssp2_fs_1, ssp2_fs_2, ssp2_fs_3,
ssp2_rxd_0, ssp2_rxd_1, ssp2_txd_0, ssp2_txd_1,
ssp3_clk, ssp3_fs, ssp3_rxd, ssp3_txd, ssp4_clk,
ssp4_fs, ssp4_rxd, ssp4_txd, ssp5_clk, ssp5_fs,
ssp5_rxd, ssp5_txd, ssp6_clk, ssp6_fs, ssp6_rxd,
ssp6_txd, stat_1, stat_2, sysclken, traceclk,
tracedt00, tracedt01, tracedt02, tracedt03,
tracedt04, tracedt05, tracedt06, tracedt07,
tracedt08, tracedt09, tracedt10, tracedt11,
tracedt12, tracedt13, tracedt14, tracedt15,
txdata3g0, txpwrind, uartb1_ucts, uartb1_urts,
uartb1_urxd, uartb1_utxd, uartb2_urxd, uartb2_utxd,
uartb3_ucts, uartb3_urts, uartb3_urxd, uartb3_utxd,
uartb4_ucts, uartb4_urts, uartb4_urxd, uartb4_utxd ]
then:
properties:
drive-strength:
enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ]
bias-disable: true
bias-pull-up: true
bias-pull-down: true
input-schmitt-enable: true
input-schmitt-disable: true
# Optional properties for I2C pins
- if:
properties:
pins:
contains:
enum: [ bsc1_scl, bsc1_sda, bsc2_scl, bsc2_sda, pmu_scl,
pmu_sda, vc_cam1_scl, vc_cam1_sda, vc_cam2_scl,
vc_cam2_sda, vc_cam3_scl, vc_cam3_sda ]
then:
properties:
bias-pull-up:
description:
There are 3 pull-up resistors (1.2k, 1.8k, 2.7k) available
in parallel for I2C pins.
enum: [ 568, 720, 831, 1080, 1200, 1800, 2700 ]
bias-disable: true
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
pinctrl@35004800 {
compatible = "brcm,bcm11351-pinctrl";
reg = <0x35004800 0x430>;
dev-a-active-pins {
/* group node defining 1 standard pin */
std-grp0 {
pins = "gpio00";
function = "alt1";
input-schmitt-enable;
bias-disable;
slew-rate = <1>;
drive-strength = <4>;
};
/* group node defining 2 I2C pins */
i2c-grp0 {
pins = "bsc1_scl", "bsc1_sda";
function = "alt2";
bias-pull-up = <720>;
input-enable;
};
/* group node defining 2 HDMI pins */
hdmi-grp0 {
pins = "hdmi_scl", "hdmi_sda";
function = "alt3";
slew-rate = <1>;
};
};
};
...

4
Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml
View File

@@ -51,6 +51,10 @@ properties:
description:
Optional power supply.
reset-gpios:
description: GPIO connected to the XRES pin
maxItems: 1
patternProperties:
'-pins$':
type: object

4
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
View File

@@ -135,7 +135,6 @@ additionalProperties:
- $ref: pinmux-node.yaml#
properties:
phandle: true
function: true
groups: true
pins: true
@@ -147,8 +146,6 @@ additionalProperties:
additionalProperties: false
- type: object
properties:
phandle: true
additionalProperties:
type: object
allOf:
@@ -156,7 +153,6 @@ additionalProperties:
- $ref: pinmux-node.yaml#
properties:
phandle: true
function: true
groups: true
pins: true

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
View File

@@ -22,8 +22,6 @@ properties:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
properties:
phandle: true
# pin groups
additionalProperties:

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
View File

@@ -32,8 +32,6 @@ properties:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
properties:
phandle: true
# pin groups
additionalProperties:

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
View File

@@ -23,8 +23,6 @@ properties:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
properties:
phandle: true
# pin groups
additionalProperties:

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
View File

@@ -24,8 +24,6 @@ properties:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
properties:
phandle: true
# pin groups
additionalProperties:

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
View File

@@ -22,8 +22,6 @@ properties:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
properties:
phandle: true
# pin groups
additionalProperties:

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