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https://github.com/Dasharo/linux.git
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Merge tag 'powerpc-6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc updates from Michael Ellerman: - Remove support for 40x CPUs & platforms - Add support to the 64-bit BPF JIT for cpu v4 instructions - Fix PCI hotplug driver crash on powernv - Fix doorbell emulation for KVM on PAPR guests (nestedv2) - Fix KVM nested guest handling of some less used SPRs - Online NUMA nodes with no CPU/memory if they have a PCI device attached - Reduce memory overhead of enabling kfence on 64-bit Radix MMU kernels - Reimplement the iommu table_group_ops for pseries for VFIO SPAPR TCE Thanks to: Anjali K, Artem Savkov, Athira Rajeev, Breno Leitao, Brian King, Celeste Liu, Christophe Leroy, Esben Haabendal, Gaurav Batra, Gautam Menghani, Haren Myneni, Hari Bathini, Jeff Johnson, Krishna Kumar, Krzysztof Kozlowski, Nathan Lynch, Nicholas Piggin, Nick Bowler, Nilay Shroff, Rob Herring (Arm), Shawn Anastasio, Shivaprasad G Bhat, Sourabh Jain, Srikar Dronamraju, Timothy Pearson, Uwe Kleine-König, and Vaibhav Jain. * tag 'powerpc-6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (57 commits) Documentation/powerpc: Mention 40x is removed powerpc: Remove 40x leftovers macintosh/therm_windtunnel: fix module unload. powerpc: Check only single values are passed to CPU/MMU feature checks powerpc/xmon: Fix disassembly CPU feature checks powerpc: Drop clang workaround for builtin constant checks powerpc64/bpf: jit support for signed division and modulo powerpc64/bpf: jit support for sign extended mov powerpc64/bpf: jit support for sign extended load powerpc64/bpf: jit support for unconditional byte swap powerpc64/bpf: jit support for 32bit offset jmp instruction powerpc/pci: Hotplug driver bridge support pci/hotplug/pnv_php: Fix hotplug driver crash on Powernv powerpc/configs: Update defconfig with now user-visible CONFIG_FSL_IFC powerpc: add missing MODULE_DESCRIPTION() macros macintosh/mac_hid: add MODULE_DESCRIPTION() KVM: PPC: add missing MODULE_DESCRIPTION() macros powerpc/kexec: Use of_property_read_reg() powerpc/64s/radix/kfence: map __kfence_pool at page granularity powerpc/pseries/iommu: Define spapr_tce_table_group_ops only with CONFIG_IOMMU_API ...
This commit is contained in:
Linus Torvalds
@@ -128,24 +128,6 @@ IBM BookE
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- All 32 bit::
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+--------------+
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| 401 |
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+--------------+
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||||
|
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||||
|
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||||
v
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+--------------+
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| 403 |
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+--------------+
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|
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|
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v
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+--------------+
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| 405 |
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+--------------+
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||||
|
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|
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v
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+--------------+
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| 440 |
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+--------------+
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||||
|
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@@ -91,6 +91,7 @@ PPC_FEATURE_HAS_MMU
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PPC_FEATURE_HAS_4xxMAC
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The processor is 40x or 44x family.
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Unused in the kernel since 732b32daef80 ("powerpc: Remove core support for 40x")
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PPC_FEATURE_UNIFIED_CACHE
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The processor has a unified L1 cache for instructions and data, as
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@@ -546,7 +546,9 @@ table information.
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+--------+-------+----+--------+----------------------------------+
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| 0x1052 | 0x08 | RW | T | CTRL |
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+--------+-------+----+--------+----------------------------------+
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| 0x1053-| | | | Reserved |
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| 0x1053 | 0x08 | RW | T | DPDES |
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+--------+-------+----+--------+----------------------------------+
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| 0x1054-| | | | Reserved |
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| 0x1FFF | | | | |
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+--------+-------+----+--------+----------------------------------+
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| 0x2000 | 0x04 | RW | T | CR |
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@@ -2439,8 +2439,11 @@ registers, find a list below:
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PPC KVM_REG_PPC_PSSCR 64
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PPC KVM_REG_PPC_DEC_EXPIRY 64
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PPC KVM_REG_PPC_PTCR 64
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PPC KVM_REG_PPC_HASHKEYR 64
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PPC KVM_REG_PPC_HASHPKEYR 64
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PPC KVM_REG_PPC_DAWR1 64
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PPC KVM_REG_PPC_DAWRX1 64
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PPC KVM_REG_PPC_DEXCR 64
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PPC KVM_REG_PPC_TM_GPR0 64
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...
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PPC KVM_REG_PPC_TM_GPR31 64
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@@ -12924,7 +12924,6 @@ F: arch/powerpc/platforms/52xx/
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LINUX FOR POWERPC EMBEDDED PPC4XX
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L: linuxppc-dev@lists.ozlabs.org
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S: Orphan
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F: arch/powerpc/platforms/40x/
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F: arch/powerpc/platforms/44x/
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LINUX FOR POWERPC EMBEDDED PPC85XX
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@@ -149,7 +149,7 @@ config PPC
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select ARCH_HAS_PTE_SPECIAL
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select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE && PPC_BOOK3S_64
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select ARCH_HAS_SET_MEMORY
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select ARCH_HAS_STRICT_KERNEL_RWX if (PPC_BOOK3S || PPC_8xx || 40x) && !HIBERNATION
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select ARCH_HAS_STRICT_KERNEL_RWX if (PPC_BOOK3S || PPC_8xx) && !HIBERNATION
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select ARCH_HAS_STRICT_KERNEL_RWX if PPC_85xx && !HIBERNATION && !RANDOMIZE_BASE
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select ARCH_HAS_STRICT_MODULE_RWX if ARCH_HAS_STRICT_KERNEL_RWX
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select ARCH_HAS_SYSCALL_WRAPPER if !SPU_BASE && !COMPAT
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@@ -167,7 +167,7 @@ config PPC
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select ARCH_SPLIT_ARG64 if PPC32
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select ARCH_STACKWALK
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select ARCH_SUPPORTS_ATOMIC_RMW
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select ARCH_SUPPORTS_DEBUG_PAGEALLOC if PPC_BOOK3S || PPC_8xx || 40x
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select ARCH_SUPPORTS_DEBUG_PAGEALLOC if PPC_BOOK3S || PPC_8xx
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select ARCH_USE_BUILTIN_BSWAP
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select ARCH_USE_CMPXCHG_LOCKREF if PPC64
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select ARCH_USE_MEMTEST
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@@ -389,7 +389,7 @@ config ARCH_SUSPEND_POSSIBLE
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def_bool y
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depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
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(PPC_85xx && !PPC_E500MC) || PPC_86xx || PPC_PSERIES \
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|| 44x || 40x
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|| 44x
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config ARCH_SUSPEND_NONZERO_CPU
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def_bool y
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@@ -443,7 +443,7 @@ config ARCH_SUPPORTS_UPROBES
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config PPC_ADV_DEBUG_REGS
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bool
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depends on 40x || BOOKE
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depends on BOOKE
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default y
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config PPC_ADV_DEBUG_IACS
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@@ -490,7 +490,7 @@ source "kernel/Kconfig.hz"
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config MATH_EMULATION
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bool "Math emulation"
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depends on 4xx || PPC_8xx || PPC_MPC832x || BOOKE || PPC_MICROWATT
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depends on 44x || PPC_8xx || PPC_MPC832x || BOOKE || PPC_MICROWATT
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select PPC_FPU_REGS
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help
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Some PowerPC chips designed for embedded applications do not have
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@@ -1077,7 +1077,7 @@ config GENERIC_ISA_DMA
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config PPC_INDIRECT_PCI
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bool
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depends on PCI
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default y if 40x || 44x
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default y if 44x
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config SBUS
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bool
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@@ -1102,15 +1102,12 @@ config FSL_PMC
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config PPC4xx_CPM
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bool
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default y
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depends on SUSPEND && (44x || 40x)
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depends on SUSPEND && 44x
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help
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PPC4xx Clock Power Management (CPM) support (suspend/resume).
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It also enables support for two different idle states (idle-wait
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and idle-doze).
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config 4xx_SOC
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bool
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config FSL_LBC
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bool "Freescale Local Bus support"
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help
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@@ -244,14 +244,6 @@ config PPC_EARLY_DEBUG_44x
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inbuilt serial port. If you enable this, ensure you set
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PPC_EARLY_DEBUG_44x_PHYSLOW below to suit your target board.
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config PPC_EARLY_DEBUG_40x
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bool "Early serial debugging for IBM/AMCC 40x CPUs"
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depends on 40x
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help
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Select this to enable early debugging for IBM 40x chips via the
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inbuilt serial port. This works on chips with a 16550 compatible
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UART.
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config PPC_EARLY_DEBUG_CPM
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bool "Early serial debugging for Freescale CPM-based serial ports"
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depends on SERIAL_CPM=y
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@@ -356,11 +348,6 @@ config PPC_EARLY_DEBUG_44x_PHYSHIGH
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depends on PPC_EARLY_DEBUG_44x
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default "0x1"
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config PPC_EARLY_DEBUG_40x_PHYSADDR
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hex "Early debug UART physical address"
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depends on PPC_EARLY_DEBUG_40x
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default "0xef600300"
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config PPC_EARLY_DEBUG_CPM_ADDR
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hex "CPM UART early debug transmit descriptor address"
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depends on PPC_EARLY_DEBUG_CPM
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@@ -301,11 +301,6 @@ ppc32_allmodconfig:
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$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/book3s_32.config \
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-f $(srctree)/Makefile allmodconfig
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generated_configs += ppc40x_allmodconfig
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ppc40x_allmodconfig:
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$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/40x.config \
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-f $(srctree)/Makefile allmodconfig
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generated_configs += ppc44x_allmodconfig
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ppc44x_allmodconfig:
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$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/44x.config \
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@@ -253,7 +253,6 @@ void ibm4xx_denali_fixup_memsize(void)
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dt_fixup_memory(0, memsize);
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}
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#define SPRN_DBCR0_40X 0x3F2
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#define SPRN_DBCR0_44X 0x134
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#define DBCR0_RST_SYSTEM 0x30000000
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@@ -270,18 +269,6 @@ void ibm44x_dbcr_reset(void)
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}
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void ibm40x_dbcr_reset(void)
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{
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unsigned long tmp;
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asm volatile (
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"mfspr %0,%1\n"
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"oris %0,%0,%2@h\n"
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"mtspr %1,%0"
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: "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM)
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);
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}
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#define EMAC_RESET 0x20000000
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void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
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{
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@@ -544,256 +531,3 @@ void ibm440spe_fixup_clocks(unsigned int sys_clk,
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eplike_fixup_uart_clk(1, "/plb/opb/serial@f0000300", ser_clk, plb_clk);
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eplike_fixup_uart_clk(2, "/plb/opb/serial@f0000600", ser_clk, plb_clk);
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}
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void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
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{
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u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
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u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
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u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
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u32 psr = mfdcr(DCRN_405_CPC0_PSR);
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u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
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u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv;
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fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
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fbdv = (pllmr & 0x1e000000) >> 25;
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if (fbdv == 0)
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fbdv = 16;
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cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
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opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
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ppdv = ((pllmr & 0x00006000) >> 13) + 1; /* PLB:PCI */
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epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
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udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
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/* check for 405GPr */
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if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
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fwdvb = 8 - (pllmr & 0x00000007);
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if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
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if (psr & 0x00000020) /* New mode enable */
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m = fwdvb * 2 * ppdv;
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else
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m = fwdvb * cbdv * ppdv;
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else if (psr & 0x00000020) /* New mode enable */
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if (psr & 0x00000800) /* PerClk synch mode */
|
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m = fwdvb * 2 * epdv;
|
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else
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m = fbdv * fwdv;
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else if (epdv == fbdv)
|
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m = fbdv * cbdv * epdv;
|
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else
|
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m = fbdv * fwdvb * cbdv;
|
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|
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cpu = sys_clk * m / fwdv;
|
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plb = sys_clk * m / (fwdvb * cbdv);
|
||||
} else {
|
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m = fwdv * fbdv * cbdv;
|
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cpu = sys_clk * m / fwdv;
|
||||
plb = cpu / cbdv;
|
||||
}
|
||||
opb = plb / opdv;
|
||||
ebc = plb / epdv;
|
||||
|
||||
if (cpc0_cr0 & 0x80)
|
||||
/* uart0 uses the external clock */
|
||||
uart0 = ser_clk;
|
||||
else
|
||||
uart0 = cpu / udiv;
|
||||
|
||||
if (cpc0_cr0 & 0x40)
|
||||
/* uart1 uses the external clock */
|
||||
uart1 = ser_clk;
|
||||
else
|
||||
uart1 = cpu / udiv;
|
||||
|
||||
/* setup the timebase clock to tick at the cpu frequency */
|
||||
cpc0_cr1 = cpc0_cr1 & ~0x00800000;
|
||||
mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);
|
||||
tb = cpu;
|
||||
|
||||
dt_fixup_cpu_clocks(cpu, tb, 0);
|
||||
dt_fixup_clock("/plb", plb);
|
||||
dt_fixup_clock("/plb/opb", opb);
|
||||
dt_fixup_clock("/plb/ebc", ebc);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
|
||||
}
|
||||
|
||||
|
||||
void ibm405ep_fixup_clocks(unsigned int sys_clk)
|
||||
{
|
||||
u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0);
|
||||
u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1);
|
||||
u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR);
|
||||
u32 cpu, plb, opb, ebc, uart0, uart1;
|
||||
u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv;
|
||||
u32 pllmr0_ccdv, tb, m;
|
||||
|
||||
fwdva = 8 - ((pllmr1 & 0x00070000) >> 16);
|
||||
fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12);
|
||||
fbdv = (pllmr1 & 0x00f00000) >> 20;
|
||||
if (fbdv == 0)
|
||||
fbdv = 16;
|
||||
|
||||
cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */
|
||||
epdv = ((pllmr0 & 0x00000300) >> 8) + 2; /* PLB:EBC */
|
||||
opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */
|
||||
|
||||
m = fbdv * fwdvb;
|
||||
|
||||
pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1;
|
||||
if (pllmr1 & 0x80000000)
|
||||
cpu = sys_clk * m / (fwdva * pllmr0_ccdv);
|
||||
else
|
||||
cpu = sys_clk / pllmr0_ccdv;
|
||||
|
||||
plb = cpu / cbdv;
|
||||
opb = plb / opdv;
|
||||
ebc = plb / epdv;
|
||||
tb = cpu;
|
||||
uart0 = cpu / (cpc0_ucr & 0x0000007f);
|
||||
uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8);
|
||||
|
||||
dt_fixup_cpu_clocks(cpu, tb, 0);
|
||||
dt_fixup_clock("/plb", plb);
|
||||
dt_fixup_clock("/plb/opb", opb);
|
||||
dt_fixup_clock("/plb/ebc", ebc);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
|
||||
}
|
||||
|
||||
static u8 ibm405ex_fwdv_multi_bits[] = {
|
||||
/* values for: 1 - 16 */
|
||||
0x01, 0x02, 0x0e, 0x09, 0x04, 0x0b, 0x10, 0x0d, 0x0c, 0x05,
|
||||
0x06, 0x0f, 0x0a, 0x07, 0x08, 0x03
|
||||
};
|
||||
|
||||
u32 ibm405ex_get_fwdva(unsigned long cpr_fwdv)
|
||||
{
|
||||
u32 index;
|
||||
|
||||
for (index = 0; index < ARRAY_SIZE(ibm405ex_fwdv_multi_bits); index++)
|
||||
if (cpr_fwdv == (u32)ibm405ex_fwdv_multi_bits[index])
|
||||
return index + 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u8 ibm405ex_fbdv_multi_bits[] = {
|
||||
/* values for: 1 - 100 */
|
||||
0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4,
|
||||
0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb,
|
||||
0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96,
|
||||
0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde,
|
||||
0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb,
|
||||
0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91,
|
||||
0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b,
|
||||
0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95,
|
||||
0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4,
|
||||
0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc,
|
||||
/* values for: 101 - 200 */
|
||||
0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
|
||||
0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
|
||||
0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,
|
||||
0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
|
||||
0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
|
||||
0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
|
||||
0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6,
|
||||
0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9,
|
||||
0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e,
|
||||
0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf,
|
||||
/* values for: 201 - 255 */
|
||||
0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae,
|
||||
0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2,
|
||||
0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2,
|
||||
0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98,
|
||||
0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81,
|
||||
0x03, 0x87, 0x0f, 0x9f, 0x3f /* END */
|
||||
};
|
||||
|
||||
u32 ibm405ex_get_fbdv(unsigned long cpr_fbdv)
|
||||
{
|
||||
u32 index;
|
||||
|
||||
for (index = 0; index < ARRAY_SIZE(ibm405ex_fbdv_multi_bits); index++)
|
||||
if (cpr_fbdv == (u32)ibm405ex_fbdv_multi_bits[index])
|
||||
return index + 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk)
|
||||
{
|
||||
/* PLL config */
|
||||
u32 pllc = CPR0_READ(DCRN_CPR0_PLLC);
|
||||
u32 plld = CPR0_READ(DCRN_CPR0_PLLD);
|
||||
u32 cpud = CPR0_READ(DCRN_CPR0_PRIMAD);
|
||||
u32 plbd = CPR0_READ(DCRN_CPR0_PRIMBD);
|
||||
u32 opbd = CPR0_READ(DCRN_CPR0_OPBD);
|
||||
u32 perd = CPR0_READ(DCRN_CPR0_PERD);
|
||||
|
||||
/* Dividers */
|
||||
u32 fbdv = ibm405ex_get_fbdv(__fix_zero((plld >> 24) & 0xff, 1));
|
||||
|
||||
u32 fwdva = ibm405ex_get_fwdva(__fix_zero((plld >> 16) & 0x0f, 1));
|
||||
|
||||
u32 cpudv0 = __fix_zero((cpud >> 24) & 7, 8);
|
||||
|
||||
/* PLBDV0 is hardwared to 010. */
|
||||
u32 plbdv0 = 2;
|
||||
u32 plb2xdv0 = __fix_zero((plbd >> 16) & 7, 8);
|
||||
|
||||
u32 opbdv0 = __fix_zero((opbd >> 24) & 3, 4);
|
||||
|
||||
u32 perdv0 = __fix_zero((perd >> 24) & 3, 4);
|
||||
|
||||
/* Resulting clocks */
|
||||
u32 cpu, plb, opb, ebc, vco, tb, uart0, uart1;
|
||||
|
||||
/* PLL's VCO is the source for primary forward ? */
|
||||
if (pllc & 0x40000000) {
|
||||
u32 m;
|
||||
|
||||
/* Feedback path */
|
||||
switch ((pllc >> 24) & 7) {
|
||||
case 0:
|
||||
/* PLLOUTx */
|
||||
m = fbdv;
|
||||
break;
|
||||
case 1:
|
||||
/* CPU */
|
||||
m = fbdv * fwdva * cpudv0;
|
||||
break;
|
||||
case 5:
|
||||
/* PERClk */
|
||||
m = fbdv * fwdva * plb2xdv0 * plbdv0 * opbdv0 * perdv0;
|
||||
break;
|
||||
default:
|
||||
printf("WARNING ! Invalid PLL feedback source !\n");
|
||||
goto bypass;
|
||||
}
|
||||
|
||||
vco = (unsigned int)(sys_clk * m);
|
||||
} else {
|
||||
bypass:
|
||||
/* Bypass system PLL */
|
||||
vco = 0;
|
||||
}
|
||||
|
||||
/* CPU = VCO / ( FWDVA x CPUDV0) */
|
||||
cpu = vco / (fwdva * cpudv0);
|
||||
/* PLB = VCO / ( FWDVA x PLB2XDV0 x PLBDV0) */
|
||||
plb = vco / (fwdva * plb2xdv0 * plbdv0);
|
||||
/* OPB = PLB / OPBDV0 */
|
||||
opb = plb / opbdv0;
|
||||
/* EBC = OPB / PERDV0 */
|
||||
ebc = opb / perdv0;
|
||||
|
||||
tb = cpu;
|
||||
uart0 = uart1 = uart_clk;
|
||||
|
||||
dt_fixup_cpu_clocks(cpu, tb, 0);
|
||||
dt_fixup_clock("/plb", plb);
|
||||
dt_fixup_clock("/plb/opb", opb);
|
||||
dt_fixup_clock("/plb/opb/ebc", ebc);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600200", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600300", uart1);
|
||||
}
|
||||
|
||||
@@ -12,13 +12,9 @@ void ibm4xx_sdram_fixup_memsize(void);
|
||||
void ibm440spe_fixup_memsize(void);
|
||||
void ibm4xx_denali_fixup_memsize(void);
|
||||
void ibm44x_dbcr_reset(void);
|
||||
void ibm40x_dbcr_reset(void);
|
||||
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1);
|
||||
void ibm4xx_fixup_ebc_ranges(const char *ebc);
|
||||
|
||||
void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
|
||||
void ibm405ep_fixup_clocks(unsigned int sys_clk);
|
||||
void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk);
|
||||
void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
|
||||
void ibm440ep_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
|
||||
unsigned int tmr_clk);
|
||||
|
||||
@@ -54,10 +54,8 @@ endif
|
||||
|
||||
$(obj)/4xx.o: BOOTTARGETFLAGS += -mcpu=405
|
||||
$(obj)/ebony.o: BOOTTARGETFLAGS += -mcpu=440
|
||||
$(obj)/cuboot-hotfoot.o: BOOTTARGETFLAGS += -mcpu=405
|
||||
$(obj)/cuboot-taishan.o: BOOTTARGETFLAGS += -mcpu=440
|
||||
$(obj)/cuboot-katmai.o: BOOTTARGETFLAGS += -mcpu=440
|
||||
$(obj)/cuboot-acadia.o: BOOTTARGETFLAGS += -mcpu=405
|
||||
$(obj)/treeboot-iss4xx.o: BOOTTARGETFLAGS += -mcpu=405
|
||||
$(obj)/treeboot-currituck.o: BOOTTARGETFLAGS += -mcpu=405
|
||||
$(obj)/treeboot-akebono.o: BOOTTARGETFLAGS += -mcpu=405
|
||||
@@ -146,7 +144,6 @@ src-wlib-$(CONFIG_PPC_POWERNV) += opal-calls.S opal.c
|
||||
ifndef CONFIG_PPC64_BOOT_WRAPPER
|
||||
src-wlib-y += crtsavres.S
|
||||
endif
|
||||
src-wlib-$(CONFIG_40x) += 4xx.c planetcore.c
|
||||
src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
|
||||
src-wlib-$(CONFIG_PPC_8xx) += mpc8xx.c planetcore.c fsl-soc.c
|
||||
src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
|
||||
@@ -154,9 +151,6 @@ src-wlib-$(CONFIG_EMBEDDED6xx) += ugecon.c fsl-soc.c
|
||||
src-wlib-$(CONFIG_CPM) += cpm-serial.c
|
||||
|
||||
src-plat-y := of.c epapr.c
|
||||
src-plat-$(CONFIG_40x) += fixed-head.S cuboot-hotfoot.c \
|
||||
cuboot-acadia.c \
|
||||
cuboot-kilauea.c simpleboot.c
|
||||
src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
|
||||
cuboot-bamboo.c cuboot-sam440ep.c \
|
||||
cuboot-sequoia.c cuboot-rainier.c \
|
||||
@@ -300,11 +294,6 @@ image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
|
||||
# Boards with newish u-boot firmware can use the uImage target above
|
||||
#
|
||||
|
||||
# Board ports in arch/powerpc/platform/40x/Kconfig
|
||||
image-$(CONFIG_HOTFOOT) += cuImage.hotfoot
|
||||
image-$(CONFIG_ACADIA) += cuImage.acadia
|
||||
image-$(CONFIG_OBS600) += uImage.obs600
|
||||
|
||||
# Board ports in arch/powerpc/platform/44x/Kconfig
|
||||
image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
|
||||
image-$(CONFIG_BAMBOO) += treeImage.bamboo cuImage.bamboo
|
||||
|
||||
@@ -1,171 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Old U-boot compatibility for Acadia
|
||||
*
|
||||
* Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
*
|
||||
* Copyright 2008 IBM Corporation
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "io.h"
|
||||
#include "dcr.h"
|
||||
#include "stdio.h"
|
||||
#include "4xx.h"
|
||||
#include "44x.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
|
||||
|
||||
#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
|
||||
|
||||
#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
|
||||
#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
|
||||
#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
|
||||
|
||||
#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
|
||||
#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
|
||||
#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
|
||||
#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
|
||||
|
||||
#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
|
||||
#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
|
||||
#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
|
||||
#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
|
||||
|
||||
static void get_clocks(void)
|
||||
{
|
||||
unsigned long sysclk, cpr_plld, cpr_pllc, cpr_primad, plloutb, i;
|
||||
unsigned long pllFwdDiv, pllFwdDivB, pllFbkDiv, pllPlbDiv, pllExtBusDiv;
|
||||
unsigned long pllOpbDiv, freqEBC, freqUART, freqOPB;
|
||||
unsigned long div; /* total divisor udiv * bdiv */
|
||||
unsigned long umin; /* minimum udiv */
|
||||
unsigned short diff; /* smallest diff */
|
||||
unsigned long udiv; /* best udiv */
|
||||
unsigned short idiff; /* current diff */
|
||||
unsigned short ibdiv; /* current bdiv */
|
||||
unsigned long est; /* current estimate */
|
||||
unsigned long baud;
|
||||
void *np;
|
||||
|
||||
/* read the sysclk value from the CPLD */
|
||||
sysclk = (in_8((unsigned char *)0x80000000) == 0xc) ? 66666666 : 33333000;
|
||||
|
||||
/*
|
||||
* Read PLL Mode registers
|
||||
*/
|
||||
cpr_plld = CPR0_READ(DCRN_CPR0_PLLD);
|
||||
cpr_pllc = CPR0_READ(DCRN_CPR0_PLLC);
|
||||
|
||||
/*
|
||||
* Determine forward divider A
|
||||
*/
|
||||
pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
|
||||
|
||||
/*
|
||||
* Determine forward divider B
|
||||
*/
|
||||
pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
|
||||
if (pllFwdDivB == 0)
|
||||
pllFwdDivB = 8;
|
||||
|
||||
/*
|
||||
* Determine FBK_DIV.
|
||||
*/
|
||||
pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
|
||||
if (pllFbkDiv == 0)
|
||||
pllFbkDiv = 256;
|
||||
|
||||
/*
|
||||
* Read CPR_PRIMAD register
|
||||
*/
|
||||
cpr_primad = CPR0_READ(DCRN_CPR0_PRIMAD);
|
||||
|
||||
/*
|
||||
* Determine PLB_DIV.
|
||||
*/
|
||||
pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
|
||||
if (pllPlbDiv == 0)
|
||||
pllPlbDiv = 16;
|
||||
|
||||
/*
|
||||
* Determine EXTBUS_DIV.
|
||||
*/
|
||||
pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
|
||||
if (pllExtBusDiv == 0)
|
||||
pllExtBusDiv = 16;
|
||||
|
||||
/*
|
||||
* Determine OPB_DIV.
|
||||
*/
|
||||
pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
|
||||
if (pllOpbDiv == 0)
|
||||
pllOpbDiv = 16;
|
||||
|
||||
/* There is a bug in U-Boot that prevents us from using
|
||||
* bd.bi_opbfreq because U-Boot doesn't populate it for
|
||||
* 405EZ. We get to calculate it, yay!
|
||||
*/
|
||||
freqOPB = (sysclk *pllFbkDiv) /pllOpbDiv;
|
||||
|
||||
freqEBC = (sysclk * pllFbkDiv) / pllExtBusDiv;
|
||||
|
||||
plloutb = ((sysclk * ((cpr_pllc & PLLC_SRC_MASK) ?
|
||||
pllFwdDivB : pllFwdDiv) *
|
||||
pllFbkDiv) / pllFwdDivB);
|
||||
|
||||
np = find_node_by_alias("serial0");
|
||||
if (getprop(np, "current-speed", &baud, sizeof(baud)) != sizeof(baud))
|
||||
fatal("no current-speed property\n\r");
|
||||
|
||||
udiv = 256; /* Assume lowest possible serial clk */
|
||||
div = plloutb / (16 * baud); /* total divisor */
|
||||
umin = (plloutb / freqOPB) << 1; /* 2 x OPB divisor */
|
||||
diff = 256; /* highest possible */
|
||||
|
||||
/* i is the test udiv value -- start with the largest
|
||||
* possible (256) to minimize serial clock and constrain
|
||||
* search to umin.
|
||||
*/
|
||||
for (i = 256; i > umin; i--) {
|
||||
ibdiv = div / i;
|
||||
est = i * ibdiv;
|
||||
idiff = (est > div) ? (est-div) : (div-est);
|
||||
if (idiff == 0) {
|
||||
udiv = i;
|
||||
break; /* can't do better */
|
||||
} else if (idiff < diff) {
|
||||
udiv = i; /* best so far */
|
||||
diff = idiff; /* update lowest diff*/
|
||||
}
|
||||
}
|
||||
freqUART = plloutb / udiv;
|
||||
|
||||
dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_intfreq, bd.bi_plb_busfreq);
|
||||
dt_fixup_clock("/plb/ebc", freqEBC);
|
||||
dt_fixup_clock("/plb/opb", freqOPB);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600300", freqUART);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600400", freqUART);
|
||||
}
|
||||
|
||||
static void acadia_fixups(void)
|
||||
{
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
get_clocks();
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
platform_ops.fixups = acadia_fixups;
|
||||
platform_ops.exit = ibm40x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
@@ -1,139 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Old U-boot compatibility for Esteem 195E Hotfoot CPU Board
|
||||
*
|
||||
* Author: Solomon Peachy <solomon@linux-wlan.com>
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "reg.h"
|
||||
#include "dcr.h"
|
||||
#include "4xx.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_HOTFOOT
|
||||
|
||||
#include "ppcboot-hotfoot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
#define NUM_REGS 3
|
||||
|
||||
static void hotfoot_fixups(void)
|
||||
{
|
||||
u32 uart = mfdcr(DCRN_CPC0_UCR) & 0x7f;
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
|
||||
dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_procfreq, 0);
|
||||
dt_fixup_clock("/plb", bd.bi_plb_busfreq);
|
||||
dt_fixup_clock("/plb/opb", bd.bi_opbfreq);
|
||||
dt_fixup_clock("/plb/ebc", bd.bi_pci_busfreq);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600300", bd.bi_procfreq / uart);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600400", bd.bi_procfreq / uart);
|
||||
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
|
||||
/* Is this a single eth/serial board? */
|
||||
if ((bd.bi_enet1addr[0] == 0) &&
|
||||
(bd.bi_enet1addr[1] == 0) &&
|
||||
(bd.bi_enet1addr[2] == 0) &&
|
||||
(bd.bi_enet1addr[3] == 0) &&
|
||||
(bd.bi_enet1addr[4] == 0) &&
|
||||
(bd.bi_enet1addr[5] == 0)) {
|
||||
void *devp;
|
||||
|
||||
printf("Trimming devtree for single serial/eth board\n");
|
||||
|
||||
devp = finddevice("/plb/opb/serial@ef600300");
|
||||
if (!devp)
|
||||
fatal("Can't find node for /plb/opb/serial@ef600300");
|
||||
del_node(devp);
|
||||
|
||||
devp = finddevice("/plb/opb/ethernet@ef600900");
|
||||
if (!devp)
|
||||
fatal("Can't find node for /plb/opb/ethernet@ef600900");
|
||||
del_node(devp);
|
||||
}
|
||||
|
||||
ibm4xx_quiesce_eth((u32 *)0xef600800, (u32 *)0xef600900);
|
||||
|
||||
/* Fix up flash size in fdt for 4M boards. */
|
||||
if (bd.bi_flashsize < 0x800000) {
|
||||
u32 regs[NUM_REGS];
|
||||
void *devp = finddevice("/plb/ebc/nor_flash@0");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for nor_flash!??");
|
||||
|
||||
printf("Fixing devtree for 4M Flash\n");
|
||||
|
||||
/* First fix up the base address */
|
||||
getprop(devp, "reg", regs, sizeof(regs));
|
||||
regs[0] = 0;
|
||||
regs[1] = 0xffc00000;
|
||||
regs[2] = 0x00400000;
|
||||
setprop(devp, "reg", regs, sizeof(regs));
|
||||
|
||||
/* Then the offsets */
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@0");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@0");
|
||||
getprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
regs[0] -= 0x400000;
|
||||
setprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@1");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@1");
|
||||
getprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
regs[0] -= 0x400000;
|
||||
setprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@2");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@2");
|
||||
getprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
regs[0] -= 0x400000;
|
||||
setprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@3");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@3");
|
||||
getprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
regs[0] -= 0x400000;
|
||||
setprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@4");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@4");
|
||||
getprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
regs[0] -= 0x400000;
|
||||
setprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@6");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@6");
|
||||
getprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
regs[0] -= 0x400000;
|
||||
setprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
|
||||
/* Delete the FeatFS node */
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@5");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@5");
|
||||
del_node(devp);
|
||||
}
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
platform_ops.fixups = hotfoot_fixups;
|
||||
platform_ops.exit = ibm40x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
@@ -1,46 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Old U-boot compatibility for PPC405EX. This image is already included
|
||||
* a dtb.
|
||||
*
|
||||
* Author: Tiejun Chen <tiejun.chen@windriver.com>
|
||||
*
|
||||
* Copyright (C) 2009 Wind River Systems, Inc.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "io.h"
|
||||
#include "dcr.h"
|
||||
#include "stdio.h"
|
||||
#include "4xx.h"
|
||||
#include "44x.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
#define KILAUEA_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void kilauea_fixups(void)
|
||||
{
|
||||
unsigned long sysclk = 33333333;
|
||||
|
||||
ibm405ex_fixup_clocks(sysclk, KILAUEA_SYS_EXT_SERIAL_CLOCK);
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
platform_ops.fixups = kilauea_fixups;
|
||||
platform_ops.exit = ibm40x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
@@ -153,17 +153,6 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
|
||||
#define CPR0_SCPID 0x120
|
||||
#define CPR0_PLLC0 0x40
|
||||
|
||||
/* 405GP Clocking/Power Management/Chip Control regs */
|
||||
#define DCRN_CPC0_PLLMR 0xb0
|
||||
#define DCRN_405_CPC0_CR0 0xb1
|
||||
#define DCRN_405_CPC0_CR1 0xb2
|
||||
#define DCRN_405_CPC0_PSR 0xb4
|
||||
|
||||
/* 405EP Clocking/Power Management/Chip Control regs */
|
||||
#define DCRN_CPC0_PLLMR0 0xf0
|
||||
#define DCRN_CPC0_PLLMR1 0xf4
|
||||
#define DCRN_CPC0_UCR 0xf5
|
||||
|
||||
/* 440GX/405EX Clock Control reg */
|
||||
#define DCRN_CPR0_CLKUPD 0x020
|
||||
#define DCRN_CPR0_PLLC 0x040
|
||||
|
||||
@@ -1,224 +0,0 @@
|
||||
/*
|
||||
* Device Tree Source for AMCC Acadia (405EZ)
|
||||
*
|
||||
* Copyright IBM Corp. 2008
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,acadia";
|
||||
compatible = "amcc,acadia";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405EZ";
|
||||
reg = <0x0>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
timebase-frequency = <0>; /* Filled in by wrapper */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <16384>;
|
||||
d-cache-size = <16384>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0>; /* Filled in by wrapper */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic-405ez", "ibm,uic";
|
||||
interrupt-controller;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
cell-index = <0>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-405ez", "ibm,plb3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-405ez", "ibm,mcmal";
|
||||
dcr-reg = <0x380 0x62>;
|
||||
num-tx-chans = <1>;
|
||||
num-rx-chans = <1>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
/* 405EZ has only 3 interrupts to the UIC, as
|
||||
* SERR, TXDE, and RXDE are or'd together into
|
||||
* one UIC bit
|
||||
*/
|
||||
interrupts = <
|
||||
0x13 0x4 /* TXEOB */
|
||||
0x15 0x4 /* RXEOB */
|
||||
0x12 0x4 /* SERR, TXDE, RXDE */>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405ez", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
dcr-reg = <0x0a 0x05>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x8>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x5 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x8>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x6 0x4>;
|
||||
};
|
||||
|
||||
IIC: i2c@ef600500 {
|
||||
compatible = "ibm,iic-405ez", "ibm,iic";
|
||||
reg = <0xef600500 0x11>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0xa 0x4>;
|
||||
};
|
||||
|
||||
GPIO0: gpio@ef600700 {
|
||||
compatible = "ibm,gpio-405ez";
|
||||
reg = <0xef600700 0x20>;
|
||||
};
|
||||
|
||||
GPIO1: gpio@ef600800 {
|
||||
compatible = "ibm,gpio-405ez";
|
||||
reg = <0xef600800 0x20>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600900 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405ez", "ibm,emac";
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
0x10 0x4 /* Ethernet */
|
||||
0x11 0x4 /* Ethernet Wake up */>;
|
||||
local-mac-address = [000000000000]; /* Filled in by wrapper */
|
||||
reg = <0xef600900 0x70>;
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "mii";
|
||||
phy-map = <0x0>;
|
||||
};
|
||||
|
||||
CAN0: can@ef601000 {
|
||||
compatible = "amcc,can-405ez";
|
||||
reg = <0xef601000 0x620>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x7 0x4>;
|
||||
};
|
||||
|
||||
CAN1: can@ef601800 {
|
||||
compatible = "amcc,can-405ez";
|
||||
reg = <0xef601800 0x620>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x8 0x4>;
|
||||
};
|
||||
|
||||
cameleon@ef602000 {
|
||||
compatible = "amcc,cameleon-405ez";
|
||||
reg = <0xef602000 0x800>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0xb 0x4 0xc 0x4>;
|
||||
};
|
||||
|
||||
ieee1588@ef602800 {
|
||||
compatible = "amcc,ieee1588-405ez";
|
||||
reg = <0xef602800 0x60>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x4 0x4>;
|
||||
/* This thing is a bit weird. It has its own UIC
|
||||
* that it uses to generate snapshot triggers. We
|
||||
* don't really support this device yet, and it needs
|
||||
* work to figure this out.
|
||||
*/
|
||||
dcr-reg = <0xe0 0x9>;
|
||||
};
|
||||
|
||||
usb@ef603000 {
|
||||
compatible = "ohci-be";
|
||||
reg = <0xef603000 0x80>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0xd 0x4 0xe 0x4>;
|
||||
};
|
||||
|
||||
dac@ef603300 {
|
||||
compatible = "amcc,dac-405ez";
|
||||
reg = <0xef603300 0x40>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x18 0x4>;
|
||||
};
|
||||
|
||||
adc@ef603400 {
|
||||
compatible = "amcc,adc-405ez";
|
||||
reg = <0xef603400 0x40>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x17 0x4>;
|
||||
};
|
||||
|
||||
spi@ef603500 {
|
||||
compatible = "amcc,spi-405ez";
|
||||
reg = <0xef603500 0x100>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x9 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405ez", "ibm,ebc";
|
||||
dcr-reg = <0x12 0x2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "/plb/opb/serial@ef600300";
|
||||
};
|
||||
};
|
||||
@@ -1,281 +0,0 @@
|
||||
/*
|
||||
* Device Tree Source for AMCC Haleakala (405EXr)
|
||||
*
|
||||
* Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,haleakala";
|
||||
compatible = "amcc,haleakala", "amcc,kilauea";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405EXr";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <16384>; /* 16 kB */
|
||||
d-cache-size = <16384>; /* 16 kB */
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic-405exr", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-405exr","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-405exr","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-405exr", "ibm,plb4";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-405exr", "ibm,sdram-4xx-ddr2";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0x5 0x4 /* ECC DED Error */
|
||||
0x6 0x4>; /* ECC SEC Error */
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-405exr", "ibm,mcmal2";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
interrupt-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405exr", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x80000000 0x80000000 0x10000000
|
||||
0xef600000 0xef600000 0x00a00000
|
||||
0xf0000000 0xf0000000 0x10000000>;
|
||||
dcr-reg = <0x0a0 0x005>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405exr", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <0x5 0x1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0x00000000 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <0x00200000 0x00200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "user";
|
||||
reg = <0x00400000 0x03b60000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600200 0x00000008>;
|
||||
virtual-reg = <0xef600200>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1a 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600400 {
|
||||
compatible = "ibm,iic-405exr", "ibm,iic";
|
||||
reg = <0xef600400 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600500 {
|
||||
compatible = "ibm,iic-405exr", "ibm,iic";
|
||||
reg = <0xef600500 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x7 0x4>;
|
||||
};
|
||||
|
||||
|
||||
RGMII0: emac-rgmii@ef600b00 {
|
||||
compatible = "ibm,rgmii-405exr", "ibm,rgmii";
|
||||
reg = <0xef600b00 0x00000104>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600900 {
|
||||
linux,network-index = <0x0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405exr", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
|
||||
/*Wake*/ 0x1 &UIC1 0x1d 0x4>;
|
||||
reg = <0xef600900 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
tx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
|
||||
PCIE0: pcie@a0000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0xa0000000 0x20000000 /* Config space access */
|
||||
0xef000000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x040 0x020>;
|
||||
sdr-base = <0x400>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
|
||||
0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0x00 to 0x3f */
|
||||
bus-range = <0x0 0x3f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,296 +0,0 @@
|
||||
/*
|
||||
* Device Tree Source for ESTeem 195E Hotfoot
|
||||
*
|
||||
* Copyright 2009 AbsoluteValue Systems <solomon@linux-wlan.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "est,hotfoot";
|
||||
compatible = "est,hotfoot";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405EP";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <0x20>;
|
||||
d-cache-line-size = <0x20>;
|
||||
i-cache-size = <0x4000>;
|
||||
d-cache-size = <0x4000>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-405ep";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL: mcmal {
|
||||
compatible = "ibm,mcmal-405ep", "ibm,mcmal";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <4>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
0xb 0x4 /* TXEOB */
|
||||
0xc 0x4 /* RXEOB */
|
||||
0xa 0x4 /* SERR */
|
||||
0xd 0x4 /* TXDE */
|
||||
0xe 0x4 /* RXDE */>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405ep", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xef600000 0xef600000 0x00a00000>;
|
||||
dcr-reg = <0x0a0 0x005>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
/* Hotfoot has UART0/UART1 swapped */
|
||||
|
||||
UART0: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <0x9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <0x9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
IIC: i2c@ef600500 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "ibm,iic-405ep", "ibm,iic";
|
||||
reg = <0xef600500 0x00000011>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
|
||||
rtc@68 {
|
||||
/* Actually a DS1339 */
|
||||
compatible = "dallas,ds1307";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
temp@4a {
|
||||
/* Not present on all boards */
|
||||
compatible = "national,lm75";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
};
|
||||
|
||||
GPIO: gpio@ef600700 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "ibm,ppc4xx-gpio";
|
||||
reg = <0xef600700 0x00000020>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
status {
|
||||
label = "Status";
|
||||
gpios = <&GPIO 1 0>;
|
||||
};
|
||||
radiorx {
|
||||
label = "Rx";
|
||||
gpios = <&GPIO 0xe 0>;
|
||||
};
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600800 {
|
||||
linux,network-index = <0x0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405ep", "ibm,emac";
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
0xf 0x4 /* Ethernet */
|
||||
0x9 0x4 /* Ethernet Wake Up */>;
|
||||
local-mac-address = [000000000000]; /* Filled in by zImage */
|
||||
reg = <0xef600800 0x00000070>;
|
||||
mal-device = <&MAL>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <0x5dc>;
|
||||
rx-fifo-size = <0x1000>;
|
||||
tx-fifo-size = <0x800>;
|
||||
phy-mode = "mii";
|
||||
phy-map = <0x00000000>;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600900 {
|
||||
linux,network-index = <0x1>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405ep", "ibm,emac";
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
0x11 0x4 /* Ethernet */
|
||||
0x9 0x4 /* Ethernet Wake Up */>;
|
||||
local-mac-address = [000000000000]; /* Filled in by zImage */
|
||||
reg = <0xef600900 0x00000070>;
|
||||
mal-device = <&MAL>;
|
||||
mal-tx-channel = <2>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <0x5dc>;
|
||||
rx-fifo-size = <0x1000>;
|
||||
tx-fifo-size = <0x800>;
|
||||
mdio-device = <&EMAC0>;
|
||||
phy-mode = "mii";
|
||||
phy-map = <0x0000001>;
|
||||
};
|
||||
};
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405ep", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* The ranges property is supplied by the bootwrapper
|
||||
* and is based on the firmware's configuration of the
|
||||
* EBC bridge
|
||||
*/
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
nor_flash@0 {
|
||||
compatible = "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0x0 0xff800000 0x00800000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* This mapping is for the 8M flash
|
||||
4M flash has all ofssets -= 4M,
|
||||
and FeatFS partition is not present */
|
||||
partition@0 {
|
||||
label = "Bootloader";
|
||||
reg = <0x7c0000 0x40000>;
|
||||
/* read-only; */
|
||||
};
|
||||
partition@1 {
|
||||
label = "Env_and_Config_Primary";
|
||||
reg = <0x400000 0x10000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "Kernel";
|
||||
reg = <0x420000 0x100000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "Filesystem";
|
||||
reg = <0x520000 0x2a0000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "Env_and_Config_Secondary";
|
||||
reg = <0x410000 0x10000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "FeatFS";
|
||||
reg = <0x000000 0x400000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "Bootloader_Env";
|
||||
reg = <0x7d0000 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
PCI0: pci@ec000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <0xeec00000 0x00000008 /* Config space access */
|
||||
0xeed80000 0x00000004 /* IACK */
|
||||
0xeed80000 0x00000004 /* Special cycle */
|
||||
0xef480000 0x00000040>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
|
||||
0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 3 -- slot1 (optional) 27/29 A/B IRQ2/4 */
|
||||
0x1800 0x0 0x0 0x1 &UIC0 0x1b 0x8
|
||||
0x1800 0x0 0x0 0x2 &UIC0 0x1d 0x8
|
||||
|
||||
/* IDSEL 4 -- slot0, 26/28 A/B IRQ1/3 */
|
||||
0x2000 0x0 0x0 0x1 &UIC0 0x1a 0x8
|
||||
0x2000 0x0 0x0 0x2 &UIC0 0x1c 0x8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &UART0;
|
||||
};
|
||||
};
|
||||
@@ -1,407 +0,0 @@
|
||||
/*
|
||||
* Device Tree Source for AMCC Kilauea (405EX)
|
||||
*
|
||||
* Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,kilauea";
|
||||
compatible = "amcc,kilauea";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405EX";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <16384>; /* 16 kB */
|
||||
d-cache-size = <16384>; /* 16 kB */
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic-405ex", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-405ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-405ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
CPM0: cpm {
|
||||
compatible = "ibm,cpm";
|
||||
dcr-access-method = "native";
|
||||
dcr-reg = <0x0b0 0x003>;
|
||||
unused-units = <0x00000000>;
|
||||
idle-doze = <0x02000000>;
|
||||
standby = <0xe3e74800>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-405ex", "ibm,plb4";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0x5 0x4 /* ECC DED Error */
|
||||
0x6 0x4>; /* ECC SEC Error */
|
||||
};
|
||||
|
||||
CRYPTO: crypto@ef700000 {
|
||||
compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
|
||||
reg = <0xef700000 0x80400>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x17 0x2>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
interrupt-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405ex", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x80000000 0x80000000 0x10000000
|
||||
0xef600000 0xef600000 0x00a00000
|
||||
0xf0000000 0xf0000000 0x10000000>;
|
||||
dcr-reg = <0x0a0 0x005>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405ex", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <0x5 0x1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0x00000000 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x001e0000>;
|
||||
};
|
||||
partition@1e0000 {
|
||||
label = "dtb";
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <0x00200000 0x00200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "user";
|
||||
reg = <0x00400000 0x03b60000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
|
||||
ndfc@1,0 {
|
||||
compatible = "ibm,ndfc";
|
||||
reg = <0x00000001 0x00000000 0x00002000>;
|
||||
ccr = <0x00001000>;
|
||||
bank-settings = <0x80002222>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
nand {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x00000000 0x00100000>;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "user";
|
||||
reg = <0x00000000 0x03f00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600200 0x00000008>;
|
||||
virtual-reg = <0xef600200>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1a 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600400 {
|
||||
compatible = "ibm,iic-405ex", "ibm,iic";
|
||||
reg = <0xef600400 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
dtt@48 {
|
||||
compatible = "dallas,ds1775";
|
||||
reg = <0x48>;
|
||||
};
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600500 {
|
||||
compatible = "ibm,iic-405ex", "ibm,iic";
|
||||
reg = <0xef600500 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x7 0x4>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef600b00 {
|
||||
compatible = "ibm,rgmii-405ex", "ibm,rgmii";
|
||||
reg = <0xef600b00 0x00000104>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600900 {
|
||||
linux,network-index = <0x0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
|
||||
/*Wake*/ 0x1 &UIC1 0x1d 0x4>;
|
||||
reg = <0xef600900 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
tx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600a00 {
|
||||
linux,network-index = <0x1>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
|
||||
/*Wake*/ 0x1 &UIC1 0x1f 0x4>;
|
||||
reg = <0xef600a00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
tx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
|
||||
PCIE0: pcie@a0000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0xa0000000 0x20000000 /* Config space access */
|
||||
0xef000000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x040 0x020>;
|
||||
sdr-base = <0x400>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
|
||||
0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0x00 to 0x3f */
|
||||
bus-range = <0x0 0x3f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pcie@c0000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0xc0000000 0x20000000 /* Config space access */
|
||||
0xef001000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x060 0x020>;
|
||||
sdr-base = <0x440>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
|
||||
0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0x40 to 0x7f */
|
||||
bus-range = <0x40 0x7f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,212 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Device Tree for Klondike (APM8018X) board.
|
||||
*
|
||||
* Copyright (c) 2010, Applied Micro Circuits Corporation
|
||||
* Author: Tanmay Inamdar <tinamdar@apm.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "apm,klondike";
|
||||
compatible = "apm,klondike";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,apm8018x";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <300000000>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <300000000>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <16384>; /* 16 kB */
|
||||
d-cache-size = <16384>; /* 16 kB */
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x010>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x010>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x010>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x0a 0x4 0x0b 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC3: interrupt-controller3 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0x0f0 0x010>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb4";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-apm8018x";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal2";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <16>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = </*TXEOB*/ 0x6 0x4
|
||||
/*RXEOB*/ 0x7 0x4
|
||||
/*SERR*/ 0x1 0x4
|
||||
/*TXDE*/ 0x2 0x4
|
||||
/*RXDE*/ 0x3 0x4>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x20000000 0x20000000 0x30000000
|
||||
0x50000000 0x50000000 0x10000000
|
||||
0x60000000 0x60000000 0x10000000
|
||||
0xFE000000 0xFE000000 0x00010000>;
|
||||
dcr-reg = <0x100 0x020>;
|
||||
clock-frequency = <300000000>; /* Filled in by U-Boot */
|
||||
|
||||
RGMII0: emac-rgmii@400a2000 {
|
||||
compatible = "ibm,rgmii";
|
||||
reg = <0x400a2000 0x00000010>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@400a3000 {
|
||||
compatible = "ibm,tah";
|
||||
reg = <0x400a3000 0x100>;
|
||||
};
|
||||
|
||||
TAH1: emac-tah@400a4000 {
|
||||
compatible = "ibm,tah";
|
||||
reg = <0x400a4000 0x100>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@400a0000 {
|
||||
compatible = "ibm,emac4", "ibm-emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4>;
|
||||
reg = <0x400a0000 0x00000100>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0x0>;
|
||||
mal-rx-channel = <0x0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-address = <0x2>;
|
||||
turbo = "no";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
tah-device = <&TAH0>;
|
||||
tah-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@400a1000 {
|
||||
compatible = "ibm,emac4", "ibm-emac4sync";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0x0>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4>;
|
||||
reg = <0x400a1000 0x00000100>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <8>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-address = <0x3>;
|
||||
turbo = "no";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
tah-device = <&TAH1>;
|
||||
tah-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "/plb/opb/serial@50001000";
|
||||
};
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user