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Merge tag 'asoc-v6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus

Browse Source 
ASoC: Updates for v6.10

This is a very big update, in large part due to extensive work the Intel
people have been doing in their drivers though it's also been busy
elsewhere.  There's also a big overhaul of the DAPM documentation from
Luca Ceresoli arising from the work he did putting together his recent
ELC talk, and he also contributed a new tool for visualising the DAPM
state.

 - A new tool dapm-graph for visualising the DAPM state.
 - Substantial fixes and clarifications for the DAPM documentation.
 - Very large updates throughout the Intel audio drivers.
 - Cleanups of accessors for driver data, module labelling, and for
   constification.
 - Modernsation and cleanup work in the Mediatek drivers.
 - Several fixes and features for the DaVinci I2S driver.
 - New drivers for several AMD and Intel platforms, Nuvoton NAU8325,
   Rockchip RK3308 and Texas Instruments PCM6240.
This commit is contained in:
Takashi Iwai
2024-05-13 11:39:49 +02:00
parent 762e6af398 c3c5ac4bd7
commit 3a07362fab
1365 changed files with 28588 additions and 16668 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
.mailmap
View File

@@ -38,6 +38,16 @@ Alexei Starovoitov <ast@kernel.org> <alexei.starovoitov@gmail.com>
Alexei Starovoitov <ast@kernel.org> <ast@fb.com>
Alexei Starovoitov <ast@kernel.org> <ast@plumgrid.com>
Alexey Makhalov <alexey.amakhalov@broadcom.com> <amakhalov@vmware.com>
Alex Elder <elder@kernel.org>
Alex Elder <elder@kernel.org> <aelder@sgi.com>
Alex Elder <elder@kernel.org> <alex.elder@linaro.org>
Alex Elder <elder@kernel.org> <alex.elder@linary.org>
Alex Elder <elder@kernel.org> <elder@dreamhost.com>
Alex Elder <elder@kernel.org> <elder@dreawmhost.com>
Alex Elder <elder@kernel.org> <elder@ieee.org>
Alex Elder <elder@kernel.org> <elder@inktank.com>
Alex Elder <elder@kernel.org> <elder@linaro.org>
Alex Elder <elder@kernel.org> <elder@newdream.net>
Alex Hung <alexhung@gmail.com> <alex.hung@canonical.com>
Alex Shi <alexs@kernel.org> <alex.shi@intel.com>
Alex Shi <alexs@kernel.org> <alex.shi@linaro.org>
@@ -98,6 +108,8 @@ Ben Widawsky <bwidawsk@kernel.org> <ben@bwidawsk.net>
Ben Widawsky <bwidawsk@kernel.org> <ben.widawsky@intel.com>
Ben Widawsky <bwidawsk@kernel.org> <benjamin.widawsky@intel.com>
Benjamin Poirier <benjamin.poirier@gmail.com> <bpoirier@suse.de>
Benjamin Tissoires <bentiss@kernel.org> <benjamin.tissoires@gmail.com>
Benjamin Tissoires <bentiss@kernel.org> <benjamin.tissoires@redhat.com>
Bjorn Andersson <andersson@kernel.org> <bjorn@kryo.se>
Bjorn Andersson <andersson@kernel.org> <bjorn.andersson@linaro.org>
Bjorn Andersson <andersson@kernel.org> <bjorn.andersson@sonymobile.com>
@@ -446,7 +458,8 @@ Mythri P K <mythripk@ti.com>
Nadav Amit <nadav.amit@gmail.com> <namit@vmware.com>
Nadav Amit <nadav.amit@gmail.com> <namit@cs.technion.ac.il>
Nadia Yvette Chambers <nyc@holomorphy.com> William Lee Irwin III <wli@holomorphy.com>
Naoya Horiguchi <naoya.horiguchi@nec.com> <n-horiguchi@ah.jp.nec.com>
Naoya Horiguchi <nao.horiguchi@gmail.com> <n-horiguchi@ah.jp.nec.com>
Naoya Horiguchi <nao.horiguchi@gmail.com> <naoya.horiguchi@nec.com>
Nathan Chancellor <nathan@kernel.org> <natechancellor@gmail.com>
Neeraj Upadhyay <quic_neeraju@quicinc.com> <neeraju@codeaurora.org>
Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com>
@@ -524,6 +537,7 @@ Rémi Denis-Courmont <rdenis@simphalempin.com>
Ricardo Ribalda <ribalda@kernel.org> <ricardo@ribalda.com>
Ricardo Ribalda <ribalda@kernel.org> Ricardo Ribalda Delgado <ribalda@kernel.org>
Ricardo Ribalda <ribalda@kernel.org> <ricardo.ribalda@gmail.com>
Richard Genoud <richard.genoud@bootlin.com> <richard.genoud@gmail.com>
Richard Leitner <richard.leitner@linux.dev> <dev@g0hl1n.net>
Richard Leitner <richard.leitner@linux.dev> <me@g0hl1n.net>
Richard Leitner <richard.leitner@linux.dev> <richard.leitner@skidata.com>

4
CREDITS
View File

@@ -3146,6 +3146,10 @@ S: Triftstra=DFe 55
S: 13353 Berlin
S: Germany
N: Gustavo Pimental
E: gustavo.pimentel@synopsys.com
D: PCI driver for Synopsys DesignWare
N: Emanuel Pirker
E: epirker@edu.uni-klu.ac.at
D: AIC5800 IEEE 1394, RAW I/O on 1394

44
Documentation/admin-guide/hw-vuln/spectre.rst
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@@ -138,11 +138,10 @@ associated with the source address of the indirect branch. Specifically,
the BHB might be shared across privilege levels even in the presence of
Enhanced IBRS.
Currently the only known real-world BHB attack vector is via
unprivileged eBPF. Therefore, it's highly recommended to not enable
unprivileged eBPF, especially when eIBRS is used (without retpolines).
For a full mitigation against BHB attacks, it's recommended to use
retpolines (or eIBRS combined with retpolines).
Previously the only known real-world BHB attack vector was via unprivileged
eBPF. Further research has found attacks that don't require unprivileged eBPF.
For a full mitigation against BHB attacks it is recommended to set BHI_DIS_S or
use the BHB clearing sequence.
Attack scenarios
----------------
@@ -430,6 +429,23 @@ The possible values in this file are:
'PBRSB-eIBRS: Not affected' CPU is not affected by PBRSB
=========================== =======================================================
- Branch History Injection (BHI) protection status:
.. list-table::
* - BHI: Not affected
- System is not affected
* - BHI: Retpoline
- System is protected by retpoline
* - BHI: BHI_DIS_S
- System is protected by BHI_DIS_S
* - BHI: SW loop, KVM SW loop
- System is protected by software clearing sequence
* - BHI: Vulnerable
- System is vulnerable to BHI
* - BHI: Vulnerable, KVM: SW loop
- System is vulnerable; KVM is protected by software clearing sequence
Full mitigation might require a microcode update from the CPU
vendor. When the necessary microcode is not available, the kernel will
report vulnerability.
@@ -484,7 +500,11 @@ Spectre variant 2
Systems which support enhanced IBRS (eIBRS) enable IBRS protection once at
boot, by setting the IBRS bit, and they're automatically protected against
Spectre v2 variant attacks.
some Spectre v2 variant attacks. The BHB can still influence the choice of
indirect branch predictor entry, and although branch predictor entries are
isolated between modes when eIBRS is enabled, the BHB itself is not isolated
between modes. Systems which support BHI_DIS_S will set it to protect against
BHI attacks.
On Intel's enhanced IBRS systems, this includes cross-thread branch target
injections on SMT systems (STIBP). In other words, Intel eIBRS enables
@@ -638,6 +658,18 @@ kernel command line.
spectre_v2=off. Spectre variant 1 mitigations
cannot be disabled.
spectre_bhi=
[X86] Control mitigation of Branch History Injection
(BHI) vulnerability. This setting affects the deployment
of the HW BHI control and the SW BHB clearing sequence.
on
(default) Enable the HW or SW mitigation as
needed.
off
Disable the mitigation.
For spectre_v2_user see Documentation/admin-guide/kernel-parameters.txt
Mitigation selection guide

10
Documentation/admin-guide/kernel-parameters.txt
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@@ -3444,6 +3444,7 @@
retbleed=off [X86]
spec_rstack_overflow=off [X86]
spec_store_bypass_disable=off [X86,PPC]
spectre_bhi=off [X86]
spectre_v2_user=off [X86]
srbds=off [X86,INTEL]
ssbd=force-off [ARM64]
@@ -6063,6 +6064,15 @@
sonypi.*= [HW] Sony Programmable I/O Control Device driver
See Documentation/admin-guide/laptops/sonypi.rst
spectre_bhi= [X86] Control mitigation of Branch History Injection
(BHI) vulnerability. This setting affects the
deployment of the HW BHI control and the SW BHB
clearing sequence.
on - (default) Enable the HW or SW mitigation
as needed.
off - Disable the mitigation.
spectre_v2= [X86,EARLY] Control mitigation of Spectre variant 2
(indirect branch speculation) vulnerability.
The default operation protects the kernel from

597
Documentation/admin-guide/verify-bugs-and-bisect-regressions.rst
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9
Documentation/devicetree/bindings/display/msm/qcom,sm8150-mdss.yaml
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@@ -53,6 +53,15 @@ patternProperties:
compatible:
const: qcom,sm8150-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
const: qcom,sm8150-dp
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true

3
Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
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@@ -52,6 +52,9 @@ properties:
- const: main
- const: mm
power-domains:
maxItems: 1
required:
- compatible
- reg

2
Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
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@@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
maintainers:
- Richard Genoud <richard.genoud@gmail.com>
- Richard Genoud <richard.genoud@bootlin.com>
properties:
compatible:

50
Documentation/devicetree/bindings/sound/davinci-mcbsp.txt
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@@ -1,50 +0,0 @@
Texas Instruments DaVinci McBSP module
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This binding describes the "Multi-channel Buffered Serial Port" (McBSP)
audio interface found in some TI DaVinci processors like the OMAP-L138 or AM180x.
Required properties:
~~~~~~~~~~~~~~~~~~~~
- compatible :
"ti,da850-mcbsp" : for DA850, AM180x and OPAM-L138 platforms
- reg : physical base address and length of the controller memory mapped
region(s).
- reg-names : Should contain:
* "mpu" for the main registers (required).
* "dat" for the data FIFO (optional).
- dmas: three element list of DMA controller phandles, DMA request line and
TC channel ordered triplets.
- dma-names: identifier string for each DMA request line in the dmas property.
These strings correspond 1:1 with the ordered pairs in dmas. The dma
identifiers must be "rx" and "tx".
Optional properties:
~~~~~~~~~~~~~~~~~~~~
- interrupts : Interrupt numbers for McBSP
- interrupt-names : Known interrupt names are "rx" and "tx"
- pinctrl-0: Should specify pin control group used for this controller.
- pinctrl-names: Should contain only one value - "default", for more details
please refer to pinctrl-bindings.txt
Example (AM1808):
~~~~~~~~~~~~~~~~~
mcbsp0: mcbsp@1d10000 {
compatible = "ti,da850-mcbsp";
pinctrl-names = "default";
pinctrl-0 = <&mcbsp0_pins>;
reg = <0x00110000 0x1000>,
<0x00310000 0x1000>;
reg-names = "mpu", "dat";
interrupts = <97 98>;
interrupt-names = "rx", "tx";
dmas = <&edma0 3 1
&edma0 2 1>;
dma-names = "tx", "rx";
};

113
Documentation/devicetree/bindings/sound/davinci-mcbsp.yaml Normal file
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@@ -0,0 +1,113 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/davinci-mcbsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: McBSP Controller for TI SoCs
maintainers:
- Bastien Curutchet <bastien.curutchet@bootlin.com>
allOf:
- $ref: dai-common.yaml#
properties:
compatible:
enum:
- ti,da850-mcbsp
reg:
minItems: 1
items:
- description: CFG registers
- description: data registers
reg-names:
minItems: 1
items:
- const: mpu
- const: dat
dmas:
items:
- description: transmission DMA channel
- description: reception DMA channel
dma-names:
items:
- const: tx
- const: rx
interrupts:
items:
- description: RX interrupt
- description: TX interrupt
interrupt-names:
items:
- const: rx
- const: tx
clocks:
minItems: 1
items:
- description: functional clock
- description: external input clock for sample rate generator.
clock-names:
minItems: 1
items:
- const: fck
- const: clks
power-domains:
maxItems: 1
"#sound-dai-cells":
const: 0
ti,T1-framing-tx:
$ref: /schemas/types.yaml#/definitions/flag
description:
If the property is present, tx data delay is set to 2 bit clock periods.
McBSP will insert a blank period (high-impedance period) before the first
data bit. This can be used to interface to T1-framing devices.
ti,T1-framing-rx:
$ref: /schemas/types.yaml#/definitions/flag
description:
If the property is present, rx data delay is set to 2 bit clock periods.
McBSP will discard the bit preceding the data stream (called framing bit).
This can be used to interface to T1-framing devices.
required:
- "#sound-dai-cells"
- compatible
- reg
- reg-names
- dmas
- dma-names
- clocks
unevaluatedProperties: false
examples:
- |
mcbsp0@1d10000 {
#sound-dai-cells = <0>;
compatible = "ti,da850-mcbsp";
pinctrl-names = "default";
pinctrl-0 = <&mcbsp0_pins>;
reg = <0x111000 0x1000>,
<0x311000 0x1000>;
reg-names = "mpu", "dat";
interrupts = <97>, <98>;
interrupt-names = "rx", "tx";
dmas = <&edma0 3 1>,
<&edma0 2 1>;
dma-names = "tx", "rx";
clocks = <&psc1 14>;
};

50
Documentation/devicetree/bindings/sound/fsl,audmix.txt
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@@ -1,50 +0,0 @@
NXP Audio Mixer (AUDMIX).
The Audio Mixer is a on-chip functional module that allows mixing of two
audio streams into a single audio stream. Audio Mixer has two input serial
audio interfaces. These are driven by two Synchronous Audio interface
modules (SAI). Each input serial interface carries 8 audio channels in its
frame in TDM manner. Mixer mixes audio samples of corresponding channels
from two interfaces into a single sample. Before mixing, audio samples of
two inputs can be attenuated based on configuration. The output of the
Audio Mixer is also a serial audio interface. Like input interfaces it has
the same TDM frame format. This output is used to drive the serial DAC TDM
interface of audio codec and also sent to the external pins along with the
receive path of normal audio SAI module for readback by the CPU.
The output of Audio Mixer can be selected from any of the three streams
- serial audio input 1
- serial audio input 2
- mixed audio
Mixing operation is independent of audio sample rate but the two audio
input streams must have same audio sample rate with same number of channels
in TDM frame to be eligible for mixing.
Device driver required properties:
=================================
- compatible : Compatible list, contains "fsl,imx8qm-audmix"
- reg : Offset and length of the register set for the device.
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the "ipg" for register access.
- power-domains : Must contain the phandle to AUDMIX power domain node
- dais : Must contain a list of phandles to AUDMIX connected
DAIs. The current implementation requires two phandles
to SAI interfaces to be provided, the first SAI in the
list being used to route the AUDMIX output.
Device driver configuration example:
======================================
audmix: audmix@59840000 {
compatible = "fsl,imx8qm-audmix";
reg = <0x0 0x59840000 0x0 0x10000>;
clocks = <&clk IMX8QXP_AUD_AUDMIX_IPG>;
clock-names = "ipg";
power-domains = <&pd_audmix>;
dais = <&sai4>, <&sai5>;
};

83
Documentation/devicetree/bindings/sound/fsl,audmix.yaml Normal file
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@@ -0,0 +1,83 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/fsl,audmix.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP Audio Mixer (AUDMIX).
maintainers:
- Shengjiu Wang <shengjiu.wang@nxp.com>
- Frank Li <Frank.Li@nxp.com>
description: |
The Audio Mixer is a on-chip functional module that allows mixing of two
audio streams into a single audio stream. Audio Mixer has two input serial
audio interfaces. These are driven by two Synchronous Audio interface
modules (SAI). Each input serial interface carries 8 audio channels in its
frame in TDM manner. Mixer mixes audio samples of corresponding channels
from two interfaces into a single sample. Before mixing, audio samples of
two inputs can be attenuated based on configuration. The output of the
Audio Mixer is also a serial audio interface. Like input interfaces it has
the same TDM frame format. This output is used to drive the serial DAC TDM
interface of audio codec and also sent to the external pins along with the
receive path of normal audio SAI module for readback by the CPU.
The output of Audio Mixer can be selected from any of the three streams
- serial audio input 1
- serial audio input 2
- mixed audio
Mixing operation is independent of audio sample rate but the two audio
input streams must have same audio sample rate with same number of channels
in TDM frame to be eligible for mixing.
properties:
compatible:
const: fsl,imx8qm-audmix
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: ipg
power-domains:
maxItems: 1
dais:
description: contain a list of phandles to AUDMIX connected DAIs.
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 2
items:
- description: the AUDMIX output
maxItems: 1
- description: serial audio input 1
maxItems: 1
- description: serial audio input 2
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- power-domains
- dais
unevaluatedProperties: false
examples:
- |
audmix@59840000 {
compatible = "fsl,imx8qm-audmix";
reg = <0x59840000 0x10000>;
clocks = <&amix_lpcg 0>;
clock-names = "ipg";
power-domains = <&pd_audmix>;
dais = <&sai4>, <&sai5>;
};

68
Documentation/devicetree/bindings/sound/fsl,esai.txt
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@@ -1,68 +0,0 @@
Freescale Enhanced Serial Audio Interface (ESAI) Controller
The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
for serial communication with a variety of serial devices, including industry
standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and
other DSPs. It has up to six transmitters and four receivers.
Required properties:
- compatible : Compatible list, should contain one of the following
compatibles:
"fsl,imx35-esai",
"fsl,vf610-esai",
"fsl,imx6ull-esai",
"fsl,imx8qm-esai",
- reg : Offset and length of the register set for the device.
- interrupts : Contains the spdif interrupt.
- dmas : Generic dma devicetree binding as described in
Documentation/devicetree/bindings/dma/dma.txt.
- dma-names : Two dmas have to be defined, "tx" and "rx".
- clocks : Contains an entry for each entry in clock-names.
- clock-names : Includes the following entries:
"core" The core clock used to access registers
"extal" The esai baud clock for esai controller used to
derive HCK, SCK and FS.
"fsys" The system clock derived from ahb clock used to
derive HCK, SCK and FS.
"spba" The spba clock is required when ESAI is placed as a
bus slave of the Shared Peripheral Bus and when two
or more bus masters (CPU, DMA or DSP) try to access
it. This property is optional depending on the SoC
design.
- fsl,fifo-depth : The number of elements in the transmit and receive
FIFOs. This number is the maximum allowed value for
TFCR[TFWM] or RFCR[RFWM].
- fsl,esai-synchronous: This is a boolean property. If present, indicating
that ESAI would work in the synchronous mode, which
means all the settings for Receiving would be
duplicated from Transmission related registers.
Optional properties:
- big-endian : If this property is absent, the native endian mode
will be in use as default, or the big endian mode
will be in use for all the device registers.
Example:
esai: esai@2024000 {
compatible = "fsl,imx35-esai";
reg = <0x02024000 0x4000>;
interrupts = <0 51 0x04>;
clocks = <&clks 208>, <&clks 118>, <&clks 208>;
clock-names = "core", "extal", "fsys";
dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <128>;
fsl,esai-synchronous;
big-endian;
};

118
Documentation/devicetree/bindings/sound/fsl,esai.yaml Normal file
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@@ -0,0 +1,118 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/fsl,esai.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Enhanced Serial Audio Interface (ESAI) Controller
maintainers:
- Shengjiu Wang <shengjiu.wang@nxp.com>
- Frank Li <Frank.Li@nxp.com>
description:
The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
for serial communication with a variety of serial devices, including industry
standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and
other DSPs. It has up to six transmitters and four receivers.
properties:
compatible:
enum:
- fsl,imx35-esai
- fsl,imx6ull-esai
- fsl,imx8qm-esai
- fsl,vf610-esai
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 3
items:
- description:
The core clock used to access registers.
- description:
The esai baud clock for esai controller used to
derive HCK, SCK and FS.
- description:
The system clock derived from ahb clock used to
derive HCK, SCK and FS.
- description:
The spba clock is required when ESAI is placed as a
bus slave of the Shared Peripheral Bus and when two
or more bus masters (CPU, DMA or DSP) try to access
it. This property is optional depending on the SoC
design.
clock-names:
minItems: 3
items:
- const: core
- const: extal
- const: fsys
- const: spba
dmas:
minItems: 2
maxItems: 2
dma-names:
items:
- const: rx
- const: tx
fsl,fifo-depth:
$ref: /schemas/types.yaml#/definitions/uint32
default: 64
description:
The number of elements in the transmit and receive
FIFOs. This number is the maximum allowed value for
TFCR[TFWM] or RFCR[RFWM].
fsl,esai-synchronous:
$ref: /schemas/types.yaml#/definitions/flag
description:
This is a boolean property. If present, indicating
that ESAI would work in the synchronous mode, which
means all the settings for Receiving would be
duplicated from Transmission related registers.
big-endian:
$ref: /schemas/types.yaml#/definitions/flag
description:
If this property is absent, the native endian mode
will be in use as default, or the big endian mode
will be in use for all the device registers.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- dmas
- dma-names
unevaluatedProperties: false
allOf:
- $ref: dai-common.yaml#
examples:
- |
esai@2024000 {
compatible = "fsl,imx35-esai";
reg = <0x02024000 0x4000>;
interrupts = <0 51 0x04>;
clocks = <&clks 208>, <&clks 118>, <&clks 208>;
clock-names = "core", "extal", "fsys";
dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <128>;
fsl,esai-synchronous;
big-endian;
};

14
Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml
View File

@@ -74,6 +74,9 @@ properties:
- const: asrck_f
- const: spba
power-domains:
maxItems: 1
fsl,asrc-rate:
$ref: /schemas/types.yaml#/definitions/uint32
description: The mutual sample rate used by DPCM Back Ends
@@ -131,6 +134,17 @@ allOf:
properties:
fsl,asrc-clk-map: false
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qm-asrc
- fsl,imx8qxp-asrc
then:
required:
- power-domains
additionalProperties: false
examples:

66
Documentation/devicetree/bindings/sound/fsl,imx-audio-spdif.yaml Normal file
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@@ -0,0 +1,66 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/fsl,imx-audio-spdif.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX audio complex with S/PDIF transceiver
maintainers:
- Shengjiu Wang <shengjiu.wang@nxp.com>
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,imx-sabreauto-spdif
- fsl,imx6sx-sdb-spdif
- const: fsl,imx-audio-spdif
- enum:
- fsl,imx-audio-spdif
model:
$ref: /schemas/types.yaml#/definitions/string
description: User specified audio sound card name
spdif-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of the i.MX S/PDIF controller
spdif-out:
type: boolean
description:
If present, the transmitting function of S/PDIF will be enabled,
indicating there's a physical S/PDIF out connector or jack on the
board or it's connecting to some other IP block, such as an HDMI
encoder or display-controller.
spdif-in:
type: boolean
description:
If present, the receiving function of S/PDIF will be enabled,
indicating there is a physical S/PDIF in connector/jack on the board.
required:
- compatible
- model
- spdif-controller
anyOf:
- required:
- spdif-in
- required:
- spdif-out
additionalProperties: false
examples:
- |
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-out;
spdif-in;
};

6
Documentation/devicetree/bindings/sound/fsl,sai.yaml
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@@ -81,14 +81,12 @@ properties:
dmas:
minItems: 1
items:
- description: DMA controller phandle and request line for RX
- description: DMA controller phandle and request line for TX
maxItems: 2
dma-names:
minItems: 1
items:
- const: rx
- enum: [ rx, tx ]
- const: tx
interrupts:

35
Documentation/devicetree/bindings/sound/fsl,spdif.yaml
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@@ -31,7 +31,10 @@ properties:
maxItems: 1
interrupts:
maxItems: 1
minItems: 1
items:
- description: Combined or receive interrupt
- description: Transmit interrupt
dmas:
items:
@@ -86,6 +89,9 @@ properties:
registers. Set this flag for HCDs with big endian descriptors and big
endian registers.
power-domains:
maxItems: 1
required:
- compatible
- reg
@@ -97,6 +103,33 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
enum:
- fsl,imx8qm-spdif
- fsl,imx8qxp-spdif
then:
properties:
interrupts:
minItems: 2
else:
properties:
interrupts:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qm-spdif
- fsl,imx8qxp-spdif
then:
required:
- power-domains
examples:
- |
spdif@2004000 {

87
Documentation/devicetree/bindings/sound/fsl,ssi.txt
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@@ -1,87 +0,0 @@
Freescale Synchronous Serial Interface
The SSI is a serial device that communicates with audio codecs. It can
be programmed in AC97, I2S, left-justified, or right-justified modes.
Required properties:
- compatible: Compatible list, should contain one of the following
compatibles:
fsl,mpc8610-ssi
fsl,imx51-ssi
fsl,imx35-ssi
fsl,imx21-ssi
- cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
- reg: Offset and length of the register set for the device.
- interrupts: <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and
level information for the interrupt. This should be
encoded based on the information in section 2)
depending on the type of interrupt controller you
have.
- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
This number is the maximum allowed value for SFCSR[TFWM0].
- clocks: "ipg" - Required clock for the SSI unit
"baud" - Required clock for SSI master mode. Otherwise this
clock is not used
Required are also ac97 link bindings if ac97 is used. See
Documentation/devicetree/bindings/sound/soc-ac97link.txt for the necessary
bindings.
Optional properties:
- codec-handle: Phandle to a 'codec' node that defines an audio
codec connected to this SSI. This node is typically
a child of an I2C or other control node.
- fsl,fiq-stream-filter: Bool property. Disabled DMA and use FIQ instead to
filter the codec stream. This is necessary for some boards
where an incompatible codec is connected to this SSI, e.g.
on pca100 and pcm043.
- dmas: Generic dma devicetree binding as described in
Documentation/devicetree/bindings/dma/dma.txt.
- dma-names: Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq
is not defined.
- fsl,mode: The operating mode for the AC97 interface only.
"ac97-slave" - AC97 mode, SSI is clock slave
"ac97-master" - AC97 mode, SSI is clock master
- fsl,ssi-asynchronous:
If specified, the SSI is to be programmed in asynchronous
mode. In this mode, pins SRCK, STCK, SRFS, and STFS must
all be connected to valid signals. In synchronous mode,
SRCK and SRFS are ignored. Asynchronous mode allows
playback and capture to use different sample sizes and
sample rates. Some drivers may require that SRCK and STCK
be connected together, and SRFS and STFS be connected
together. This would still allow different sample sizes,
but not different sample rates.
- fsl,playback-dma: Phandle to a node for the DMA channel to use for
playback of audio. This is typically dictated by SOC
design. See the notes below.
Only used on Power Architecture.
- fsl,capture-dma: Phandle to a node for the DMA channel to use for
capture (recording) of audio. This is typically dictated
by SOC design. See the notes below.
Only used on Power Architecture.
Child 'codec' node required properties:
- compatible: Compatible list, contains the name of the codec
Child 'codec' node optional properties:
- clock-frequency: The frequency of the input clock, which typically comes
from an on-board dedicated oscillator.
Notes on fsl,playback-dma and fsl,capture-dma:
On SOCs that have an SSI, specific DMA channels are hard-wired for playback
and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
playback and DMA channel 3 for capture. The developer can choose which
DMA controller to use, but the channels themselves are hard-wired. The
purpose of these two properties is to represent this hardware design.
The device tree nodes for the DMA channels that are referenced by
"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
"fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
"fsl,mpc8610-dma-channel") can remain. If these nodes are left as
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
drivers (fsldma) will attempt to use them, and it will conflict with the
sound drivers.

194
Documentation/devicetree/bindings/sound/fsl,ssi.yaml Normal file
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@@ -0,0 +1,194 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/fsl,ssi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Synchronous Serial Interface
maintainers:
- Shengjiu Wang <shengjiu.wang@nxp.com>
description:
Notes on fsl,playback-dma and fsl,capture-dma
On SOCs that have an SSI, specific DMA channels are hard-wired for playback
and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
playback and DMA channel 3 for capture. The developer can choose which
DMA controller to use, but the channels themselves are hard-wired. The
purpose of these two properties is to represent this hardware design.
The device tree nodes for the DMA channels that are referenced by
"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
"fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
"fsl,mpc8610-dma-channel") can remain. If these nodes are left as
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
drivers (fsldma) will attempt to use them, and it will conflict with the
sound drivers.
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,imx50-ssi
- fsl,imx53-ssi
- const: fsl,imx51-ssi
- const: fsl,imx21-ssi
- items:
- enum:
- fsl,imx25-ssi
- fsl,imx27-ssi
- fsl,imx35-ssi
- fsl,imx51-ssi
- const: fsl,imx21-ssi
- items:
- enum:
- fsl,imx6q-ssi
- fsl,imx6sl-ssi
- fsl,imx6sx-ssi
- const: fsl,imx51-ssi
- items:
- const: fsl,imx21-ssi
- items:
- const: fsl,mpc8610-ssi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: The ipg clock for register access
- description: clock for SSI master mode
minItems: 1
clock-names:
items:
- const: ipg
- const: baud
minItems: 1
dmas:
oneOf:
- items:
- description: DMA controller phandle and request line for RX
- description: DMA controller phandle and request line for TX
- items:
- description: DMA controller phandle and request line for RX0
- description: DMA controller phandle and request line for TX0
- description: DMA controller phandle and request line for RX1
- description: DMA controller phandle and request line for TX1
dma-names:
oneOf:
- items:
- const: rx
- const: tx
- items:
- const: rx0
- const: tx0
- const: rx1
- const: tx1
"#sound-dai-cells":
const: 0
description: optional, some dts node didn't add it.
cell-index:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
description: The SSI index
ac97-gpios:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: Please refer to soc-ac97link.txt
codec-handle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to a 'codec' node that defines an audio
codec connected to this SSI. This node is typically
a child of an I2C or other control node.
fsl,fifo-depth:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The number of elements in the transmit and receive FIFOs.
This number is the maximum allowed value for SFCSR[TFWM0].
enum: [8, 15]
fsl,fiq-stream-filter:
type: boolean
description:
Disabled DMA and use FIQ instead to filter the codec stream.
This is necessary for some boards where an incompatible codec
is connected to this SSI, e.g. on pca100 and pcm043.
fsl,mode:
$ref: /schemas/types.yaml#/definitions/string
enum: [ ac97-slave, ac97-master, i2s-slave, i2s-master,
lj-slave, lj-master, rj-slave, rj-master ]
description: |
"ac97-slave" - AC97 mode, SSI is clock slave
"ac97-master" - AC97 mode, SSI is clock master
"i2s-slave" - I2S mode, SSI is clock slave
"i2s-master" - I2S mode, SSI is clock master
"lj-slave" - Left justified mode, SSI is clock slave
"lj-master" - Left justified mode, SSI is clock master
"rj-slave" - Right justified mode, SSI is clock slave
"rj-master" - Right justified mode, SSI is clock master
fsl,ssi-asynchronous:
type: boolean
description: If specified, the SSI is to be programmed in asynchronous
mode. In this mode, pins SRCK, STCK, SRFS, and STFS must
all be connected to valid signals. In synchronous mode,
SRCK and SRFS are ignored. Asynchronous mode allows
playback and capture to use different sample sizes and
sample rates. Some drivers may require that SRCK and STCK
be connected together, and SRFS and STFS be connected
together. This would still allow different sample sizes,
but not different sample rates.
fsl,playback-dma:
$ref: /schemas/types.yaml#/definitions/phandle
description: Phandle to a node for the DMA channel to use for
playback of audio. This is typically dictated by SOC
design. Only used on Power Architecture.
fsl,capture-dma:
$ref: /schemas/types.yaml#/definitions/phandle
description: Phandle to a node for the DMA channel to use for
capture (recording) of audio. This is typically dictated
by SOC design. Only used on Power Architecture.
required:
- compatible
- reg
- interrupts
- fsl,fifo-depth
allOf:
- $ref: dai-common.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imx6qdl-clock.h>
ssi@2028000 {
compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi";
reg = <0x02028000 0x4000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
<&clks IMX6QDL_CLK_SSI1>;
clock-names = "ipg", "baud";
dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
fsl,fifo-depth = <15>;
};

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