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Merge tag 'devicetree-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Browse Source 
Pull devicetree updates from Rob Herring:

 - Convert FPGA bridge, all TPMs (finally), and Rockchip HDMI bindings
   to schemas

 - Improvements in Samsung GPU schemas

 - A few more cases of dropping unneeded quotes in schemas

 - Merge QCom idle-states txt binding into common idle-states schema

 - Add X1E80100, SM8650, SM8650, and SDX75 SoCs to QCom Power Domain
   Controller

 - Add NXP i.mx8dl to SCU PD

 - Add synaptics r63353 panel controller

 - Clarify the wording around the use of 'wakeup-source' property

 - Add a DTS coding style doc

 - Add smi vendor prefix

 - Fix DT_SCHEMA_FILES incorrect matching of paths outside the kernel
   tree

 - Disable sysfb (e.g. EFI FB) when simple-framebuffer node is present

 - Fix double free in of_parse_phandle_with_args_map()

 - A couple of kerneldoc fixes

* tag 'devicetree-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (37 commits)
  of: unittest: Fix of_count_phandle_with_args() expected value message
  dt-bindings: fpga: altera: Convert bridge bindings to yaml
  dt-bindings: fpga: Convert bridge binding to yaml
  dt-bindings: vendor-prefixes: Add smi
  dt-bindings: power: Clarify wording for wakeup-source property
  of: Fix double free in of_parse_phandle_with_args_map
  dt-bindings: ignore paths outside kernel for DT_SCHEMA_FILES
  drivers: of: Fixed kernel doc warning
  dt-bindings: tpm: Document Microsoft fTPM bindings
  dt-bindings: tpm: Convert IBM vTPM bindings to DT schema
  dt-bindings: tpm: Convert Google Cr50 bindings to DT schema
  dt-bindings: tpm: Consolidate TCG TIS bindings
  dt-bindings: display: rockchip,inno-hdmi: Document RK3128 compatible
  dt-bindings: arm: Add remote etm dt-binding
  dt-bindings: mmc: sdhci-pxa: Fix 'regs' typo
  media: dt-bindings: samsung,s5p-mfc: Fix iommu properties schemas
  dt-bindings: display: panel: Add synaptics r63353 panel controller
  dt-bindings: arm: merge qcom,idle-state with idle-state
  dt-bindings: drm: rockchip: convert inno_hdmi-rockchip.txt to yaml
  dt-bindings: cache: qcom,llcc: correct QDU1000 reg entries
  ...
This commit is contained in:
Linus Torvalds
2024-01-12 15:05:30 -08:00
parent 42bff4d0f9 716089b417
commit 38814330fe
65 changed files with 1426 additions and 598 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/Makefile
View File

@@ -28,7 +28,7 @@ $(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
-name 'processed-schema*' \)
find_cmd = $(find_all_cmd) | grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))"
find_cmd = $(find_all_cmd) | sed 's|^$(srctree)/$(src)/||' | grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))" | sed 's|^|$(srctree)/$(src)/|'
CHK_DT_DOCS := $(shell $(find_cmd))
quiet_cmd_yamllint = LINT $(src)

2
Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml
View File

@@ -16,7 +16,7 @@ maintainers:
properties:
compatible:
const: "calxeda,hb-sregs-l2-ecc"
const: calxeda,hb-sregs-l2-ecc
reg:
maxItems: 1

84
Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
View File

@@ -1,84 +0,0 @@
QCOM Idle States for cpuidle driver
ARM provides idle-state node to define the cpuidle states, as defined in [1].
cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
states. Idle states have different enter/exit latency and residency values.
The idle states supported by the QCOM SoC are defined as -
* Standby
* Retention
* Standalone Power Collapse (Standalone PC or SPC)
* Power Collapse (PC)
Standby: Standby does a little more in addition to architectural clock gating.
When the WFI instruction is executed the ARM core would gate its internal
clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
trigger to execute the SPM state machine. The SPM state machine waits for the
interrupt to trigger the core back in to active. This triggers the cache
hierarchy to enter standby states, when all cpus are idle. An interrupt brings
the SPM state machine out of its wait, the next step is to ensure that the
cache hierarchy is also out of standby, and then the cpu is allowed to resume
execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
driver and is not defined in the DT. The SPM state machine should be
configured to execute this state by default and after executing every other
state below.
Retention: Retention is a low power state where the core is clock gated and
the memory and the registers associated with the core are retained. The
voltage may be reduced to the minimum value needed to keep the processor
registers active. The SPM should be configured to execute the retention
sequence and would wait for interrupt, before restoring the cpu to execution
state. Retention may have a slightly higher latency than Standby.
Standalone PC: A cpu can power down and warmboot if there is a sufficient time
between the time it enters idle and the next known wake up. SPC mode is used
to indicate a core entering a power down state without consulting any other
cpu or the system resources. This helps save power only on that core. The SPM
sequence for this idle state is programmed to power down the supply to the
core, wait for the interrupt, restore power to the core, and ensure the
system state including cache hierarchy is ready before allowing core to
resume. Applying power and resetting the core causes the core to warmboot
back into Elevation Level (EL) which trampolines the control back to the
kernel. Entering a power down state for the cpu, needs to be done by trapping
into a EL. Failing to do so, would result in a crash enforced by the warm boot
code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
be flushed in s/w, before powering down the core.
Power Collapse: This state is similar to the SPC mode, but distinguishes
itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
modes. In a hierarchical power domain SoC, this means L2 and other caches can
be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
voltages reduced, provided all cpus enter this state. Since the span of low
power modes possible at this state is vast, the exit latency and the residency
of this low power mode would be considered high even though at a cpu level,
this essentially is cpu power down. The SPM in this state also may handshake
with the Resource power manager (RPM) processor in the SoC to indicate a
complete application processor subsystem shut down.
The idle-state for QCOM SoCs are distinguished by the compatible property of
the idle-states device node.
The devicetree representation of the idle state should be -
Required properties:
- compatible: Must be one of -
"qcom,idle-state-ret",
"qcom,idle-state-spc",
"qcom,idle-state-pc",
and "arm,idle-state".
Other required and optional properties are specified in [1].
Example:
idle-states {
CPU_SPC: spc {
compatible = "qcom,idle-state-spc", "arm,idle-state";
entry-latency-us = <150>;
exit-latency-us = <200>;
min-residency-us = <2000>;
};
};
[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml

51
Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml Normal file
View File

@@ -0,0 +1,51 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/qcom,coresight-remote-etm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Coresight Remote ETM(Embedded Trace Macrocell)
maintainers:
- Jinlong Mao <quic_jinlmao@quicinc.com>
- Tao Zhang <quic_taozha@quicinc.com>
description:
Support for ETM trace collection on remote processor using coresight
framework. Enabling this will allow turning on ETM tracing on remote
processor like modem processor via sysfs and collecting the trace
via coresight TMC sinks.
properties:
compatible:
const: qcom,coresight-remote-etm
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- out-ports
additionalProperties: false
examples:
- |
etm {
compatible = "qcom,coresight-remote-etm";
out-ports {
port {
modem_etm0_out_funnel_modem: endpoint {
remote-endpoint = <&funnel_modem_in_modem_etm0>;
};
};
};
};
...

2
Documentation/devicetree/bindings/auxdisplay/hit,hd44780.yaml
View File

@@ -113,7 +113,7 @@ examples:
hd44780 {
compatible = "hit,hd44780";
display-height-chars = <2>;
display-width-chars = <16>;
display-width-chars = <16>;
data-gpios = <&pcf8574 4 0>,
<&pcf8574 5 0>,
<&pcf8574 6 0>,

2
Documentation/devicetree/bindings/cache/qcom,llcc.yaml vendored
View File

@@ -66,6 +66,7 @@ allOf:
compatible:
contains:
enum:
- qcom,qdu1000-llcc
- qcom,sc7180-llcc
- qcom,sm6350-llcc
then:
@@ -103,7 +104,6 @@ allOf:
compatible:
contains:
enum:
- qcom,qdu1000-llcc
- qcom,sc8180x-llcc
- qcom,sc8280xp-llcc
- qcom,x1e80100-llcc

2
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
View File

@@ -125,7 +125,7 @@ examples:
clk25m: clock-oscillator-25m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-frequency = <25000000>;
clock-output-names = "clk25m";
};
...

81
Documentation/devicetree/bindings/cpu/idle-states.yaml
View File

@@ -243,7 +243,64 @@ description: |+
just supports idle_standby, an idle-states node is not required.
===========================================
6 - References
6 - Qualcomm specific STATES
===========================================
Idle states have different enter/exit latency and residency values.
The idle states supported by the QCOM SoC are defined as -
* Standby
* Retention
* Standalone Power Collapse (Standalone PC or SPC)
* Power Collapse (PC)
Standby: Standby does a little more in addition to architectural clock gating.
When the WFI instruction is executed the ARM core would gate its internal
clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
trigger to execute the SPM state machine. The SPM state machine waits for the
interrupt to trigger the core back in to active. This triggers the cache
hierarchy to enter standby states, when all cpus are idle. An interrupt brings
the SPM state machine out of its wait, the next step is to ensure that the
cache hierarchy is also out of standby, and then the cpu is allowed to resume
execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
driver and is not defined in the DT. The SPM state machine should be
configured to execute this state by default and after executing every other
state below.
Retention: Retention is a low power state where the core is clock gated and
the memory and the registers associated with the core are retained. The
voltage may be reduced to the minimum value needed to keep the processor
registers active. The SPM should be configured to execute the retention
sequence and would wait for interrupt, before restoring the cpu to execution
state. Retention may have a slightly higher latency than Standby.
Standalone PC: A cpu can power down and warmboot if there is a sufficient time
between the time it enters idle and the next known wake up. SPC mode is used
to indicate a core entering a power down state without consulting any other
cpu or the system resources. This helps save power only on that core. The SPM
sequence for this idle state is programmed to power down the supply to the
core, wait for the interrupt, restore power to the core, and ensure the
system state including cache hierarchy is ready before allowing core to
resume. Applying power and resetting the core causes the core to warmboot
back into Elevation Level (EL) which trampolines the control back to the
kernel. Entering a power down state for the cpu, needs to be done by trapping
into a EL. Failing to do so, would result in a crash enforced by the warm boot
code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
be flushed in s/w, before powering down the core.
Power Collapse: This state is similar to the SPC mode, but distinguishes
itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
modes. In a hierarchical power domain SoC, this means L2 and other caches can
be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
voltages reduced, provided all cpus enter this state. Since the span of low
power modes possible at this state is vast, the exit latency and the residency
of this low power mode would be considered high even though at a cpu level,
this essentially is cpu power down. The SPM in this state also may handshake
with the Resource power manager (RPM) processor in the SoC to indicate a
complete application processor subsystem shut down.
===========================================
7 - References
===========================================
[1] ARM Linux Kernel documentation - CPUs bindings
@@ -301,9 +358,16 @@ patternProperties:
properties:
compatible:
enum:
- arm,idle-state
- riscv,idle-state
oneOf:
- items:
- enum:
- qcom,idle-state-ret
- qcom,idle-state-spc
- qcom,idle-state-pc
- const: arm,idle-state
- enum:
- arm,idle-state
- riscv,idle-state
arm,psci-suspend-param:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -852,4 +916,13 @@ examples:
};
};
// Example 4 - Qualcomm SPC
idle-states {
cpu_spc: cpu-spc {
compatible = "qcom,idle-state-spc", "arm,idle-state";
entry-latency-us = <150>;
exit-latency-us = <200>;
min-residency-us = <2000>;
};
};
...

61
Documentation/devicetree/bindings/display/panel/synaptics,r63353.yaml Normal file
View File

@@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/synaptics,r63353.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synaptics R63353 based MIPI-DSI panels
maintainers:
- Michael Trimarchi <michael@amarulasolutions.com>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
items:
- enum:
- sharp,ls068b3sx02
- const: syna,r63353
avdd-supply: true
dvdd-supply: true
reg: true
required:
- compatible
- avdd-supply
- dvdd-supply
- reg
- reset-gpios
- port
- backlight
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "sharp,ls068b3sx02", "syna,r63353";
reg = <0>;
avdd-supply = <&avdd_display>;
dvdd-supply = <&dvdd_display>;
reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
};
};
...

49
Documentation/devicetree/bindings/display/rockchip/inno_hdmi-rockchip.txt
View File

@@ -1,49 +0,0 @@
Rockchip specific extensions to the Innosilicon HDMI
================================
Required properties:
- compatible:
"rockchip,rk3036-inno-hdmi";
- reg:
Physical base address and length of the controller's registers.
- clocks, clock-names:
Phandle to hdmi controller clock, name should be "pclk"
- interrupts:
HDMI interrupt number
- ports:
Contain one port node with endpoint definitions as defined in
Documentation/devicetree/bindings/graph.txt.
- pinctrl-0, pinctrl-name:
Switch the iomux of HPD/CEC pins to HDMI function.
Example:
hdmi: hdmi@20034000 {
compatible = "rockchip,rk3036-inno-hdmi";
reg = <0x20034000 0x4000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI>;
clock-names = "pclk";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_ctl>;
hdmi_in: port {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in_lcdc: endpoint@0 {
reg = <0>;
remote-endpoint = <&lcdc_out_hdmi>;
};
};
};
&pinctrl {
hdmi {
hdmi_ctl: hdmi-ctl {
rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
<1 9 RK_FUNC_1 &pcfg_pull_none>,
<1 10 RK_FUNC_1 &pcfg_pull_none>,
<1 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
};

139
Documentation/devicetree/bindings/display/rockchip/rockchip,inno-hdmi.yaml Normal file
View File

@@ -0,0 +1,139 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/rockchip/rockchip,inno-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip Innosilicon HDMI controller
maintainers:
- Sandy Huang <hjc@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
enum:
- rockchip,rk3036-inno-hdmi
- rockchip,rk3128-inno-hdmi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
items:
- description: The HDMI controller main clock
- description: The HDMI PHY reference clock
clock-names:
minItems: 1
items:
- const: pclk
- const: ref
power-domains:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Port node with one endpoint connected to a vop node.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
Port node with one endpoint connected to a hdmi-connector node.
required:
- port@0
- port@1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- pinctrl-0
- pinctrl-names
- ports
allOf:
- if:
properties:
compatible:
contains:
const: rockchip,rk3036-inno-hdmi
then:
properties:
power-domains: false
- if:
properties:
compatible:
contains:
const: rockchip,rk3128-inno-hdmi
then:
properties:
clocks:
minItems: 2
clock-names:
minItems: 2
required:
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rk3036-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
hdmi: hdmi@20034000 {
compatible = "rockchip,rk3036-inno-hdmi";
reg = <0x20034000 0x4000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI>;
clock-names = "pclk";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_ctl>;
ports {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in: port@0 {
reg = <0>;
hdmi_in_vop: endpoint {
remote-endpoint = <&vop_out_hdmi>;
};
};
hdmi_out: port@1 {
reg = <1>;
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
};
};
pinctrl {
hdmi {
hdmi_ctl: hdmi-ctl {
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
<1 RK_PB1 1 &pcfg_pull_none>,
<1 RK_PB2 1 &pcfg_pull_none>,
<1 RK_PB3 1 &pcfg_pull_none>;
};
};
};

196
Documentation/devicetree/bindings/dts-coding-style.rst Normal file
View File

@@ -0,0 +1,196 @@
.. SPDX-License-Identifier: GPL-2.0
=====================================
Devicetree Sources (DTS) Coding Style
=====================================
When writing Devicetree Sources (DTS) please observe below guidelines. They
should be considered complementary to any rules expressed already in
the Devicetree Specification and the dtc compiler (including W=1 and W=2
builds).
Individual architectures and subarchitectures can define additional rules,
making the coding style stricter.
Naming and Valid Characters
---------------------------
The Devicetree Specification allows a broad range of characters in node
and property names, but this coding style narrows the range down to achieve
better code readability.
1. Node and property names can use only the following characters:
* Lowercase characters: [a-z]
* Digits: [0-9]
* Dash: -
2. Labels can use only the following characters:
* Lowercase characters: [a-z]
* Digits: [0-9]
* Underscore: _
3. Unless a bus defines differently, unit addresses shall use lowercase
hexadecimal digits, without leading zeros (padding).
4. Hex values in properties, e.g. "reg", shall use lowercase hex. The address
part can be padded with leading zeros.
Example::
gpi_dma2: dma-controller@a00000 {
compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00a00000 0x0 0x60000>;
}
Order of Nodes
--------------
1. Nodes on any bus, thus using unit addresses for children, shall be
ordered by unit address in ascending order.
Alternatively for some subarchitectures, nodes of the same type can be
grouped together, e.g. all I2C controllers one after another even if this
breaks unit address ordering.
2. Nodes without unit addresses shall be ordered alpha-numerically by the node
name. For a few node types, they can be ordered by the main property, e.g.
pin configuration states ordered by value of "pins" property.
3. When extending nodes in the board DTS via &label, the entries shall be
ordered either alpha-numerically or by keeping the order from DTSI, where
the choice depends on the subarchitecture.
The above-described ordering rules are easy to enforce during review, reduce
chances of conflicts for simultaneous additions of new nodes to a file and help
in navigating through the DTS source.
Example::
/* SoC DTSI */
/ {
cpus {
/* ... */
};
psci {
/* ... */
};
soc@0 {
dma: dma-controller@10000 {
/* ... */
};
clk: clock-controller@80000 {
/* ... */
};
};
};
/* Board DTS - alphabetical order */
&clk {
/* ... */
};
&dma {
/* ... */
};
/* Board DTS - alternative order, keep as DTSI */
&dma {
/* ... */
};
&clk {
/* ... */
};
Order of Properties in Device Node
----------------------------------
The following order of properties in device nodes is preferred:
1. "compatible"
2. "reg"
3. "ranges"
4. Standard/common properties (defined by common bindings, e.g. without
vendor-prefixes)
5. Vendor-specific properties
6. "status" (if applicable)
7. Child nodes, where each node is preceded with a blank line
The "status" property is by default "okay", thus it can be omitted.
The above-described ordering follows this approach:
1. Most important properties start the node: compatible then bus addressing to
match unit address.
2. Each node will have common properties in similar place.
3. Status is the last information to annotate that device node is or is not
finished (board resources are needed).
Example::
/* SoC DTSI */
device_node: device-class@6789abc {
compatible = "vendor,device";
reg = <0x0 0x06789abc 0x0 0xa123>;
ranges = <0x0 0x0 0x06789abc 0x1000>;
#dma-cells = <1>;
clocks = <&clock_controller 0>, <&clock_controller 1>;
clock-names = "bus", "host";
vendor,custom-property = <2>;
status = "disabled";
child_node: child-class@100 {
reg = <0x100 0x200>;
/* ... */
};
};
/* Board DTS */
&device_node {
vdd-supply = <&board_vreg1>;
status = "okay";
}
Indentation
-----------
1. Use indentation according to Documentation/process/coding-style.rst.
2. Each entry in arrays with multiple cells, e.g. "reg" with two IO addresses,
shall be enclosed in <>.
3. For arrays spanning across lines, it is preferred to align the continued
entries with opening < from the first line.
Example::
thermal-sensor@c271000 {
compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
reg = <0x0 0x0c271000 0x0 0x1000>,
<0x0 0x0c222000 0x0 0x1000>;
};
Organizing DTSI and DTS
-----------------------
The DTSI and DTS files shall be organized in a way representing the common,
reusable parts of hardware. Typically, this means organizing DTSI and DTS files
into several files:
1. DTSI with contents of the entire SoC, without nodes for hardware not present
on the SoC.
2. If applicable: DTSI with common or re-usable parts of the hardware, e.g.
entire System-on-Module.
3. DTS representing the board.
Hardware components that are present on the board shall be placed in the
board DTS, not in the SoC or SoM DTSI. A partial exception is a common
external reference SoC input clock, which could be coded as a fixed-clock in
the SoC DTSI with its frequency provided by each board DTS.

13
Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
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@@ -1,13 +0,0 @@
Altera FPGA To SDRAM Bridge Driver
Required properties:
- compatible : Should contain "altr,socfpga-fpga2sdram-bridge"
See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
Example:
fpga_bridge3: fpga-bridge@ffc25080 {
compatible = "altr,socfpga-fpga2sdram-bridge";
reg = <0xffc25080 0x4>;
bridge-enable = <0>;
};

20
Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
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Altera Freeze Bridge Controller Driver
The Altera Freeze Bridge Controller manages one or more freeze bridges.
The controller can freeze/disable the bridges which prevents signal
changes from passing through the bridge. The controller can also
unfreeze/enable the bridges which allows traffic to pass through the
bridge normally.
Required properties:
- compatible : Should contain "altr,freeze-bridge-controller"
- regs : base address and size for freeze bridge module
See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
Example:
freeze-controller@100000450 {
compatible = "altr,freeze-bridge-controller";
regs = <0x1000 0x10>;
bridge-enable = <0>;
};

36
Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
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Altera FPGA/HPS Bridge Driver
Required properties:
- regs : base address and size for AXI bridge module
- compatible : Should contain one of:
"altr,socfpga-lwhps2fpga-bridge",
"altr,socfpga-hps2fpga-bridge", or
"altr,socfpga-fpga2hps-bridge"
- resets : Phandle and reset specifier for this bridge's reset
- clocks : Clocks used by this module.
See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
Example:
fpga_bridge0: fpga-bridge@ff400000 {
compatible = "altr,socfpga-lwhps2fpga-bridge";
reg = <0xff400000 0x100000>;
resets = <&rst LWHPS2FPGA_RESET>;
clocks = <&l4_main_clk>;
bridge-enable = <0>;
};
fpga_bridge1: fpga-bridge@ff500000 {
compatible = "altr,socfpga-hps2fpga-bridge";
reg = <0xff500000 0x10000>;
resets = <&rst HPS2FPGA_RESET>;
clocks = <&l4_main_clk>;
bridge-enable = <1>;
};
fpga_bridge2: fpga-bridge@ff600000 {
compatible = "altr,socfpga-fpga2hps-bridge";
reg = <0xff600000 0x100000>;
resets = <&rst FPGA2HPS_RESET>;
clocks = <&l4_main_clk>;
};

41
Documentation/devicetree/bindings/fpga/altr,freeze-bridge-controller.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/altr,freeze-bridge-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera Freeze Bridge Controller
description:
The Altera Freeze Bridge Controller manages one or more freeze bridges.
The controller can freeze/disable the bridges which prevents signal
changes from passing through the bridge. The controller can also
unfreeze/enable the bridges which allows traffic to pass through the bridge
normally.
maintainers:
- Xu Yilun <yilun.xu@intel.com>
allOf:
- $ref: fpga-bridge.yaml#
properties:
compatible:
const: altr,freeze-bridge-controller
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
fpga-bridge@100000450 {
compatible = "altr,freeze-bridge-controller";
reg = <0x1000 0x10>;
bridge-enable = <0>;
};

33
Documentation/devicetree/bindings/fpga/altr,socfpga-fpga2sdram-bridge.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/altr,socfpga-fpga2sdram-bridge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera FPGA To SDRAM Bridge
maintainers:
- Xu Yilun <yilun.xu@intel.com>
allOf:
- $ref: fpga-bridge.yaml#
properties:
compatible:
const: altr,socfpga-fpga2sdram-bridge
reg:
maxItems: 1
required:
- compatible
unevaluatedProperties: false
examples:
- |
fpga-bridge@ffc25080 {
compatible = "altr,socfpga-fpga2sdram-bridge";
reg = <0xffc25080 0x4>;
bridge-enable = <0>;
};

49
Documentation/devicetree/bindings/fpga/altr,socfpga-hps2fpga-bridge.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera FPGA/HPS Bridge
maintainers:
- Xu Yilun <yilun.xu@intel.com>
allOf:
- $ref: fpga-bridge.yaml#
properties:
compatible:
enum:
- altr,socfpga-lwhps2fpga-bridge
- altr,socfpga-hps2fpga-bridge
- altr,socfpga-fpga2hps-bridge
reg:
maxItems: 1
resets:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- clocks
- resets
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/reset/altr,rst-mgr.h>
fpga-bridge@ff400000 {
compatible = "altr,socfpga-lwhps2fpga-bridge";
reg = <0xff400000 0x100000>;
bridge-enable = <0>;
clocks = <&l4_main_clk>;
resets = <&rst LWHPS2FPGA_RESET>;
};

13
Documentation/devicetree/bindings/fpga/fpga-bridge.txt
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FPGA Bridge Device Tree Binding
Optional properties:
- bridge-enable : 0 if driver should disable bridge at startup
1 if driver should enable bridge at startup
Default is to leave bridge in current state.
Example:
fpga_bridge3: fpga-bridge@ffc25080 {
compatible = "altr,socfpga-fpga2sdram-bridge";
reg = <0xffc25080 0x4>;
bridge-enable = <0>;
};

30
Documentation/devicetree/bindings/fpga/fpga-bridge.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: FPGA Bridge
maintainers:
- Michal Simek <michal.simek@amd.com>
properties:
$nodename:
pattern: "^fpga-bridge(@.*|-([0-9]|[1-9][0-9]+))?$"
bridge-enable:
description: |
0 if driver should disable bridge at startup
1 if driver should enable bridge at startup
Default is to leave bridge in current state.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1 ]
additionalProperties: true
examples:
- |
fpga-bridge {
bridge-enable = <0>;
};

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