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Merge tag 's3c24xx-dma' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

Browse Source 
From Kukjin Kim, this branch adds device-tree support to the DMA controller
on the older Samsung SoCs. It also adds support for one of the missing SoCs
in the family (2410).

The driver has been Ack:ed by Vinod Koul, but is merged through here due
to dependencies with platform code.

* tag 's3c24xx-dma' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: S3C24XX: add dma pdata for s3c2410, s3c2440 and s3c2442
  dmaengine: s3c24xx-dma: add support for the s3c2410 type of controller
  ARM: S3C24XX: Fix possible dma selection warning
  ARM: SAMSUNG: set s3c24xx_dma_filter for s3c64xx-spi0 device
  ARM: S3C24XX: add platform-devices for new dma driver for s3c2412 and s3c2443
  dmaengine: add driver for Samsung s3c24xx SoCs
  ARM: S3C24XX: number the dma clocks
  + Linux 3.12-rc3

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2013-10-27 21:42:44 -07:00
parent f2c4e82e35 1fecf8958e
commit 3316dee245
246 changed files with 3994 additions and 1263 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
CREDITS
View File

@@ -2808,8 +2808,7 @@ S: Ottawa, Ontario
S: Canada K2P 0X8
N: Mikael Pettersson
E: mikpe@it.uu.se
W: http://user.it.uu.se/~mikpe/linux/
E: mikpelinux@gmail.com
D: Miscellaneous fixes
N: Reed H. Petty

10
Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
View File

@@ -1,11 +1,11 @@
* Samsung Exynos specific extensions to the Synopsis Designware Mobile
* Samsung Exynos specific extensions to the Synopsys Designware Mobile
Storage Host Controller
The Synopsis designware mobile storage host controller is used to interface
The Synopsys designware mobile storage host controller is used to interface
a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
differences between the core Synopsis dw mshc controller properties described
by synopsis-dw-mshc.txt and the properties used by the Samsung Exynos specific
extensions to the Synopsis Designware Mobile Storage Host Controller.
differences between the core Synopsys dw mshc controller properties described
by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
extensions to the Synopsys Designware Mobile Storage Host Controller.
Required Properties:

10
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
View File

@@ -1,11 +1,11 @@
* Rockchip specific extensions to the Synopsis Designware Mobile
* Rockchip specific extensions to the Synopsys Designware Mobile
Storage Host Controller
The Synopsis designware mobile storage host controller is used to interface
The Synopsys designware mobile storage host controller is used to interface
a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
differences between the core Synopsis dw mshc controller properties described
by synopsis-dw-mshc.txt and the properties used by the Rockchip specific
extensions to the Synopsis Designware Mobile Storage Host Controller.
differences between the core Synopsys dw mshc controller properties described
by synopsys-dw-mshc.txt and the properties used by the Rockchip specific
extensions to the Synopsys Designware Mobile Storage Host Controller.
Required Properties:

8
Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt → Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
View File

@@ -1,14 +1,14 @@
* Synopsis Designware Mobile Storage Host Controller
* Synopsys Designware Mobile Storage Host Controller
The Synopsis designware mobile storage host controller is used to interface
The Synopsys designware mobile storage host controller is used to interface
a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
differences between the core mmc properties described by mmc.txt and the
properties used by the Synopsis Designware Mobile Storage Host Controller.
properties used by the Synopsys Designware Mobile Storage Host Controller.
Required Properties:
* compatible: should be
- snps,dw-mshc: for controllers compliant with synopsis dw-mshc.
- snps,dw-mshc: for controllers compliant with synopsys dw-mshc.
* #address-cells: should be 1.
* #size-cells: should be 0.

2
Documentation/devicetree/bindings/pci/designware-pcie.txt
View File

@@ -1,4 +1,4 @@
* Synopsis Designware PCIe interface
* Synopsys Designware PCIe interface
Required properties:
- compatible: should contain "snps,dw-pcie" to identify the

0
Documentation/devicetree/bindings/tty/serial/qca,ar9330-uart.txt → Documentation/devicetree/bindings/serial/qca,ar9330-uart.txt
View File

4
Documentation/kernel-parameters.txt
View File

@@ -3485,6 +3485,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
the unplug protocol
never -- do not unplug even if version check succeeds
xen_nopvspin [X86,XEN]
Disables the ticketlock slowpath using Xen PV
optimizations.
xirc2ps_cs= [NET,PCMCIA]
Format:
<irq>,<irq_mask>,<io>,<full_duplex>,<do_sound>,<lockup_hack>[,<irq2>[,<irq3>[,<irq4>]]]

6
Documentation/sound/alsa/HD-Audio-Models.txt
View File

@@ -296,6 +296,12 @@ Cirrus Logic CS4206/4207
imac27 IMac 27 Inch
auto BIOS setup (default)
Cirrus Logic CS4208
===================
mba6 MacBook Air 6,1 and 6,2
gpio0 Enable GPIO 0 amp
auto BIOS setup (default)
VIA VT17xx/VT18xx/VT20xx
========================
auto BIOS setup (default)

20
MAINTAINERS
View File

@@ -1812,7 +1812,8 @@ S: Supported
F: drivers/net/ethernet/broadcom/bnx2x/
BROADCOM BCM281XX/BCM11XXX ARM ARCHITECTURE
M: Christian Daudt <csd@broadcom.com>
M: Christian Daudt <bcm@fixthebug.org>
L: bcm-kernel-feedback-list@broadcom.com
T: git git://git.github.com/broadcom/bcm11351
S: Maintained
F: arch/arm/mach-bcm/
@@ -2639,6 +2640,18 @@ F: include/linux/device-mapper.h
F: include/linux/dm-*.h
F: include/uapi/linux/dm-*.h
DIGI NEO AND CLASSIC PCI PRODUCTS
M: Lidza Louina <lidza.louina@gmail.com>
L: driverdev-devel@linuxdriverproject.org
S: Maintained
F: drivers/staging/dgnc/
DIGI EPCA PCI PRODUCTS
M: Lidza Louina <lidza.louina@gmail.com>
L: driverdev-devel@linuxdriverproject.org
S: Maintained
F: drivers/staging/dgap/
DIOLAN U2C-12 I2C DRIVER
M: Guenter Roeck <linux@roeck-us.net>
L: linux-i2c@vger.kernel.org
@@ -6595,7 +6608,7 @@ S: Obsolete
F: drivers/net/wireless/prism54/
PROMISE SATA TX2/TX4 CONTROLLER LIBATA DRIVER
M: Mikael Pettersson <mikpe@it.uu.se>
M: Mikael Pettersson <mikpelinux@gmail.com>
L: linux-ide@vger.kernel.org
S: Maintained
F: drivers/ata/sata_promise.*
@@ -8724,9 +8737,8 @@ F: Documentation/hid/hiddev.txt
F: drivers/hid/usbhid/
USB/IP DRIVERS
M: Matt Mooney <mfm@muteddisk.com>
L: linux-usb@vger.kernel.org
S: Maintained
S: Orphan
F: drivers/staging/usbip/
USB ISP116X DRIVER

2
Makefile
View File

@@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 12
SUBLEVEL = 0
EXTRAVERSION = -rc2
EXTRAVERSION = -rc3
NAME = One Giant Leap for Frogkind
# *DOCUMENTATION*

3
arch/Kconfig
View File

@@ -286,9 +286,6 @@ config HAVE_PERF_USER_STACK_DUMP
config HAVE_ARCH_JUMP_LABEL
bool
config HAVE_ARCH_MUTEX_CPU_RELAX
bool
config HAVE_RCU_TABLE_FREE
bool

3
arch/arm/Kconfig
View File

@@ -2216,8 +2216,7 @@ config NEON
config KERNEL_MODE_NEON
bool "Support for NEON in kernel mode"
default n
depends on NEON
depends on NEON && AEABI
help
Say Y to include support for NEON in kernel mode.

6
arch/arm/crypto/aes-armv4.S
View File

@@ -148,7 +148,7 @@ AES_Te:
@ const AES_KEY *key) {
.align 5
ENTRY(AES_encrypt)
sub r3,pc,#8 @ AES_encrypt
adr r3,AES_encrypt
stmdb sp!,{r1,r4-r12,lr}
mov r12,r0 @ inp
mov r11,r2
@@ -381,7 +381,7 @@ _armv4_AES_encrypt:
.align 5
ENTRY(private_AES_set_encrypt_key)
_armv4_AES_set_encrypt_key:
sub r3,pc,#8 @ AES_set_encrypt_key
adr r3,_armv4_AES_set_encrypt_key
teq r0,#0
moveq r0,#-1
beq .Labrt
@@ -843,7 +843,7 @@ AES_Td:
@ const AES_KEY *key) {
.align 5
ENTRY(AES_decrypt)
sub r3,pc,#8 @ AES_decrypt
adr r3,AES_decrypt
stmdb sp!,{r1,r4-r12,lr}
mov r12,r0 @ inp
mov r11,r2

7
arch/arm/include/asm/uaccess.h
View File

@@ -19,6 +19,13 @@
#include <asm/unified.h>
#include <asm/compiler.h>
#if __LINUX_ARM_ARCH__ < 6
#include <asm-generic/uaccess-unaligned.h>
#else
#define __get_user_unaligned __get_user
#define __put_user_unaligned __put_user
#endif
#define VERIFY_READ 0
#define VERIFY_WRITE 1

4
arch/arm/kernel/entry-common.S
View File

@@ -442,10 +442,10 @@ local_restart:
ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine
add r1, sp, #S_OFF
cmp scno, #(__ARM_NR_BASE - __NR_SYSCALL_BASE)
2: cmp scno, #(__ARM_NR_BASE - __NR_SYSCALL_BASE)
eor r0, scno, #__NR_SYSCALL_BASE @ put OS number back
bcs arm_syscall
2: mov why, #0 @ no longer a real syscall
mov why, #0 @ no longer a real syscall
b sys_ni_syscall @ not private func
#if defined(CONFIG_OABI_COMPAT) || !defined(CONFIG_AEABI)

8
arch/arm/kernel/entry-header.S
View File

@@ -329,10 +329,10 @@
#ifdef CONFIG_CONTEXT_TRACKING
.if \save
stmdb sp!, {r0-r3, ip, lr}
bl user_exit
bl context_tracking_user_exit
ldmia sp!, {r0-r3, ip, lr}
.else
bl user_exit
bl context_tracking_user_exit
.endif
#endif
.endm
@@ -341,10 +341,10 @@
#ifdef CONFIG_CONTEXT_TRACKING
.if \save
stmdb sp!, {r0-r3, ip, lr}
bl user_enter
bl context_tracking_user_enter
ldmia sp!, {r0-r3, ip, lr}
.else
bl user_enter
bl context_tracking_user_enter
.endif
#endif
.endm

3
arch/arm/mach-s3c24xx/Kconfig
View File

@@ -28,6 +28,7 @@ config CPU_S3C2410
select CPU_ARM920T
select CPU_LLSERIAL_S3C2410
select S3C2410_CLOCK
select S3C2410_DMA if S3C24XX_DMA
select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
select S3C2410_PM if PM
select SAMSUNG_WDT_RESET
@@ -70,6 +71,7 @@ config CPU_S3C2442
select CPU_ARM920T
select CPU_LLSERIAL_S3C2440
select S3C2410_CLOCK
select S3C2410_DMA if S3C24XX_DMA
select S3C2410_PM if PM
help
Support for S3C2442 Samsung Mobile CPU based systems.
@@ -148,7 +150,6 @@ config S3C2410_DMA_DEBUG
config S3C2410_DMA
bool
depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
default y if CPU_S3C2410 || CPU_S3C2442
help
DMA device selection for S3C2410 and compatible CPUs

8
arch/arm/mach-s3c24xx/clock-s3c2412.c
View File

@@ -484,22 +484,22 @@ static struct clk init_clocks_disable[] = {
static struct clk init_clocks[] = {
{
.name = "dma",
.name = "dma.0",
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA0,
}, {
.name = "dma",
.name = "dma.1",
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA1,
}, {
.name = "dma",
.name = "dma.2",
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA2,
}, {
.name = "dma",
.name = "dma.3",
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA3,

12
arch/arm/mach-s3c24xx/common-s3c2443.c
View File

@@ -438,32 +438,32 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "dma",
.name = "dma.0",
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA0,
}, {
.name = "dma",
.name = "dma.1",
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA1,
}, {
.name = "dma",
.name = "dma.2",
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA2,
}, {
.name = "dma",
.name = "dma.3",
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA3,
}, {
.name = "dma",
.name = "dma.4",
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA4,
}, {
.name = "dma",
.name = "dma.5",
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA5,

206
arch/arm/mach-s3c24xx/common.c
View File

@@ -31,6 +31,7 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/platform_data/dma-s3c24xx.h>
#include <mach/hardware.h>
#include <mach/regs-clock.h>
@@ -44,6 +45,7 @@
#include <mach/regs-gpio.h>
#include <plat/regs-serial.h>
#include <mach/dma.h>
#include <plat/cpu.h>
#include <plat/devs.h>
@@ -329,3 +331,207 @@ void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
clk_p.rate = pclk;
clk_f.rate = fclk;
}
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
static struct resource s3c2410_dma_resource[] = {
[0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
[1] = DEFINE_RES_IRQ(IRQ_DMA0),
[2] = DEFINE_RES_IRQ(IRQ_DMA1),
[3] = DEFINE_RES_IRQ(IRQ_DMA2),
[4] = DEFINE_RES_IRQ(IRQ_DMA3),
};
#endif
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
[DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
[DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
[DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
S3C24XX_DMA_CHANREQ(2, 2) |
S3C24XX_DMA_CHANREQ(1, 3),
},
[DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
[DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
[DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
[DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
[DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
[DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
S3C24XX_DMA_CHANREQ(3, 2) |
S3C24XX_DMA_CHANREQ(3, 3),
},
[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
S3C24XX_DMA_CHANREQ(1, 2),
},
[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
[DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
[DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
[DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
};
static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
.num_phy_channels = 4,
.channels = s3c2410_dma_channels,
.num_channels = DMACH_MAX,
};
struct platform_device s3c2410_device_dma = {
.name = "s3c2410-dma",
.id = 0,
.num_resources = ARRAY_SIZE(s3c2410_dma_resource),
.resource = s3c2410_dma_resource,
.dev = {
.platform_data = &s3c2410_dma_platdata,
},
};
#endif
#ifdef CONFIG_CPU_S3C2412
static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
[DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
[DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
[DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
[DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
[DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
[DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
[DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
[DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
[DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
[DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
[DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
[DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
[DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
[DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
[DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
[DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
[DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
};
static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
.num_phy_channels = 4,
.channels = s3c2412_dma_channels,
.num_channels = DMACH_MAX,
};
struct platform_device s3c2412_device_dma = {
.name = "s3c2412-dma",
.id = 0,
.num_resources = ARRAY_SIZE(s3c2410_dma_resource),
.resource = s3c2410_dma_resource,
.dev = {
.platform_data = &s3c2412_dma_platdata,
},
};
#endif
#if defined(CONFIG_CPU_S3C2440)
static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
[DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
[DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
[DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
S3C24XX_DMA_CHANREQ(6, 1) |
S3C24XX_DMA_CHANREQ(2, 2) |
S3C24XX_DMA_CHANREQ(1, 3),
},
[DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
[DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
[DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
[DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
[DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
[DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
S3C24XX_DMA_CHANREQ(3, 2) |
S3C24XX_DMA_CHANREQ(3, 3),
},
[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
S3C24XX_DMA_CHANREQ(1, 2),
},
[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
S3C24XX_DMA_CHANREQ(0, 2),
},
[DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
S3C24XX_DMA_CHANREQ(5, 2),
},
[DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
S3C24XX_DMA_CHANREQ(6, 3),
},
[DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
S3C24XX_DMA_CHANREQ(5, 3),
},
[DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
[DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
[DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
};
static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
.num_phy_channels = 4,
.channels = s3c2440_dma_channels,
.num_channels = DMACH_MAX,
};
struct platform_device s3c2440_device_dma = {
.name = "s3c2410-dma",
.id = 0,
.num_resources = ARRAY_SIZE(s3c2410_dma_resource),
.resource = s3c2410_dma_resource,
.dev = {
.platform_data = &s3c2440_dma_platdata,
},
};
#endif
#if defined(CONFIG_CPUS_3C2443) || defined(CONFIG_CPU_S3C2416)
static struct resource s3c2443_dma_resource[] = {
[0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
[1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
[2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
[3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
[4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
[5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
[6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
};
static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
[DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
[DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
[DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
[DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
[DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
[DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
[DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
[DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
[DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
[DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
[DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
[DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
[DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
[DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
[DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
[DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
[DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
[DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 },
[DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
};
static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
.num_phy_channels = 6,
.channels = s3c2443_dma_channels,
.num_channels = DMACH_MAX,
};
struct platform_device s3c2443_device_dma = {
.name = "s3c2443-dma",
.id = 0,
.num_resources = ARRAY_SIZE(s3c2443_dma_resource),
.resource = s3c2443_dma_resource,
.dev = {
.platform_data = &s3c2443_dma_platdata,
},
};
#endif

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