mirror of
https://github.com/Dasharo/linux.git
synced 2026-03-06 15:25:10 -08:00
Merge tag 'drm-next-2023-11-07' of git://anongit.freedesktop.org/drm/drm
Pull more drm updates from Dave Airlie: "Geert pointed out I missed the renesas reworks in my main pull, so this pull contains the renesas next work for atomic conversion and DT support. It also contains a bunch of amdgpu and some small ssd13xx fixes. renesas: - atomic conversion - DT support ssd13xx: - dt binding fix for ssd132x - Initialize ssd130x crtc_state to NULL. amdgpu: - Fix RAS support check - RAS fixes - MES fixes - SMU13 fixes - Contiguous memory allocation fix - BACO fixes - GPU reset fixes - Min power limit fixes - GFX11 fixes - USB4/TB hotplug fixes - ARM regression fix - GFX9.4.3 fixes - KASAN/KCSAN stack size check fixes - SR-IOV fixes - SMU14 fixes - PSP13 fixes - Display blend fixes - Flexible array size fixes amdkfd: - GPUVM fix radeon: - Flexible array size fixes" * tag 'drm-next-2023-11-07' of git://anongit.freedesktop.org/drm/drm: (83 commits) drm/amd/display: Enable fast update on blendTF change drm/amd/display: Fix blend LUT programming drm/amd/display: Program plane color setting correctly drm/amdgpu: Query and report boot status drm/amdgpu: Add psp v13 function to query boot status drm/amd/swsmu: remove fw version check in sw_init. drm/amd/swsmu: update smu v14_0_0 driver if and metrics table drm/amdgpu: Add C2PMSG_109/126 reg field shift/masks drm/amdgpu: Optimize the asic type fix code drm/amdgpu: fix GRBM read timeout when do mes_self_test drm/amdgpu: check recovery status of xgmi hive in ras_reset_error_count drm/amd/pm: only check sriov vf flag once when creating hwmon sysfs drm/amdgpu: Attach eviction fence on alloc drm/amdkfd: Improve amdgpu_vm_handle_moved drm/amd/display: Increase frame warning limit with KASAN or KCSAN in dml2 drm/amd/display: Avoid NULL dereference of timing generator drm/amdkfd: Update cache info for GFX 9.4.3 drm/amdkfd: Populate cache info for GFX 9.4.3 drm/amdgpu: don't put MQDs in VRAM on ARM | ARM64 drm/amdgpu/smu13: drop compute workload workaround ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,130 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/renesas,shmobile-lcdc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas SH-Mobile LCD Controller (LCDC)
|
||||
|
||||
maintainers:
|
||||
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r8a7740-lcdc # R-Mobile A1
|
||||
- renesas,sh73a0-lcdc # SH-Mobile AG5
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
description:
|
||||
Only the functional clock is mandatory.
|
||||
Some of the optional clocks are model-dependent (e.g. "video" (a.k.a.
|
||||
"vou" or "dv_clk") is available on R-Mobile A1 only).
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: fck
|
||||
- enum: [ media, lclk, hdmi, video ]
|
||||
- enum: [ media, lclk, hdmi, video ]
|
||||
- enum: [ media, lclk, hdmi, video ]
|
||||
- enum: [ media, lclk, hdmi, video ]
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: LCD port (R-Mobile A1 and SH-Mobile AG5)
|
||||
unevaluatedProperties: false
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: HDMI port (R-Mobile A1 LCDC1 and SH-Mobile AG5)
|
||||
unevaluatedProperties: false
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: MIPI-DSI port (SH-Mobile AG5)
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,r8a7740-lcdc
|
||||
then:
|
||||
properties:
|
||||
ports:
|
||||
properties:
|
||||
port@2: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,sh73a0-lcdc
|
||||
then:
|
||||
properties:
|
||||
ports:
|
||||
required:
|
||||
- port@1
|
||||
- port@2
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7740-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
lcd-controller@fe940000 {
|
||||
compatible = "renesas,r8a7740-lcdc";
|
||||
reg = <0xfe940000 0x4000>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7740_CLK_LCDC0>,
|
||||
<&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk0_clk>,
|
||||
<&vou_clk>;
|
||||
clock-names = "fck", "media", "lclk", "video";
|
||||
power-domains = <&pd_a4lc>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
lcdc0_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -11,10 +11,10 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
- enum:
|
||||
- solomon,ssd1322
|
||||
- solomon,ssd1325
|
||||
- solomon,ssd1327
|
||||
enum:
|
||||
- solomon,ssd1322
|
||||
- solomon,ssd1325
|
||||
- solomon,ssd1327
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@@ -949,6 +949,78 @@ The following tables list existing packed RGB formats.
|
||||
- b\ :sub:`2`
|
||||
- b\ :sub:`1`
|
||||
- b\ :sub:`0`
|
||||
* .. _MEDIA-BUS-FMT-RGB666-2X9-BE:
|
||||
|
||||
- MEDIA_BUS_FMT_RGB666_2X9_BE
|
||||
- 0x1025
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
- r\ :sub:`5`
|
||||
- r\ :sub:`4`
|
||||
- r\ :sub:`3`
|
||||
- r\ :sub:`2`
|
||||
- r\ :sub:`1`
|
||||
- r\ :sub:`0`
|
||||
- g\ :sub:`5`
|
||||
- g\ :sub:`4`
|
||||
- g\ :sub:`3`
|
||||
* -
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
- g\ :sub:`2`
|
||||
- g\ :sub:`1`
|
||||
- g\ :sub:`0`
|
||||
- b\ :sub:`5`
|
||||
- b\ :sub:`4`
|
||||
- b\ :sub:`3`
|
||||
- b\ :sub:`2`
|
||||
- b\ :sub:`1`
|
||||
- b\ :sub:`0`
|
||||
* .. _MEDIA-BUS-FMT-BGR666-1X18:
|
||||
|
||||
- MEDIA_BUS_FMT_BGR666_1X18
|
||||
|
||||
13
MAINTAINERS
13
MAINTAINERS
@@ -7133,7 +7133,7 @@ F: drivers/gpu/host1x/
|
||||
F: include/linux/host1x.h
|
||||
F: include/uapi/drm/tegra_drm.h
|
||||
|
||||
DRM DRIVERS FOR RENESAS
|
||||
DRM DRIVERS FOR RENESAS R-CAR
|
||||
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
M: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
@@ -7144,7 +7144,16 @@ F: Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
|
||||
F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
|
||||
F: Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml
|
||||
F: Documentation/devicetree/bindings/display/renesas,du.yaml
|
||||
F: drivers/gpu/drm/renesas/
|
||||
F: drivers/gpu/drm/renesas/rcar-du/
|
||||
|
||||
DRM DRIVERS FOR RENESAS SHMOBILE
|
||||
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
M: Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
L: linux-renesas-soc@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/display/renesas,shmobile-lcdc.yaml
|
||||
F: drivers/gpu/drm/renesas/shmobile/
|
||||
F: include/linux/platform_data/shmob_drm.h
|
||||
|
||||
DRM DRIVERS FOR ROCKCHIP
|
||||
|
||||
@@ -363,9 +363,6 @@ struct amdgpu_ip_block_version {
|
||||
const struct amd_ip_funcs *funcs;
|
||||
};
|
||||
|
||||
#define HW_REV(_Major, _Minor, _Rev) \
|
||||
((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
|
||||
|
||||
struct amdgpu_ip_block {
|
||||
struct amdgpu_ip_block_status status;
|
||||
const struct amdgpu_ip_block_version *version;
|
||||
|
||||
@@ -425,6 +425,32 @@ validate_fail:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
|
||||
uint32_t domain,
|
||||
struct dma_fence *fence)
|
||||
{
|
||||
int ret = amdgpu_bo_reserve(bo, false);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
|
||||
if (ret)
|
||||
goto unreserve_out;
|
||||
|
||||
ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
|
||||
if (ret)
|
||||
goto unreserve_out;
|
||||
|
||||
dma_resv_add_fence(bo->tbo.base.resv, fence,
|
||||
DMA_RESV_USAGE_BOOKKEEP);
|
||||
|
||||
unreserve_out:
|
||||
amdgpu_bo_unreserve(bo);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
|
||||
{
|
||||
return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
|
||||
@@ -1784,6 +1810,15 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
|
||||
}
|
||||
bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
|
||||
bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
|
||||
} else {
|
||||
mutex_lock(&avm->process_info->lock);
|
||||
if (avm->process_info->eviction_fence &&
|
||||
!dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
|
||||
ret = amdgpu_amdkfd_bo_validate_and_fence(bo, domain,
|
||||
&avm->process_info->eviction_fence->base);
|
||||
mutex_unlock(&avm->process_info->lock);
|
||||
if (ret)
|
||||
goto err_validate_bo;
|
||||
}
|
||||
|
||||
if (offset)
|
||||
@@ -1793,6 +1828,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
|
||||
|
||||
allocate_init_user_pages_failed:
|
||||
err_pin_bo:
|
||||
err_validate_bo:
|
||||
remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
|
||||
drm_vma_node_revoke(&gobj->vma_node, drm_priv);
|
||||
err_node_allow:
|
||||
@@ -1866,10 +1902,6 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
|
||||
if (unlikely(ret))
|
||||
return ret;
|
||||
|
||||
/* The eviction fence should be removed by the last unmap.
|
||||
* TODO: Log an error condition if the bo still has the eviction fence
|
||||
* attached
|
||||
*/
|
||||
amdgpu_amdkfd_remove_eviction_fence(mem->bo,
|
||||
process_info->eviction_fence);
|
||||
pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
|
||||
@@ -1998,19 +2030,6 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
|
||||
if (unlikely(ret))
|
||||
goto out_unreserve;
|
||||
|
||||
if (mem->mapped_to_gpu_memory == 0 &&
|
||||
!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
|
||||
/* Validate BO only once. The eviction fence gets added to BO
|
||||
* the first time it is mapped. Validate will wait for all
|
||||
* background evictions to complete.
|
||||
*/
|
||||
ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
|
||||
if (ret) {
|
||||
pr_debug("Validate failed\n");
|
||||
goto out_unreserve;
|
||||
}
|
||||
}
|
||||
|
||||
list_for_each_entry(entry, &mem->attachments, list) {
|
||||
if (entry->bo_va->base.vm != avm || entry->is_mapped)
|
||||
continue;
|
||||
@@ -2037,10 +2056,6 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
|
||||
mem->mapped_to_gpu_memory);
|
||||
}
|
||||
|
||||
if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
|
||||
dma_resv_add_fence(bo->tbo.base.resv,
|
||||
&avm->process_info->eviction_fence->base,
|
||||
DMA_RESV_USAGE_BOOKKEEP);
|
||||
ret = unreserve_bo_and_vms(&ctx, false, false);
|
||||
|
||||
goto out;
|
||||
@@ -2074,7 +2089,6 @@ int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
|
||||
struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
|
||||
{
|
||||
struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
|
||||
struct amdkfd_process_info *process_info = avm->process_info;
|
||||
unsigned long bo_size = mem->bo->tbo.base.size;
|
||||
struct kfd_mem_attachment *entry;
|
||||
struct bo_vm_reservation_context ctx;
|
||||
@@ -2115,15 +2129,6 @@ int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
|
||||
mem->mapped_to_gpu_memory);
|
||||
}
|
||||
|
||||
/* If BO is unmapped from all VMs, unfence it. It can be evicted if
|
||||
* required.
|
||||
*/
|
||||
if (mem->mapped_to_gpu_memory == 0 &&
|
||||
!amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) &&
|
||||
!mem->bo->tbo.pin_count)
|
||||
amdgpu_amdkfd_remove_eviction_fence(mem->bo,
|
||||
process_info->eviction_fence);
|
||||
|
||||
unreserve_out:
|
||||
unreserve_bo_and_vms(&ctx, false, false);
|
||||
out:
|
||||
@@ -2351,8 +2356,20 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
|
||||
amdgpu_sync_create(&(*mem)->sync);
|
||||
(*mem)->is_imported = true;
|
||||
|
||||
mutex_lock(&avm->process_info->lock);
|
||||
if (avm->process_info->eviction_fence &&
|
||||
!dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
|
||||
ret = amdgpu_amdkfd_bo_validate_and_fence(bo, (*mem)->domain,
|
||||
&avm->process_info->eviction_fence->base);
|
||||
mutex_unlock(&avm->process_info->lock);
|
||||
if (ret)
|
||||
goto err_remove_mem;
|
||||
|
||||
return 0;
|
||||
|
||||
err_remove_mem:
|
||||
remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
|
||||
drm_vma_node_revoke(&obj->vma_node, drm_priv);
|
||||
err_free_mem:
|
||||
kfree(*mem);
|
||||
err_put_obj:
|
||||
|
||||
@@ -29,6 +29,7 @@
|
||||
#include "amdgpu.h"
|
||||
#include "atom.h"
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/acpi.h>
|
||||
@@ -287,6 +288,10 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
|
||||
if (adev->flags & AMD_IS_APU)
|
||||
return false;
|
||||
|
||||
/* ATRM is for on-platform devices only */
|
||||
if (dev_is_removable(&adev->pdev->dev))
|
||||
return false;
|
||||
|
||||
while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
|
||||
if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
|
||||
(pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
|
||||
|
||||
@@ -1117,6 +1117,11 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
|
||||
return r;
|
||||
}
|
||||
|
||||
/* FIXME: In theory this loop shouldn't be needed any more when
|
||||
* amdgpu_vm_handle_moved handles all moved BOs that are reserved
|
||||
* with p->ticket. But removing it caused test regressions, so I'm
|
||||
* leaving it here for now.
|
||||
*/
|
||||
amdgpu_bo_list_for_each_entry(e, p->bo_list) {
|
||||
bo_va = e->bo_va;
|
||||
if (bo_va == NULL)
|
||||
@@ -1131,7 +1136,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
|
||||
return r;
|
||||
}
|
||||
|
||||
r = amdgpu_vm_handle_moved(adev, vm);
|
||||
r = amdgpu_vm_handle_moved(adev, vm, &p->exec.ticket);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
||||
@@ -41,6 +41,7 @@
|
||||
#include <drm/drm_fb_helper.h>
|
||||
#include <drm/drm_probe_helper.h>
|
||||
#include <drm/amdgpu_drm.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/vgaarb.h>
|
||||
#include <linux/vga_switcheroo.h>
|
||||
#include <linux/efi.h>
|
||||
@@ -1073,6 +1074,8 @@ static int amdgpu_device_asic_init(struct amdgpu_device *adev)
|
||||
amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) {
|
||||
amdgpu_psp_wait_for_bootloader(adev);
|
||||
ret = amdgpu_atomfirmware_asic_init(adev, true);
|
||||
/* TODO: check the return val and stop device initialization if boot fails */
|
||||
amdgpu_psp_query_boot_status(adev);
|
||||
return ret;
|
||||
} else {
|
||||
return amdgpu_atom_asic_init(adev->mode_info.atom_context);
|
||||
@@ -2223,7 +2226,6 @@ out:
|
||||
*/
|
||||
static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct drm_device *dev = adev_to_drm(adev);
|
||||
struct pci_dev *parent;
|
||||
int i, r;
|
||||
bool total;
|
||||
@@ -2294,7 +2296,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
|
||||
(amdgpu_is_atpx_hybrid() ||
|
||||
amdgpu_has_atpx_dgpu_power_cntl()) &&
|
||||
((adev->flags & AMD_IS_APU) == 0) &&
|
||||
!pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
|
||||
!dev_is_removable(&adev->pdev->dev))
|
||||
adev->flags |= AMD_IS_PX;
|
||||
|
||||
if (!(adev->flags & AMD_IS_APU)) {
|
||||
@@ -3962,13 +3964,23 @@ int amdgpu_device_init(struct amdgpu_device *adev,
|
||||
}
|
||||
}
|
||||
} else {
|
||||
tmp = amdgpu_reset_method;
|
||||
/* It should do a default reset when loading or reloading the driver,
|
||||
* regardless of the module parameter reset_method.
|
||||
*/
|
||||
amdgpu_reset_method = AMD_RESET_METHOD_NONE;
|
||||
r = amdgpu_asic_reset(adev);
|
||||
amdgpu_reset_method = tmp;
|
||||
switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
|
||||
case IP_VERSION(13, 0, 0):
|
||||
case IP_VERSION(13, 0, 7):
|
||||
case IP_VERSION(13, 0, 10):
|
||||
r = psp_gpu_reset(adev);
|
||||
break;
|
||||
default:
|
||||
tmp = amdgpu_reset_method;
|
||||
/* It should do a default reset when loading or reloading the driver,
|
||||
* regardless of the module parameter reset_method.
|
||||
*/
|
||||
amdgpu_reset_method = AMD_RESET_METHOD_NONE;
|
||||
r = amdgpu_asic_reset(adev);
|
||||
amdgpu_reset_method = tmp;
|
||||
break;
|
||||
}
|
||||
|
||||
if (r) {
|
||||
dev_err(adev->dev, "asic reset on init failed\n");
|
||||
goto failed;
|
||||
@@ -4132,7 +4144,7 @@ fence_driver_init:
|
||||
|
||||
px = amdgpu_device_supports_px(ddev);
|
||||
|
||||
if (px || (!pci_is_thunderbolt_attached(adev->pdev) &&
|
||||
if (px || (!dev_is_removable(&adev->pdev->dev) &&
|
||||
apple_gmux_detect(NULL, NULL)))
|
||||
vga_switcheroo_register_client(adev->pdev,
|
||||
&amdgpu_switcheroo_ops, px);
|
||||
@@ -4282,7 +4294,7 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev)
|
||||
|
||||
px = amdgpu_device_supports_px(adev_to_drm(adev));
|
||||
|
||||
if (px || (!pci_is_thunderbolt_attached(adev->pdev) &&
|
||||
if (px || (!dev_is_removable(&adev->pdev->dev) &&
|
||||
apple_gmux_detect(NULL, NULL)))
|
||||
vga_switcheroo_unregister_client(adev->pdev);
|
||||
|
||||
@@ -5566,10 +5578,6 @@ skip_hw_reset:
|
||||
drm_sched_start(&ring->sched, true);
|
||||
}
|
||||
|
||||
if (adev->enable_mes &&
|
||||
amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3))
|
||||
amdgpu_mes_self_test(tmp_adev);
|
||||
|
||||
if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled)
|
||||
drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
|
||||
|
||||
|
||||
@@ -99,6 +99,7 @@
|
||||
MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
|
||||
|
||||
#define mmRCC_CONFIG_MEMSIZE 0xde3
|
||||
#define mmMP0_SMN_C2PMSG_33 0x16061
|
||||
#define mmMM_INDEX 0x0
|
||||
#define mmMM_INDEX_HI 0x6
|
||||
#define mmMM_DATA 0x1
|
||||
@@ -239,8 +240,26 @@ static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev,
|
||||
static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,
|
||||
uint8_t *binary)
|
||||
{
|
||||
uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
|
||||
int ret = 0;
|
||||
uint64_t vram_size;
|
||||
u32 msg;
|
||||
int i, ret = 0;
|
||||
|
||||
/* It can take up to a second for IFWI init to complete on some dGPUs,
|
||||
* but generally it should be in the 60-100ms range. Normally this starts
|
||||
* as soon as the device gets power so by the time the OS loads this has long
|
||||
* completed. However, when a card is hotplugged via e.g., USB4, we need to
|
||||
* wait for this to complete. Once the C2PMSG is updated, we can
|
||||
* continue.
|
||||
*/
|
||||
if (dev_is_removable(&adev->pdev->dev)) {
|
||||
for (i = 0; i < 1000; i++) {
|
||||
msg = RREG32(mmMP0_SMN_C2PMSG_33);
|
||||
if (msg & 0x80000000)
|
||||
break;
|
||||
msleep(1);
|
||||
}
|
||||
}
|
||||
vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
|
||||
|
||||
if (vram_size) {
|
||||
uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
|
||||
@@ -2449,6 +2468,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
|
||||
if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(4, 8, 0))
|
||||
adev->gmc.xgmi.supported = true;
|
||||
|
||||
if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
|
||||
adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 4, 0);
|
||||
|
||||
/* set NBIO version */
|
||||
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
|
||||
case IP_VERSION(6, 1, 0):
|
||||
|
||||
@@ -409,7 +409,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
|
||||
if (!r)
|
||||
r = amdgpu_vm_clear_freed(adev, vm, NULL);
|
||||
if (!r)
|
||||
r = amdgpu_vm_handle_moved(adev, vm);
|
||||
r = amdgpu_vm_handle_moved(adev, vm, ticket);
|
||||
|
||||
if (r && r != -EBUSY)
|
||||
DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
|
||||
|
||||
@@ -2041,6 +2041,14 @@ static const struct pci_device_id pciidlist[] = {
|
||||
|
||||
MODULE_DEVICE_TABLE(pci, pciidlist);
|
||||
|
||||
static const struct amdgpu_asic_type_quirk asic_type_quirks[] = {
|
||||
/* differentiate between P10 and P11 asics with the same DID */
|
||||
{0x67FF, 0xE3, CHIP_POLARIS10},
|
||||
{0x67FF, 0xE7, CHIP_POLARIS10},
|
||||
{0x67FF, 0xF3, CHIP_POLARIS10},
|
||||
{0x67FF, 0xF7, CHIP_POLARIS10},
|
||||
};
|
||||
|
||||
static const struct drm_driver amdgpu_kms_driver;
|
||||
|
||||
static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
|
||||
@@ -2083,6 +2091,22 @@ static void amdgpu_init_debug_options(struct amdgpu_device *adev)
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) {
|
||||
if (pdev->device == asic_type_quirks[i].device &&
|
||||
pdev->revision == asic_type_quirks[i].revision) {
|
||||
flags &= ~AMD_ASIC_MASK;
|
||||
flags |= asic_type_quirks[i].type;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return flags;
|
||||
}
|
||||
|
||||
static int amdgpu_pci_probe(struct pci_dev *pdev,
|
||||
const struct pci_device_id *ent)
|
||||
{
|
||||
@@ -2110,15 +2134,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
|
||||
"See modparam exp_hw_support\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
/* differentiate between P10 and P11 asics with the same DID */
|
||||
if (pdev->device == 0x67FF &&
|
||||
(pdev->revision == 0xE3 ||
|
||||
pdev->revision == 0xE7 ||
|
||||
pdev->revision == 0xF3 ||
|
||||
pdev->revision == 0xF7)) {
|
||||
flags &= ~AMD_ASIC_MASK;
|
||||
flags |= CHIP_POLARIS10;
|
||||
}
|
||||
|
||||
flags = amdgpu_fix_asic_type(pdev, flags);
|
||||
|
||||
/* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
|
||||
* however, SME requires an indirect IOMMU mapping because the encryption
|
||||
|
||||
@@ -385,9 +385,11 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
|
||||
struct amdgpu_ring *ring = &kiq->ring;
|
||||
u32 domain = AMDGPU_GEM_DOMAIN_GTT;
|
||||
|
||||
#if !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
|
||||
/* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */
|
||||
if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 0, 0))
|
||||
domain |= AMDGPU_GEM_DOMAIN_VRAM;
|
||||
#endif
|
||||
|
||||
/* create MQD for KIQ */
|
||||
if (!adev->enable_mes_kiq && !ring->mqd_obj) {
|
||||
|
||||
@@ -557,8 +557,20 @@ static void amdgpu_mes_queue_init_mqd(struct amdgpu_device *adev,
|
||||
mqd_prop.hqd_queue_priority = p->hqd_queue_priority;
|
||||
mqd_prop.hqd_active = false;
|
||||
|
||||
if (p->queue_type == AMDGPU_RING_TYPE_GFX ||
|
||||
p->queue_type == AMDGPU_RING_TYPE_COMPUTE) {
|
||||
mutex_lock(&adev->srbm_mutex);
|
||||
amdgpu_gfx_select_me_pipe_q(adev, p->ring->me, p->ring->pipe, 0, 0, 0);
|
||||
}
|
||||
|
||||
mqd_mgr->init_mqd(adev, q->mqd_cpu_ptr, &mqd_prop);
|
||||
|
||||
if (p->queue_type == AMDGPU_RING_TYPE_GFX ||
|
||||
p->queue_type == AMDGPU_RING_TYPE_COMPUTE) {
|
||||
amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, 0);
|
||||
mutex_unlock(&adev->srbm_mutex);
|
||||
}
|
||||
|
||||
amdgpu_bo_unreserve(q->mqd_obj);
|
||||
}
|
||||
|
||||
@@ -994,9 +1006,13 @@ int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
|
||||
switch (queue_type) {
|
||||
case AMDGPU_RING_TYPE_GFX:
|
||||
ring->funcs = adev->gfx.gfx_ring[0].funcs;
|
||||
ring->me = adev->gfx.gfx_ring[0].me;
|
||||
ring->pipe = adev->gfx.gfx_ring[0].pipe;
|
||||
break;
|
||||
case AMDGPU_RING_TYPE_COMPUTE:
|
||||
ring->funcs = adev->gfx.compute_ring[0].funcs;
|
||||
ring->me = adev->gfx.compute_ring[0].me;
|
||||
ring->pipe = adev->gfx.compute_ring[0].pipe;
|
||||
break;
|
||||
case AMDGPU_RING_TYPE_SDMA:
|
||||
ring->funcs = adev->sdma.instance[0].ring.funcs;
|
||||
|
||||
@@ -2120,6 +2120,21 @@ int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
int amdgpu_psp_query_boot_status(struct amdgpu_device *adev)
|
||||
{
|
||||
struct psp_context *psp = &adev->psp;
|
||||
int ret = 0;
|
||||
|
||||
if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU))
|
||||
return 0;
|
||||
|
||||
if (psp->funcs &&
|
||||
psp->funcs->query_boot_status)
|
||||
ret = psp->funcs->query_boot_status(psp);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int psp_hw_start(struct psp_context *psp)
|
||||
{
|
||||
struct amdgpu_device *adev = psp->adev;
|
||||
|
||||
@@ -134,6 +134,7 @@ struct psp_funcs {
|
||||
int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
|
||||
int (*vbflash_stat)(struct psp_context *psp);
|
||||
int (*fatal_error_recovery_quirk)(struct psp_context *psp);
|
||||
int (*query_boot_status)(struct psp_context *psp);
|
||||
};
|
||||
|
||||
struct ta_funcs {
|
||||
@@ -537,4 +538,6 @@ int is_psp_fw_valid(struct psp_bin_desc bin);
|
||||
|
||||
int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev);
|
||||
|
||||
int amdgpu_psp_query_boot_status(struct amdgpu_device *adev);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1222,6 +1222,8 @@ int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
|
||||
struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
|
||||
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
|
||||
const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
|
||||
struct amdgpu_hive_info *hive;
|
||||
int hive_ras_recovery = 0;
|
||||
|
||||
if (!block_obj || !block_obj->hw_ops) {
|
||||
dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
|
||||
@@ -1229,15 +1231,22 @@ int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
/* skip ras error reset in gpu reset */
|
||||
if ((amdgpu_in_reset(adev) || atomic_read(&ras->in_recovery)) &&
|
||||
mca_funcs && mca_funcs->mca_set_debug_mode)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (!amdgpu_ras_is_supported(adev, block) ||
|
||||
!amdgpu_ras_get_mca_debug_mode(adev))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
hive = amdgpu_get_xgmi_hive(adev);
|
||||
if (hive) {
|
||||
hive_ras_recovery = atomic_read(&hive->ras_recovery);
|
||||
amdgpu_put_xgmi_hive(hive);
|
||||
}
|
||||
|
||||
/* skip ras error reset in gpu reset */
|
||||
if ((amdgpu_in_reset(adev) || atomic_read(&ras->in_recovery) ||
|
||||
hive_ras_recovery) &&
|
||||
mca_funcs && mca_funcs->mca_set_debug_mode)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (block_obj->hw_ops->reset_ras_error_count)
|
||||
block_obj->hw_ops->reset_ras_error_count(adev);
|
||||
|
||||
|
||||
@@ -166,8 +166,12 @@ static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev,
|
||||
}
|
||||
}
|
||||
|
||||
if (reset)
|
||||
if (reset) {
|
||||
/* use mode-2 reset for poison consumption */
|
||||
if (!entry)
|
||||
con->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET;
|
||||
amdgpu_ras_reset_gpu(adev);
|
||||
}
|
||||
}
|
||||
|
||||
kfree(err_data->err_addr);
|
||||
|
||||
@@ -1373,6 +1373,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
|
||||
*
|
||||
* @adev: amdgpu_device pointer
|
||||
* @vm: requested vm
|
||||
* @ticket: optional reservation ticket used to reserve the VM
|
||||
*
|
||||
* Make sure all BOs which are moved are updated in the PTs.
|
||||
*
|
||||
@@ -1382,11 +1383,12 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
|
||||
* PTs have to be reserved!
|
||||
*/
|
||||
int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
|
||||
struct amdgpu_vm *vm)
|
||||
struct amdgpu_vm *vm,
|
||||
struct ww_acquire_ctx *ticket)
|
||||
{
|
||||
struct amdgpu_bo_va *bo_va;
|
||||
struct dma_resv *resv;
|
||||
bool clear;
|
||||
bool clear, unlock;
|
||||
int r;
|
||||
|
||||
spin_lock(&vm->status_lock);
|
||||
@@ -1409,17 +1411,24 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
|
||||
spin_unlock(&vm->status_lock);
|
||||
|
||||
/* Try to reserve the BO to avoid clearing its ptes */
|
||||
if (!adev->debug_vm && dma_resv_trylock(resv))
|
||||
if (!adev->debug_vm && dma_resv_trylock(resv)) {
|
||||
clear = false;
|
||||
unlock = true;
|
||||
/* The caller is already holding the reservation lock */
|
||||
} else if (ticket && dma_resv_locking_ctx(resv) == ticket) {
|
||||
clear = false;
|
||||
unlock = false;
|
||||
/* Somebody else is using the BO right now */
|
||||
else
|
||||
} else {
|
||||
clear = true;
|
||||
unlock = false;
|
||||
}
|
||||
|
||||
r = amdgpu_vm_bo_update(adev, bo_va, clear);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
if (!clear)
|
||||
if (unlock)
|
||||
dma_resv_unlock(resv);
|
||||
spin_lock(&vm->status_lock);
|
||||
}
|
||||
|
||||
@@ -443,7 +443,8 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
|
||||
struct amdgpu_vm *vm,
|
||||
struct dma_fence **fence);
|
||||
int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
|
||||
struct amdgpu_vm *vm);
|
||||
struct amdgpu_vm *vm,
|
||||
struct ww_acquire_ctx *ticket);
|
||||
void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
|
||||
struct amdgpu_vm *vm, struct amdgpu_bo *bo);
|
||||
int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user